perf fixes

Linus,

Please pull the latest perf-urgent-for-linus git tree from:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-for-linus

HEAD: 26a4f3c08de49c1437a7b7f97693cf22d8c31656 perf/x86: disable PEBS on a guest entry.

Thanks,

Ingo

------------------>
Borislav Petkov (1):
perf, x86: Fix uncore_types_exit section mismatch

Gleb Natapov (1):
perf/x86: disable PEBS on a guest entry.

Yan, Zheng (2):
perf/x86: Fixes for Nehalem-EX uncore driver perf/x86: Add Intel Westmere-EX uncore support

 arch/x86/kernel/cpu/perf_event_intel.c        |  10 +-
 arch/x86/kernel/cpu/perf_event_intel_uncore.c | 253 ++++++++++++++------------
 arch/x86/kernel/cpu/perf_event_intel_uncore.h |  46 +++--
 3 files changed, 165 insertions(+), 144 deletions(-)

index 3823669..7f2739e 100644
@@ -1522,8 +1522,16 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
 	arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
 	arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
 	arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
+	/*
+	 * If PMU counter has PEBS enabled it is not enough to disable counter
+	 * on a guest entry since PEBS memory write can overshoot guest entry
+	 * and corrupt guest memory. Disabling PEBS solves the problem.
+	 */
+	arr[1].msr = MSR_IA32_PEBS_ENABLE;
+	arr[1].host = cpuc->pebs_enabled;
+	arr[1].guest = 0;
 
-	*nr = 1;
+	*nr = 2;
 	return arr;
 }
 

The missing description:

Small fixes for merge window fallout, plus a (smallish) hw-enablement patch for the new uncore PMU driver, enabling Intel Westmere-EX support.

Thanks,

Ingo