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"Nuke 386-DX/SX support" changes for v3.8

GIT PULL Ingo Molnar 6 participants 8 messages Dec 11, 2012 – Dec 13, 2012

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Ingo Molnar

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#0 lore raw

Linus,

Please consider pulling the latest x86-nuke386-for-linus git tree from:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-nuke386-for-linus

HEAD: 11af32b69ef7ee64c7d8848cad71a6f3749d9e37 x86, 386 removal: Document Nx586 as a 386 and thus unsupported

This tree removes ancient-386-CPUs support and thus zaps quite a bit of complexity:

   24 files changed, 56 insertions(+), 425 deletions(-)

... which complexity has plagued us with extra work whenever we wanted to change SMP primitives, for years.

Unfortunately there's a nostalgic cost: your old original 386 DX33 system from early 1991 won't be able to boot modern Linux kernels anymore. Sniff.

Thanks,

Ingo

------------------>
H. Peter Anvin (9):
x86, 386 removal: Remove CONFIG_M386 from Kconfig x86, 386 removal: Remove CONFIG_CMPXCHG
x86, 386 removal: Remove CONFIG_XADD
x86, 386 removal: Remove CONFIG_BSWAP
x86, 386 removal: Remove CONFIG_INVLPG
x86, 386 removal: Remove CONFIG_X86_WP_WORKS_OK x86, 386 removal: Remove CONFIG_X86_POPAD_OK
x86, cleanups: Simplify sync_core() in the case of no CPUID x86, 386 removal: Document Nx586 as a 386 and thus unsupported

 arch/x86/Kconfig                  | 11 ++----
 arch/x86/Kconfig.cpu              | 73 +++++++++++----------------------------
 arch/x86/Makefile_32.cpu          |  1 -
 arch/x86/include/asm/atomic.h     | 16 ---------
 arch/x86/include/asm/cmpxchg_32.h | 55 -----------------------------
 arch/x86/include/asm/cpufeature.h |  6 ----
 arch/x86/include/asm/futex.h      | 12 -------
 arch/x86/include/asm/local.h      | 18 +---------
 arch/x86/include/asm/module.h     |  2 --
 arch/x86/include/asm/percpu.h     |  3 --
 arch/x86/include/asm/processor.h  | 33 ++++++++++++------
 arch/x86/include/asm/swab.h       | 29 ++--------------
 arch/x86/include/asm/tlbflush.h   |  3 --
 arch/x86/include/asm/uaccess.h    | 42 ----------------------
 arch/x86/kernel/cpu/amd.c         |  3 --
 arch/x86/kernel/cpu/bugs.c        | 41 ++--------------------
 arch/x86/kernel/cpu/intel.c       |  4 ---
 arch/x86/lib/Makefile             |  1 -
 arch/x86/lib/cmpxchg.c            | 54 -----------------------------
 arch/x86/lib/usercopy_32.c        | 57 ------------------------------
 arch/x86/mm/init_32.c             |  5 +--
 arch/x86/mm/tlb.c                 |  8 ++---
 arch/x86/um/Kconfig               |  2 +-
 arch/x86/xen/Kconfig              |  2 +-
 24 files changed, 56 insertions(+), 425 deletions(-)
 delete mode 100644 arch/x86/lib/cmpxchg.c
arch/x86/Kconfig +3 -8
index 46c3bff..631b298 100644
@@ -69,8 +69,8 @@ config X86
 	select HAVE_PERF_USER_STACK_DUMP
 	select HAVE_DEBUG_KMEMLEAK
 	select ANON_INODES
-	select HAVE_ALIGNED_STRUCT_PAGE if SLUB && !M386
-	select HAVE_CMPXCHG_LOCAL if !M386
+	select HAVE_ALIGNED_STRUCT_PAGE if SLUB
+	select HAVE_CMPXCHG_LOCAL
 	select HAVE_CMPXCHG_DOUBLE
 	select HAVE_ARCH_KMEMCHECK
 	select HAVE_USER_RETURN_NOTIFIER

@@ -171,13 +171,8 @@ config ARCH_MAY_HAVE_PC_FDC
 	def_bool y
 	depends on ISA_DMA_API
 
-config RWSEM_GENERIC_SPINLOCK
-	def_bool y
-	depends on !X86_XADD
-
 config RWSEM_XCHGADD_ALGORITHM
 	def_bool y
-	depends on X86_XADD
 
 config GENERIC_CALIBRATE_DELAY
 	def_bool y

@@ -1100,7 +1095,7 @@ config HIGHMEM4G
 
 config HIGHMEM64G
 	bool "64GB"
-	depends on !M386 && !M486
+	depends on !M486
 	select X86_PAE
 	---help---
 	  Select this if you have a 32-bit processor and more than 4
arch/x86/Kconfig.cpu +20 -53

136 lines not on this page · raw message

arch/x86/Makefile_32.cpu +0 -1
index 86cee7b..6647ed4 100644
@@ -10,7 +10,6 @@ tune		= $(call cc-option,-mcpu=$(1),$(2))
 endif
 
 align := $(cc-option-align)
-cflags-$(CONFIG_M386)		+= -march=i386
 cflags-$(CONFIG_M486)		+= -march=i486
 cflags-$(CONFIG_M586)		+= -march=i586
 cflags-$(CONFIG_M586TSC)	+= -march=i586
arch/x86/include/asm/atomic.h +0 -16
index b6c3b82..722aa3b 100644
@@ -172,23 +172,7 @@ static inline int atomic_add_negative(int i, atomic_t *v)
  */
 static inline int atomic_add_return(int i, atomic_t *v)
 {
-#ifdef CONFIG_M386
-	int __i;
-	unsigned long flags;
-	if (unlikely(boot_cpu_data.x86 <= 3))
-		goto no_xadd;
-#endif
-	/* Modern 486+ processor */
 	return i + xadd(&v->counter, i);
-
-#ifdef CONFIG_M386
-no_xadd: /* Legacy 386 processor */
-	raw_local_irq_save(flags);
-	__i = atomic_read(v);
-	atomic_set(v, i + __i);
-	raw_local_irq_restore(flags);
-	return i + __i;
-#endif
 }
 
 /**
arch/x86/include/asm/cmpxchg_32.h +0 -55

68 lines not on this page · raw message

arch/x86/include/asm/cpufeature.h +0 -6
index 8c297aa..ff8dd62 100644
@@ -312,12 +312,6 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_cx16		boot_cpu_has(X86_FEATURE_CX16)
 #define cpu_has_eager_fpu	boot_cpu_has(X86_FEATURE_EAGER_FPU)
 
-#if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
-# define cpu_has_invlpg		1
-#else
-# define cpu_has_invlpg		(boot_cpu_data.x86 > 3)
-#endif
-
 #ifdef CONFIG_X86_64
 
 #undef  cpu_has_vme
arch/x86/include/asm/futex.h +0 -12
index f373046..be27ba1 100644
@@ -55,12 +55,6 @@ static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
 	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
 		return -EFAULT;
 
-#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
-	/* Real i386 machines can only support FUTEX_OP_SET */
-	if (op != FUTEX_OP_SET && boot_cpu_data.x86 == 3)
-		return -ENOSYS;
-#endif
-
 	pagefault_disable();
 
 	switch (op) {

@@ -118,12 +112,6 @@ static inline int futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
 {
 	int ret = 0;
 
-#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_BSWAP)
-	/* Real i386 machines have no cmpxchg instruction */
-	if (boot_cpu_data.x86 == 3)
-		return -ENOSYS;
-#endif
-
 	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
 		return -EFAULT;
arch/x86/include/asm/local.h +1 -17
index c8bed0d..2d89e39 100644
@@ -124,27 +124,11 @@ static inline int local_add_negative(long i, local_t *l)
  */
 static inline long local_add_return(long i, local_t *l)
 {
-	long __i;
-#ifdef CONFIG_M386
-	unsigned long flags;
-	if (unlikely(boot_cpu_data.x86 <= 3))
-		goto no_xadd;
-#endif
-	/* Modern 486+ processor */
-	__i = i;
+	long __i = i;
 	asm volatile(_ASM_XADD "%0, %1;"
 		     : "+r" (i), "+m" (l->a.counter)
 		     : : "memory");
 	return i + __i;
-
-#ifdef CONFIG_M386
-no_xadd: /* Legacy 386 processor */
-	local_irq_save(flags);
-	__i = local_read(l);
-	local_set(l, i + __i);
-	local_irq_restore(flags);
-	return i + __i;
-#endif
 }
 
 static inline long local_sub_return(long i, local_t *l)
arch/x86/include/asm/module.h +0 -2
index 9eae775..e3b7819 100644
@@ -5,8 +5,6 @@
 
 #ifdef CONFIG_X86_64
 /* X86_64 does not define MODULE_PROC_FAMILY */
-#elif defined CONFIG_M386
-#define MODULE_PROC_FAMILY "386 "
 #elif defined CONFIG_M486
 #define MODULE_PROC_FAMILY "486 "
 #elif defined CONFIG_M586
arch/x86/include/asm/percpu.h +0 -3
index 1104afa..0da5200 100644
@@ -406,7 +406,6 @@ do {									\
 #define this_cpu_xchg_2(pcp, nval)	percpu_xchg_op(pcp, nval)
 #define this_cpu_xchg_4(pcp, nval)	percpu_xchg_op(pcp, nval)
 
-#ifndef CONFIG_M386
 #define __this_cpu_add_return_1(pcp, val) percpu_add_return_op(pcp, val)
 #define __this_cpu_add_return_2(pcp, val) percpu_add_return_op(pcp, val)
 #define __this_cpu_add_return_4(pcp, val) percpu_add_return_op(pcp, val)

@@ -421,8 +420,6 @@ do {									\
 #define this_cpu_cmpxchg_2(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)
 #define this_cpu_cmpxchg_4(pcp, oval, nval)	percpu_cmpxchg_op(pcp, oval, nval)
 
-#endif /* !CONFIG_M386 */
-
 #ifdef CONFIG_X86_CMPXCHG64
 #define percpu_cmpxchg8b_double(pcp1, pcp2, o1, o2, n1, n2)		\
 ({									\
arch/x86/include/asm/processor.h +22 -11
index ad1fc85..b0d3e73 100644
@@ -672,18 +672,29 @@ static inline void sync_core(void)
 {
 	int tmp;
 
-#if defined(CONFIG_M386) || defined(CONFIG_M486)
-	if (boot_cpu_data.x86 < 5)
-		/* There is no speculative execution.
-		 * jmp is a barrier to prefetching. */
-		asm volatile("jmp 1f\n1:\n" ::: "memory");
-	else
+#ifdef CONFIG_M486
+	/*
+	 * Do a CPUID if available, otherwise do a jump.  The jump
+	 * can conveniently enough be the jump around CPUID.
+	 */
+	asm volatile("cmpl %2,%1\n\t"
+		     "jl 1f\n\t"
+		     "cpuid\n"
+		     "1:"
+		     : "=a" (tmp)
+		     : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "0" (1)
+		     : "ebx", "ecx", "edx", "memory");
+#else
+	/*
+	 * CPUID is a barrier to speculative execution.
+	 * Prefetched instructions are automatically
+	 * invalidated when modified.
+	 */
+	asm volatile("cpuid"
+		     : "=a" (tmp)
+		     : "0" (1)
+		     : "ebx", "ecx", "edx", "memory");
 #endif
-		/* cpuid is a barrier to speculative execution.
-		 * Prefetched instructions are automatically
-		 * invalidated when modified. */
-		asm volatile("cpuid" : "=a" (tmp) : "0" (1)
-			     : "ebx", "ecx", "edx", "memory");
 }
 
 static inline void __monitor(const void *eax, unsigned long ecx,
arch/x86/include/asm/swab.h +2 -27
index 557cd9f..7f235c7 100644
@@ -6,22 +6,7 @@
 
 static inline __attribute_const__ __u32 __arch_swab32(__u32 val)
 {
-#ifdef __i386__
-# ifdef CONFIG_X86_BSWAP
-	asm("bswap %0" : "=r" (val) : "0" (val));
-# else
-	asm("xchgb %b0,%h0\n\t"	/* swap lower bytes	*/
-	    "rorl $16,%0\n\t"	/* swap words		*/
-	    "xchgb %b0,%h0"	/* swap higher bytes	*/
-	    : "=q" (val)
-	    : "0" (val));
-# endif
-
-#else /* __i386__ */
-	asm("bswapl %0"
-	    : "=r" (val)
-	    : "0" (val));
-#endif
+	asm("bswapl %0" : "=r" (val) : "0" (val));
 	return val;
 }
 #define __arch_swab32 __arch_swab32

@@ -37,22 +22,12 @@ static inline __attribute_const__ __u64 __arch_swab64(__u64 val)
 		__u64 u;
 	} v;
 	v.u = val;
-# ifdef CONFIG_X86_BSWAP
 	asm("bswapl %0 ; bswapl %1 ; xchgl %0,%1"
 	    : "=r" (v.s.a), "=r" (v.s.b)
 	    : "0" (v.s.a), "1" (v.s.b));
-# else
-	v.s.a = __arch_swab32(v.s.a);
-	v.s.b = __arch_swab32(v.s.b);
-	asm("xchgl %0,%1"
-	    : "=r" (v.s.a), "=r" (v.s.b)
-	    : "0" (v.s.a), "1" (v.s.b));
-# endif
 	return v.u;
 #else /* __i386__ */
-	asm("bswapq %0"
-	    : "=r" (val)
-	    : "0" (val));
+	asm("bswapq %0" : "=r" (val) : "0" (val));
 	return val;
 #endif
 }
arch/x86/include/asm/tlbflush.h +0 -3
index 74a4433..0fee48e 100644
@@ -56,10 +56,7 @@ static inline void __flush_tlb_all(void)
 
 static inline void __flush_tlb_one(unsigned long addr)
 {
-	if (cpu_has_invlpg)
 		__flush_tlb_single(addr);
-	else
-		__flush_tlb();
 }
 
 #define TLB_FLUSH_ALL	-1UL
arch/x86/include/asm/uaccess.h +0 -42

66 lines not on this page · raw message

arch/x86/kernel/cpu/amd.c +0 -3
index 1b7d165..a025d8c 100644
@@ -753,9 +753,6 @@ static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
 
 static void __cpuinit cpu_set_tlb_flushall_shift(struct cpuinfo_x86 *c)
 {
-	if (!cpu_has_invlpg)
-		return;
-
 	tlb_flushall_shift = 5;
 
 	if (c->x86 <= 0x11)
arch/x86/kernel/cpu/bugs.c +2 -39

62 lines not on this page · raw message

arch/x86/kernel/cpu/intel.c +0 -4
index 198e019..fcaabd0 100644
@@ -612,10 +612,6 @@ static void __cpuinit intel_tlb_lookup(const unsigned char desc)
 
 static void __cpuinit intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
 {
-	if (!cpu_has_invlpg) {
-		tlb_flushall_shift = -1;
-		return;
-	}
 	switch ((c->x86 << 8) + c->x86_model) {
 	case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
 	case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
arch/x86/lib/Makefile +0 -1
index b00f678..96b2c66 100644
@@ -32,7 +32,6 @@ ifeq ($(CONFIG_X86_32),y)
         lib-y += checksum_32.o
         lib-y += strstr_32.o
         lib-y += string_32.o
-        lib-y += cmpxchg.o
 ifneq ($(CONFIG_X86_CMPXCHG64),y)
         lib-y += cmpxchg8b_emu.o atomic64_386_32.o
 endif
arch/x86/lib/cmpxchg.c deleted +0 -54

54 lines not on this page · raw message

arch/x86/lib/usercopy_32.c +0 -57

63 lines not on this page · raw message

arch/x86/mm/init_32.c +1 -4
index 11a5800..745d66b 100644
@@ -715,10 +715,7 @@ static void __init test_wp_bit(void)
 
 	if (!boot_cpu_data.wp_works_ok) {
 		printk(KERN_CONT "No.\n");
-#ifdef CONFIG_X86_WP_WORKS_OK
-		panic(
-  "This kernel doesn't support CPU's with broken WP. Recompile it for a 386!");
-#endif
+		panic("Linux doesn't support CPUs with broken WP.");
 	} else {
 		printk(KERN_CONT "Ok.\n");
 	}
arch/x86/mm/tlb.c +3 -5
index 60f926c..13a6b29 100644
@@ -104,7 +104,7 @@ static void flush_tlb_func(void *info)
 		return;
 
 	if (this_cpu_read(cpu_tlbstate.state) == TLBSTATE_OK) {
-		if (f->flush_end == TLB_FLUSH_ALL || !cpu_has_invlpg)
+		if (f->flush_end == TLB_FLUSH_ALL)
 			local_flush_tlb();
 		else if (!f->flush_end)
 			__flush_tlb_single(f->flush_start);

@@ -337,10 +337,8 @@ static const struct file_operations fops_tlbflush = {
 
 static int __cpuinit create_tlb_flushall_shift(void)
 {
-	if (cpu_has_invlpg) {
-		debugfs_create_file("tlb_flushall_shift", S_IRUSR | S_IWUSR,
-			arch_debugfs_dir, NULL, &fops_tlbflush);
-	}
+	debugfs_create_file("tlb_flushall_shift", S_IRUSR | S_IWUSR,
+			    arch_debugfs_dir, NULL, &fops_tlbflush);
 	return 0;
 }
 late_initcall(create_tlb_flushall_shift);
arch/x86/um/Kconfig +1 -1
index 0761175..b0c30da 100644
@@ -31,7 +31,7 @@ config X86_64
 	select MODULES_USE_ELF_RELA
 
 config RWSEM_XCHGADD_ALGORITHM
-	def_bool X86_XADD && 64BIT
+	def_bool 64BIT
 
 config RWSEM_GENERIC_SPINLOCK
 	def_bool !RWSEM_XCHGADD_ALGORITHM
arch/x86/xen/Kconfig +1 -1
index fdce49c..9a6775c 100644
@@ -7,7 +7,7 @@ config XEN
 	select PARAVIRT
 	select PARAVIRT_CLOCK
 	depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS)
-	depends on X86_CMPXCHG && X86_TSC
+	depends on X86_TSC
 	help
 	  This is the Linux Xen port.  Enabling this will allow the
 	  kernel to boot in a paravirtualized environment under the
#1 lore raw
Quoted 3 lines · Ingo Molnar

This tree removes ancient-386-CPUs support and thus zaps quite a bit of complexity:

Btw, I think we should probably at least consider taking this one step further, and remove the dear old FPU emulation support too. Remove CONFIG_MATH_EMULATION and all of arch/x86/math-emu, along with a lot of small special cases.

Or do people still use the 486SX?

Now, the math emulation hasn't been all that fundamentally problematic (compared to lack of xadd etc), but it does result in some complexities in exception handling and ptrace (grep for HAVE_HWFP or "hard_math" or a number of other magic things). None of which have likely been tested at all in the last ten years, so who knows if it actually *works* or not.

Maybe somebody could try booting with "no387". Does it actually work?

Linus

reviewer
#2 lore raw
Quoted 12 lines · Linus Torvalds
Quoted 3 lines · Ingo Molnar

This tree removes ancient-386-CPUs support and thus zaps quite a bit of complexity:

Btw, I think we should probably at least consider taking this one step further, and remove the dear old FPU emulation support too. Remove CONFIG_MATH_EMULATION and all of arch/x86/math-emu, along with a lot of small special cases.

Or do people still use the 486SX?

Quoted 9 lines

Now, the math emulation hasn't been all that fundamentally problematic (compared to lack of xadd etc), but it does result in some complexities in exception handling and ptrace (grep for HAVE_HWFP or "hard_math" or a number of other magic things). None of which have likely been tested at all in the last ten years, so who knows if it actually *works* or not.

Maybe somebody could try booting with "no387". Does it actually work?

It builds and boots, at least. I'm currently installing Red Hat 4.1 in a VM so I can test to see if it does anything more than that. It doesn't get in the way the same case the old 386 bits does, so I'm more reluctant to remove it, but it does touch a lot of paths.

There were a *bunch* of embedded 486 clones made, some still in production as far as I know, and I wouldn't be surprised if some of them lacked FPU. I guess we'll see.

-hpa

Signature · 2 lines
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.
reviewer
#3 lore raw
Quoted 6 lines · H. Peter Anvin

It builds and boots, at least. I'm currently installing Red Hat 4.1 in a VM so I can test to see if it does anything more than that. It doesn't get in the way the same case the old 386 bits does, so I'm more reluctant to remove it, but it does touch a lot of paths.

Well... it turns out to boot and run Red Hat 4.1 just fine (using qemu -cpu 486 and the no387 option) once I changed /dev/hda1 to /dev/sda1.

I'm actually kind of impressed.

-hpa

Signature · 2 lines
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.
#4 lore raw
Quoted 3 lines · H. Peter Anvin

Well... it turns out to boot and run Red Hat 4.1 just fine (using qemu -cpu 486 and the no387 option) once I changed /dev/hda1 to /dev/sda1.

Ok. It sounds like the code actually works despite lack of testing, and it clearly hasn't been the same kind of maintenance pain and problem that the lack of cmpxchg and friends, so let's leave it alone. Thanks,

Linus

#5 lore raw
In reply to H. Peter Anvin
Quoted 7 lines · H. Peter Anvin <hpa <at> zytor.com> writes:
Quoted 1 line · Linus Torvalds

Or do people still use the 486SX?

There were a *bunch* of embedded 486 clones made, some still in production as far as I know, and I wouldn't be surprised if some of them lacked FPU. I guess we'll see.

This one is fairly recent: Bifferboard ⇒ http://bifferos.co.uk/

bye,
//mirabilos

#6 lore raw
In reply to H. Peter Anvin

On Mit, 2012-12-12 at 11:00 -0800, H. Peter Anvin wrote:
[...]

Quoted 3 lines

There were a *bunch* of embedded 486 clones made, some still in production as far as I know, and I wouldn't be surprised if some of them lacked FPU. I guess we'll see.

And there is an x86 emulator written in Javascript at
http://www.bellard.org/jslinux/.

http://www.bellard.org/jslinux/tech.html says that it (also) lacks an FPU.

Bernd

Signature · 2 lines
Bernd Petrovitsch                  Email : [email protected]
                     LUGA : http://www.luga.at
#7 lore raw
In reply to Linus Torvalds
Quoted 11 lines · Linus Torvalds
Quoted 3 lines · Ingo Molnar

This tree removes ancient-386-CPUs support and thus zaps quite a bit of complexity:

Btw, I think we should probably at least consider taking this one step further, and remove the dear old FPU emulation support too. Remove CONFIG_MATH_EMULATION and all of arch/x86/math-emu, along with a lot of small special cases.

Or do people still use the 486SX?

Yes, the RDC-R321x SoC which is supported by mainline actually needs Math emulation to properly work.

Quoted 9 lines

Now, the math emulation hasn't been all that fundamentally problematic (compared to lack of xadd etc), but it does result in some complexities in exception handling and ptrace (grep for HAVE_HWFP or "hard_math" or a number of other magic things). None of which have likely been tested at all in the last ten years, so who knows if it actually *works* or not.

Maybe somebody could try booting with "no387". Does it actually work?

Ok, I could try that.
--
Florian