e1000: make ICS write-only

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -0

index 92fb00a..928d804 100644

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
         val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }
 

Signature · 1 line

MST

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -0

index 92fb00a..928d804 100644

Quoted 22 lines · Jason Wang

Quoted 21 lines · Michael S. Tsirkin

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

Quoted 14 lines

hw/e1000.c set_interrupt_cause(E1000State *s, int index, uint32_t val) · line 235

Quoted 12 lines

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
         val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }
 

If my memory is correct, though ICS is marked as read only in the spec, we do can read it when I'm examining a real e1000 card.

Interesting, this was not Bill's motivation.
I haven't seen any reads with linux or windows guests - which guest did trigger them for you?
Also, what's the value one would expect?

Quoted 37 lines · Michael S. Tsirkin

Quoted 22 lines · Jason Wang

Quoted 21 lines · Michael S. Tsirkin

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

Quoted 14 lines

hw/e1000.c set_interrupt_cause(E1000State *s, int index, uint32_t val) · line 235

Quoted 12 lines

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
         val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }
 

If my memory is correct, though ICS is marked as read only in the spec, we do can read it when I'm examining a real e1000 card.

Quoted 5 lines

Interesting, this was not Bill's motivation.
I haven't seen any reads with linux or windows guests - which guest did trigger them for you?
Also, what's the value one would expect?

I also find this violation of spec in the past, so I just hack the linux driver to see the result. I'm not sure if there are some driver depends on this value. I forget the detail of what value it returns, may worth to try again to see.

Quoted 21 lines · Michael S. Tsirkin

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c set_interrupt_cause(E1000State *s, int index, uint32_t val) · line 235

Quoted 12 lines

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
         val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }
 

If my memory is correct, though ICS is marked as read only in the spec, we do can read it when I'm examining a real e1000 card.

Of all the gin joints in all the towns in all the world, Michael S. Tsirkin had to walk into mine at 02:51:00 on Wednesday 09 January 2013 and say:

Quoted 11 lines

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

You are wrong.

I know what the spec says. The spec lies (or at the very least, it doesn't agree with reality). With actual PRO/1000 hardware, the ICS register is readable. It provides a way to obtain the currently pending interrupt bits without the auto-clear behavior of the ICR register (which in some cases is actually detrimental).

The Intel 10GbE NICs (82598, 82599, x540) are the same way (they're very similar in design to the PRO/1000s, particularly the 82575, 82576, 82580 and later devices). The spes for the 10GbE devices _also_ say that ICS is read only. But if you look at the Intel drivers for those chips, you'll see they have actually implemented a workaround for a device errata (I think the for the 82598) that actually requires reading the ICS register. If you had implemented a PRO/10GbE virtual device based on the same chip and obeyed the spec the same way, I suspect Intel's driver would break.

I actually have in my possession real PRO/1000 silicon going all the way back to the 82543 and have tested every single one of them, and they all work like this. I've also asked the Intel LAN access division people about it and they said that in spite of it not being documented as readable, there's nothing particularly wrong with doing this.

The problem with using ICR is that the auto-clear behavior can sometimes result in some awkward interrupt handling code. You need to test ICR in interrupt context to see if there are events pending, and then schedule some other thread to handle them. But since reading ICR clears the bits, you need to save the events somewhere so that the other thread knows what events need servicing. Keeping the saved copy of pending events properly synchronized so that you don't lose any is actually big challenge. The VxWorks PRO/1000 driver used to have some very ugly code in it to deal with it, all of which became much simpler when using the ICS register instead.

I know what the spec says. But this is a case where the spec only says that because Intel decided not to disclose what the hardware actually does. They also don't tell you about all the hidden debug registers in the hardware either, but that doesn't mean they don't exist.

So pretty please, with sugar on top, leave this code alone.

-Bill

Quoted 20 lines

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t
 val) val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }

Signature · 6 lines

=============================================================================
-Bill Paul            (510) 749-2329 | Member of Technical Staff,
                 [email protected] | Master of Unix-Fu - Wind River Systems
=============================================================================
   "I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================

Of all the gin joints in all the towns in all the world, Michael S. Tsirkin had to walk into mine at 02:51:00 on Wednesday 09 January 2013 and say:

Quoted 11 lines

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

You are wrong.

I know what the spec says. The spec lies (or at the very least, it doesn't agree with reality). With actual PRO/1000 hardware, the ICS register is readable. It provides a way to obtain the currently pending interrupt bits without the auto-clear behavior of the ICR register (which in some cases is actually detrimental).

The Intel 10GbE NICs (82598, 82599, x540) are the same way (they're very similar in design to the PRO/1000s, particularly the 82575, 82576, 82580 and later devices). The spes for the 10GbE devices _also_ say that ICS is read only. But if you look at the Intel drivers for those chips, you'll see they have actually implemented a workaround for a device errata (I think the for the 82598) that actually requires reading the ICS register. If you had implemented a PRO/10GbE virtual device based on the same chip and obeyed the spec the same way, I suspect Intel's driver would break.

I actually have in my possession real PRO/1000 silicon going all the way back to the 82543 and have tested every single one of them, and they all work like this. I've also asked the Intel LAN access division people about it and they said that in spite of it not being documented as readable, there's nothing particularly wrong with doing this.

The problem with using ICR is that the auto-clear behavior can sometimes result in some awkward interrupt handling code. You need to test ICR in interrupt context to see if there are events pending, and then schedule some other thread to handle them. But since reading ICR clears the bits, you need to save the events somewhere so that the other thread knows what events need servicing. Keeping the saved copy of pending events properly synchronized so that you don't lose any is actually big challenge. The VxWorks PRO/1000 driver used to have some very ugly code in it to deal with it, all of which became much simpler when using the ICS register instead.

I know what the spec says. But this is a case where the spec only says that because Intel decided not to disclose what the hardware actually does. They also don't tell you about all the hidden debug registers in the hardware either, but that doesn't mean they don't exist.

So pretty please, with sugar on top, leave this code alone.

-Bill

Quoted 20 lines

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t
 val) val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }

Signature · 6 lines

=============================================================================
-Bill Paul            (510) 749-2329 | Member of Technical Staff,
                 [email protected] | Master of Unix-Fu - Wind River Systems
=============================================================================
   "I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t
 val) val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }

Of all the gin joints in all the towns in all the world, Michael S. Tsirkin had to walk into mine at 02:51:00 on Wednesday 09 January 2013 and say:

Quoted 11 lines

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968,
qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

You are wrong.

I know what the spec says. The spec lies (or at the very least, it doesn't agree with reality). With actual PRO/1000 hardware, the ICS register is readable. It provides a way to obtain the currently pending interrupt bits without the auto-clear behavior of the ICR register (which in some cases is actually detrimental).

The Intel 10GbE NICs (82598, 82599, x540) are the same way (they're very similar in design to the PRO/1000s, particularly the 82575, 82576, 82580 and later devices). The spes for the 10GbE devices _also_ say that ICS is read only. But if you look at the Intel drivers for those chips, you'll see they have actually implemented a workaround for a device errata (I think the for the 82598) that actually requires reading the ICS register. If you had implemented a PRO/10GbE virtual device based on the same chip and obeyed the spec the same way, I suspect Intel's driver would break.

I actually have in my possession real PRO/1000 silicon going all the way back to the 82543 and have tested every single one of them, and they all work like this. I've also asked the Intel LAN access division people about it and they said that in spite of it not being documented as readable, there's nothing particularly wrong with doing this.

The problem with using ICR is that the auto-clear behavior can sometimes result in some awkward interrupt handling code. You need to test ICR in interrupt context to see if there are events pending, and then schedule some other thread to handle them. But since reading ICR clears the bits, you need to save the events somewhere so that the other thread knows what events need servicing. Keeping the saved copy of pending events properly synchronized so that you don't lose any is actually big challenge. The VxWorks PRO/1000 driver used to have some very ugly code in it to deal with it, all of which became much simpler when using the ICS register instead.

I know what the spec says. But this is a case where the spec only says that because Intel decided not to disclose what the hardware actually does. They also don't tell you about all the hidden debug registers in the hardware either, but that doesn't mean they don't exist.

So pretty please, with sugar on top, leave this code alone.

-Bill

Quoted 20 lines

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---
 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index, uint32_t
 val) val |= E1000_ICR_INT_ASSERTED;
     }
     s->mac_reg[ICR] = val;
-    s->mac_reg[ICS] = val;
     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) != 0);
 }

Signature · 6 lines

=============================================================================
-Bill Paul            (510) 749-2329 | Member of Technical Staff,
                 [email protected] | Master of Unix-Fu - Wind River Systems
=============================================================================
   "I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================

I figured this would be the case but this is where a comment in the code or commit message would have helped a lot in avoiding future confusion.

Regards,

Anthony Liguori

Quoted 56 lines

Of all the gin joints in all the towns in all the world, Michael S. Tsirkin

had to walk into mine at 02:51:00 on Wednesday 09 January 2013 and say:

Quoted 11 lines

Since commit b1332393cdd7d023de8f1f8aa136ee7866a18968, qemu started updating ICS register when interrupt
is sent, with the intent to match spec better
(guests do not actually read this register).
However, the function set_interrupt_cause where ICS
is updated is often called internally by
device emulation so reading it does not produce the last value written by driver. Looking closer at the spec,
it documents ICS as write-only, so there's no need
to update it at all. I conclude that while harmless this line is useless code so removing it is a bit cleaner than keeping it in.

You are wrong.

I know what the spec says. The spec lies (or at the very least, it doesn't agree with reality). With actual PRO/1000 hardware, the ICS register is readable. It provides a way to obtain the currently pending interrupt bits without the auto-clear behavior of the ICR register (which in some cases is actually detrimental).

The Intel 10GbE NICs (82598, 82599, x540) are the same way (they're very similar in design to the PRO/1000s, particularly the 82575, 82576, 82580 and later devices). The spes for the 10GbE devices _also_ say that ICS is read only. But if you look at the Intel drivers for those chips, you'll see they have actually implemented a workaround for a device errata (I think the for the 82598) that actually requires reading the ICS register. If you had implemented a PRO/10GbE virtual device based on the same chip and obeyed the spec the same way, I suspect Intel's driver would break.

I actually have in my possession real PRO/1000 silicon going all the way back to the 82543 and have tested every single one of them, and they all work like this. I've also asked the Intel LAN access division people about it and they said that in spite of it not being documented as readable, there's nothing particularly wrong with doing this.

The problem with using ICR is that the auto-clear behavior can sometimes result in some awkward interrupt handling code. You need to test ICR in interrupt context to see if there are events pending, and then schedule some other thread to handle them. But since reading ICR clears the bits, you need to save the events somewhere so that the other thread knows what events need servicing. Keeping the saved copy of pending events properly synchronized so that you don't lose any is actually big challenge. The VxWorks PRO/1000 driver used to have some very ugly code in it to deal with it, all of which became much simpler when using the ICS register instead.

I know what the spec says. But this is a case where the spec only says that because Intel decided not to disclose what the hardware actually does. They also don't tell you about all the hidden debug registers in the hardware either, but that doesn't mean they don't exist.

Quoted 3 lines

So pretty please, with sugar on top, leave this code alone.

-Bill

OK now since there's no spec, I'd like to find out how does the register behave. Let's assume I read ICR. This clears ICR - does it also clear ICS?

Thanks,
MST

Quoted 26 lines

Quoted 26 lines

Tested with windows and linux guests.

Cc Bill Paul <[email protected]>

Reported-by Yan Vugenfirer <[email protected]>

Signed-off-by Michael S. Tsirkin <[email protected]>

---

 hw/e1000.c | 1 -
 1 file changed, 1 deletion(-)

hw/e1000.c +0 -1

index 92fb00a..928d804 100644
@@ -230,7 +230,6 @@ set_interrupt_cause(E1000State *s, int index,
 uint32_t val) val |= E1000_ICR_INT_ASSERTED;
 
     }
     s->mac_reg[ICR] = val;
 
-    s->mac_reg[ICS] = val;
 

     qemu_set_irq(s->dev.irq[0], (s->mac_reg[IMS] & s->mac_reg[ICR]) !=
     0);

}

Quoted 6 lines

I figured this would be the case but this is where a comment in the code or commit message would have helped a lot in avoiding future confusion.

Regards,

Anthony Liguori

I just sent a documentation patch, please take a look. Thanks!

Of all the gin joints in all the towns in all the world, Michael S. Tsirkin had to walk into mine at 14:07:53 on Wednesday 09 January 2013 and say:

Quoted 10 lines · Anthony Liguori

Quoted 6 lines

I figured this would be the case but this is where a comment in the code or commit message would have helped a lot in avoiding future confusion.

Regards,

Anthony Liguori

I just sent a documentation patch, please take a look. Thanks!

Well, strictly speaking, VxWorks doesn't rely on the ICS behavior anymore, but it prefers it. I ran into problems with VMware and Simics too, as they also don't emulate the ICS behavior, and getting that fixed was more of an uphill battle. So as a compromise I added a check to the driver to see if the ICS register has 'real hardware behavior' or 'emulated behavior' and made it use an alternate interrupt handling scheme in the emulated case. The alternate scheme is a little less efficient than the ICS scheme in some cases (mainly when the PRO/1000 device's interrupt is shared), but it still handles interrupts reliably.

That's a minor nit though. I'm fine with the comments as is. I just didn't want you do think VxWorks was completely brain damaged. :)

Note that I don't think VMware emulates the 'flexible RX mode' descriptor mechanism for the PRO/100 either, because the non-NDAed PRO/100 manual doesn't bother to mention it exists. I think this is something that was fixed in QEMU but I haven't had a chance to test it in a while. There's a similar problem with simulated the AMD PCnet/PCI devices (they only support the 'configuration block' setup method -- for the older non-PCI LANCE chips that was the only way to configure them but PCI devices starting with the am97c970 can be configured just by setting up registers).

Honestly I'm surprised I still have all my hair and that it's still the same color.

-Bill

Signature · 6 lines

=============================================================================
-Bill Paul            (510) 749-2329 | Member of Technical Staff,
                 [email protected] | Master of Unix-Fu - Wind River Systems
=============================================================================
   "I put a dollar in a change machine. Nothing changed." - George Carlin
=============================================================================