perf: Move PERF_MEM*SHIFT macros up the block

index fb104e5..52697a3 100644
@@ -632,14 +632,15 @@ union perf_mem_data_src {
 };
 
 /* type of opcode (load/store/prefetch,code) */
+#define PERF_MEM_OP_SHIFT	0
 #define PERF_MEM_OP_NA		0x01 /* not available */
 #define PERF_MEM_OP_LOAD	0x02 /* load instruction */
 #define PERF_MEM_OP_STORE	0x04 /* store instruction */
 #define PERF_MEM_OP_PFETCH	0x08 /* prefetch */
 #define PERF_MEM_OP_EXEC	0x10 /* code (execution) */
-#define PERF_MEM_OP_SHIFT	0
 
 /* memory hierarchy (memory level, hit or miss) */
+#define PERF_MEM_LVL_SHIFT	5
 #define PERF_MEM_LVL_NA		0x01  /* not available */
 #define PERF_MEM_LVL_HIT	0x02  /* hit level */
 #define PERF_MEM_LVL_MISS	0x04  /* miss level  */

@@ -654,22 +655,22 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_REM_CCE2	0x800 /* Remote Cache (2 hops) */
 #define PERF_MEM_LVL_IO		0x1000 /* I/O memory */
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
-#define PERF_MEM_LVL_SHIFT	5
 
 /* snoop mode */
+#define PERF_MEM_SNOOP_SHIFT	19
 #define PERF_MEM_SNOOP_NA	0x01 /* not available */
 #define PERF_MEM_SNOOP_NONE	0x02 /* no snoop */
 #define PERF_MEM_SNOOP_HIT	0x04 /* snoop hit */
 #define PERF_MEM_SNOOP_MISS	0x08 /* snoop miss */
 #define PERF_MEM_SNOOP_HITM	0x10 /* snoop hit modified */
-#define PERF_MEM_SNOOP_SHIFT	19
 
 /* locked instruction */
+#define PERF_MEM_LOCK_SHIFT	24
 #define PERF_MEM_LOCK_NA	0x01 /* not available */
 #define PERF_MEM_LOCK_LOCKED	0x02 /* locked transaction */
-#define PERF_MEM_LOCK_SHIFT	24
 
 /* TLB access */
+#define PERF_MEM_TLB_SHIFT	26
 #define PERF_MEM_TLB_NA		0x01 /* not available */
 #define PERF_MEM_TLB_HIT	0x02 /* hit level */
 #define PERF_MEM_TLB_MISS	0x04 /* miss level */

@@ -677,7 +678,6 @@ union perf_mem_data_src {
 #define PERF_MEM_TLB_L2		0x10 /* L2 */
 #define PERF_MEM_TLB_WK		0x20 /* Hardware Walker*/
 #define PERF_MEM_TLB_OS		0x40 /* OS fault handler */
-#define PERF_MEM_TLB_SHIFT	26
 
 #define PERF_MEM_S(a, s) \
 	(((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)

index f265049..30488f5 100644
@@ -37,6 +37,8 @@ struct power_pmu {
 	void            (*config_bhrb)(u64 pmu_bhrb_filter);
 	void		(*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
 	int		(*limited_pmc_event)(u64 event_id);
+	void		(*get_mem_data_src)(union perf_mem_data_src *dsrc,
+				struct pt_regs *regs);
 	u32		flags;
 	const struct attribute_group	**attr_groups;
 	int		n_generic;

index 29c6482..e0e0848 100644
@@ -1627,6 +1627,10 @@ static void record_and_restart(struct perf_event *event, unsigned long val,
 			data.br_stack = &cpuhw->bhrb_stack;
 		}
 
+		if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC &&
+				ppmu->get_mem_data_src)
+			ppmu->get_mem_data_src(&data.data_src, regs);
+
 		if (perf_event_overflow(event, &data, regs))
 			power_pmu_stop(event, 0);
 	}

76 lines not on this page · raw message

index 52697a3..815ee12 100644
@@ -626,8 +626,8 @@ union perf_mem_data_src {
 			mem_lvl:14,	/* memory hierarchy level */
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
-			mem_dtlb:7,	/* tlb access */
-			mem_rsvd:31;
+			mem_dtlb:17,	/* tlb access */
+			mem_rsvd:21;
 	};
 };
 

@@ -678,6 +678,16 @@ union perf_mem_data_src {
 #define PERF_MEM_TLB_L2		0x10 /* L2 */
 #define PERF_MEM_TLB_WK		0x20 /* Hardware Walker*/
 #define PERF_MEM_TLB_OS		0x40 /* OS fault handler */
+#define PERF_MEM_TLB_L3		0x80
+#define PERF_MEM_TLB_REM_L2_CCE1	0x100	/* Remote L2 cache (1 hop) */
+#define PERF_MEM_TLB_REM_L3_CCE1	0x200	/* Remote L3 cache (1 hop) */
+#define PERF_MEM_TLB_REM_CCE2	0x400	/* Remote cache (2 hops) */
+#define PERF_MEM_TLB_REM_CCE3	0x800	/* Remote cache (3 hops) */
+#define PERF_MEM_TLB_LOC_RAM	0x1000	/* Local DRAM */
+#define PERF_MEM_TLB_REM_RAM1	0x2000	/* Remote DRAM (1 hop) */
+#define PERF_MEM_TLB_REM_RAM2	0x4000	/* Remote DRAM (2 hops) */
+#define PERF_MEM_TLB_REM_RAM3	0x8000	/* Remote DRAM (3 hops) */
+#define PERF_MEM_TLB_CCE_DIRTY	0x10000	/* Remote cache entry hit, but dirty */
 
 #define PERF_MEM_S(a, s) \
 	(((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)

index c1cac96..8cb4cbc 100644
@@ -209,6 +209,10 @@ static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
 	return nalt;
 }
 
+#define POWER7_MMCRA_DCACHE_MISS        (0x1LL << 55)
+#define POWER7_MMCRA_DCACHE_SRC_SHIFT   51
+#define POWER7_MMCRA_DCACHE_SRC_MASK    (0xFLL << POWER7_MMCRA_DCACHE_SRC_SHIFT)
+
 #define	POWER7_MMCRA_MDTLB_MISS		(0x1LL << 50)
 #define	POWER7_MMCRA_MDTLB_SRC_SHIFT	46
 #define	POWER7_MMCRA_MDTLB_SRC_MASK	(0xFLL << POWER7_MMCRA_MDTLB_SRC_SHIFT)

@@ -231,6 +235,7 @@ static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
  */
 #define P(a, b)			PERF_MEM_S(a, b)
 #define TD(a, b)		(P(TLB, CCE_DIRTY) | P(a, b))
+#define XD(a, b)		(P(XLVL, CCE_DIRTY) | P(a, b))
 
 static u64 mdtlb_src_map[] = {
 	P(TLB,  L2),			/* 00: FROM_L2 */

@@ -258,6 +263,37 @@ static u64 mdtlb_src_map[] = {
 	P(TLB,  NA),			/* 15: Reserved */
 };
 
+/*
+ * Similar to mdtlb_src_map[] table above, use dcache_src_map[] to map
+ * the Power7 DCACHE_SRC field (bits 9..12) in MMCRA register to the
+ * Linux memory hierarchy levels.
+ */
+static u64 dcache_src_map[] = {
+	P(LVL,   L2),			/* 00: FROM_L2 */
+	P(LVL,   L3),			/* 01: FROM_L3 */
+
+	P(LVL,   NA),			/* 02: Reserved */
+	P(LVL,   NA),			/* 03: Reserved */
+
+	P(XLVL,  REM_L2_CCE1),		/* 04: FROM_L2.1_SHR */
+	XD(XLVL, REM_L2_CCE1),		/* 05: FROM_L2.1_MOD */
+
+	P(XLVL,  REM_L3_CCE1),		/* 06: FROM_L3.1_SHR */
+	XD(XLVL, REM_L3_CCE1),		/* 07: FROM_L3.1_MOD */
+
+	P(LVL,   REM_CCE2),		/* 08: FROM_RL2L3_SHR */
+	XD(LVL,  REM_CCE2),		/* 09: FROM_RL2L3_MOD */
+
+	P(XLVL,  REM_CCE3),		/* 10: FROM_DL2L3_SHR */
+	XD(XLVL, REM_CCE3),		/* 11: FROM_DL2L3_MOD */
+
+	P(LVL,   LOC_RAM),		/* 12: FROM_LMEM */
+	P(LVL,   REM_RAM2),		/* 13: FROM_RMEM */
+	P(XLVL,  REM_RAM3),		/* 14: FROM_DMEM */
+
+	P(LVL,   NA),			/* 15: Reserved */
+};
+
 static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
 				struct pt_regs *regs)
 {

@@ -270,6 +306,14 @@ static void power7_get_mem_data_src(union perf_mem_data_src *dsrc,
 
 		dsrc->val |= mdtlb_src_map[idx];
 	}
+
+	if (mmcra & POWER7_MMCRA_DCACHE_MISS) {
+		idx = mmcra & POWER7_MMCRA_DCACHE_SRC_MASK;
+		idx >>= POWER7_MMCRA_DCACHE_SRC_SHIFT;
+
+		dsrc->val |= dcache_src_map[idx];
+	}
+
 }
 
 /*

index 815ee12..149b33d 100644
@@ -627,7 +627,8 @@ union perf_mem_data_src {
 			mem_snoop:5,	/* snoop mode */
 			mem_lock:2,	/* lock instr */
 			mem_dtlb:17,	/* tlb access */
-			mem_rsvd:21;
+			mem_xlvl:6,	/* memory hierarchy levels contd */
+			mem_rsvd:15;
 	};
 };
 

@@ -655,6 +656,7 @@ union perf_mem_data_src {
 #define PERF_MEM_LVL_REM_CCE2	0x800 /* Remote Cache (2 hops) */
 #define PERF_MEM_LVL_IO		0x1000 /* I/O memory */
 #define PERF_MEM_LVL_UNC	0x2000 /* Uncached memory */
+/* memory hierarchy levels continued/extended below */
 
 /* snoop mode */
 #define PERF_MEM_SNOOP_SHIFT	19

@@ -689,6 +691,15 @@ union perf_mem_data_src {
 #define PERF_MEM_TLB_REM_RAM3	0x8000	/* Remote DRAM (3 hops) */
 #define PERF_MEM_TLB_CCE_DIRTY	0x10000	/* Remote cache entry hit, but dirty */
 
+/* Extended levels i.e. continuation of PERF_MEM_LVL* values above. */
+#define PERF_MEM_XLVL_SHIFT		43
+#define PERF_MEM_XLVL_NA		0x01	/* not available */
+#define PERF_MEM_XLVL_CCE_DIRTY		0x02    /* cache entry hit, was dirty */
+#define PERF_MEM_XLVL_REM_L2_CCE1	0x04    /* Remote L2-cache (1 hop) */
+#define PERF_MEM_XLVL_REM_L3_CCE1	0x08    /* Remote L3-cache (1 hop) */
+#define PERF_MEM_XLVL_REM_CCE3		0x10    /* Remote cache (3 hops) */
+#define PERF_MEM_XLVL_REM_RAM3		0x20    /* Remote DRAM (3 hops) */
+
 #define PERF_MEM_S(a, s) \
 	(((u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT)