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drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()

PATCH In review Dan Carpenter 2 participants 2 messages Jul 12, 2013

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Dan Carpenter

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#0 lore raw

PATCH 1/1 drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()

We care about the upper 32 bits here so we have to use 1ULL instead of 1 to avoid a shift wrapping bug.

Signed-off-by Dan Carpenter <[email protected]>
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +1 -1
index 64dca26..fe67415 100644
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
 			} while (!tpcnr[gpc]);
 			tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 
-			tpc_set |= 1 << ((gpc * 8) + tpc);
+			tpc_set |= 1ULL << ((gpc * 8) + tpc);
 		}
 
 		nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
Reviewed-by on v1 1/1
#1 lore raw

Op 12-07-13 08:33, Dan Carpenter schreef:

Quoted 10 lines

We care about the upper 32 bits here so we have to use 1ULL instead of 1 to avoid a shift wrapping bug.

Signed-off-by Dan Carpenter <[email protected]>
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +0 -0
index 64dca26..fe67415 100644

drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv) · line 1045

Quoted 8 lines
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c +1 -1
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
 			} while (!tpcnr[gpc]);
 			tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
 
-			tpc_set |= 1 << ((gpc * 8) + tpc);
+			tpc_set |= 1ULL << ((gpc * 8) + tpc);
 		}
 
 		nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
Reviewed-by Maarten Lankhorst <[email protected]>

Any other code in nouveau that looks bugged?