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powerpc: Correct FSCR bit definitions

PATCH In review Paul Mackerras 2 participants 2 messages Sep 5, 2013 PowerPC

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PATCH 1/1 powerpc: Correct FSCR bit definitions

Commit 74e400cee6 ("powerpc: Rework setting up H/FSCR bit definitions") ended up with incorrect bit numbers for FSCR_PM_LG and FSCR_BHRB_LG. This fixes them.

---
 arch/powerpc/include/asm/reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/powerpc/include/asm/reg.h +2 -2
index dc10bf5..10d1ef0 100644
@@ -258,8 +258,8 @@
 #define FSCR_TAR_LG	8	/* Enable Target Address Register */
 #define FSCR_EBB_LG	7	/* Enable Event Based Branching */
 #define FSCR_TM_LG	5	/* Enable Transactional Memory */
-#define FSCR_PM_LG	4	/* Enable prob/priv access to PMU SPRs */
-#define FSCR_BHRB_LG	3	/* Enable Branch History Rolling Buffer*/
+#define FSCR_BHRB_LG	4	/* Enable Branch History Rolling Buffer*/
+#define FSCR_PM_LG	3	/* Enable prob/priv access to PMU SPRs */
 #define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */
 #define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
 #define FSCR_FP_LG	0	/* Enable Floating Point */
Signature · 1 line
1.8.4.rc3
Acked-by on v1 1/1
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Quoted 5 lines · Paul Mackerras

Commit 74e400cee6 ("powerpc: Rework setting up H/FSCR bit definitions") ended up with incorrect bit numbers for FSCR_PM_LG and FSCR_BHRB_LG. This fixes them.

Sorry about that screw up.

Mikey

Quoted 22 lines
---
 arch/powerpc/include/asm/reg.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/powerpc/include/asm/reg.h +2 -2
index dc10bf5..10d1ef0 100644
@@ -258,8 +258,8 @@
 #define FSCR_TAR_LG	8	/* Enable Target Address Register */
 #define FSCR_EBB_LG	7	/* Enable Event Based Branching */
 #define FSCR_TM_LG	5	/* Enable Transactional Memory */
-#define FSCR_PM_LG	4	/* Enable prob/priv access to PMU SPRs */
-#define FSCR_BHRB_LG	3	/* Enable Branch History Rolling Buffer*/
+#define FSCR_BHRB_LG	4	/* Enable Branch History Rolling Buffer*/
+#define FSCR_PM_LG	3	/* Enable prob/priv access to PMU SPRs */
 #define FSCR_DSCR_LG	2	/* Enable Data Stream Control Register */
 #define FSCR_VECVSX_LG	1	/* Enable VMX/VSX  */
 #define FSCR_FP_LG	0	/* Enable Floating Point */
Signature · 1 line
1.8.4.rc3