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x86/pmc_atom: silence shift wrapping warnings in pmc_sleep_tmr_show()

PATCH In review Dan Carpenter 3 participants 3 messages Aug 1, 2014 – Aug 2, 2014

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#0 lore raw

PATCH 1/1 x86/pmc_atom: silence shift wrapping warnings in pmc_sleep_tmr_show()

I don't know if we really need 64 bits here but these variables are declared as u64 and it can't hurt to cast this so we prevent any shift wrapping.

Signed-off-by Dan Carpenter <[email protected]>
arch/x86/kernel/pmc_atom.c +5 -5
index 0d92ef6..0c424a6 100644
@@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 	struct pmc_dev *pmc = s->private;
 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 
-	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
-	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
-	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
-	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
-	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
+	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
+	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
+	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
+	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
+	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 
 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
Acked-by on v1 1/1
#1 lore raw
Quoted 7 lines · Srinidhi
Quoted 3 lines · Dan Carpenter

I don't know if we really need 64 bits here but these variables are declared as u64 and it can't hurt to cast this so we prevent any shift wrapping.

Hmm..not sure the usage of u64 for these registers. AFAIK these registers are 32-bit wide..

I didn't declare the registers, I declared the variables in microsecond.

Quoted 2 lines

Aubrey, any reason declaring them as u64?

These registers are the time spent in units of 32us. So yes, we need 64bits here for the conversion.

Quoted 5 lines

Srinidhi

Quoted 2 lines
Signed-off-by Dan Carpenter <[email protected]>

The patch looks good to me.

Acked-by Aubrey Li <[email protected]>
Quoted 23 lines
Quoted 22 lines
arch/x86/kernel/pmc_atom.c +5 -5
index 0d92ef6..0c424a6 100644
@@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 	struct pmc_dev *pmc = s->private;
 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 
-	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
-	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
-	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
-	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
-	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
+	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
+	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
+	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
+	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
+	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 
 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
merge bot
#2 lore raw

[tip:x86/platform] x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show()

In reply to Dan Carpenter
x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show()
Commit-ID:  4c51cb005b29e6329d7e598bf835689b230817c9
Gitweb:     http://git.kernel.org/tip/4c51cb005b29e6329d7e598bf835689b230817c9
Author:     Dan Carpenter <[email protected]>
AuthorDate: Fri, 1 Aug 2014 11:27:15 +0300
Committer:  H. Peter Anvin <[email protected]>
CommitDate: Sat, 2 Aug 2014 16:52:17 -0700

x86/pmc_atom: Silence shift wrapping warnings in pmc_sleep_tmr_show()

I don't know if we really need 64 bits here but these variables are declared as u64 and it can't hurt to cast this so we prevent any shift wrapping.

Signed-off-by Dan Carpenter <[email protected]>
Acked-by Aubrey Li <[email protected]>
Link http://lkml.kernel.org/r/20140801082715.GE28869@mwanda open here
Signed-off-by H. Peter Anvin <[email protected]>
---
 arch/x86/kernel/pmc_atom.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)
arch/x86/kernel/pmc_atom.c +5 -5
index 0d92ef6..0c424a6 100644
@@ -174,11 +174,11 @@ static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
 	struct pmc_dev *pmc = s->private;
 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
 
-	s0ir_tmr = pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
-	s0i1_tmr = pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
-	s0i2_tmr = pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
-	s0i3_tmr = pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
-	s0_tmr = pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
+	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
+	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
+	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
+	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
+	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
 
 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);