target-ppc: Add FWNMI support in qemu for powerKVM guests

PATCH Superseded Aravinda Prasad 3 participants 13 messages Sep 4, 2014 – Sep 11, 2014

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Aravinda Prasad

author

2014-09-04 11:13 UTC #0 lore raw

v2 cover target-ppc: Add FWNMI support in qemu for powerKVM guests

This series of patches add support for fwnmi in powerKVM guests.

Currently upon machine check exception, if the address in error belongs to guest then KVM invokes guest's NMI interrupt vector 0x200.

This patch series adds functionality where the guest's 0x200 interrupt vector is patched such that QEMU gets control. QEMU then builds error log and reports the error to OS registered machine check handlers through RTAS space.

Apart from this, the patch series also takes care of synchronization when multiple processors encounter machine check at or about the same time.

The patch set was tested by simulating a machine check error in the guest.

Changes in v2:
- Re-based to github.com/agraf/qemu.git branch: ppc-next
- Merged patches 4 and 5.
- Incorporated other review comments

---

Aravinda Prasad (4):
target-ppc: Extend rtas-blob
target-ppc: Register and handle HCALL to receive updated RTAS region
target-ppc: Build error log
target-ppc: Handle ibm,nmi-register RTAS call

 hw/ppc/spapr.c         |    4 +
 hw/ppc/spapr_hcall.c   |  178 ++++++++++++++++++++++++++++++++++++++++++++++++
 hw/ppc/spapr_rtas.c    |  116 +++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |   13 +++-
 4 files changed, 309 insertions(+), 2 deletions(-)

Signature · 1 line

Aravinda Prasad

Aravinda Prasad

author

2014-09-04 11:13 UTC #1 lore raw

PATCH v2 1/4 target-ppc: Extend rtas-blob

Extend rtas-blob to accommodate error log. Error log structure is saved in rtas space upon a machine check exception.

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr.c |    4 ++++
 1 file changed, 4 insertions(+)

hw/ppc/spapr.c +4 -0

index 4b20e36..4a7c0ae 100644
@@ -1409,6 +1409,10 @@ static void ppc_spapr_init(MachineState *machine)
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
     spapr->rtas_size = get_image_size(filename);
+
+    /* Resize blob to accommodate error log at a page aligned address */
+    spapr->rtas_size = TARGET_PAGE_ALIGN(spapr->rtas_size) + TARGET_PAGE_SIZE;
+
     spapr->rtas_blob = g_malloc(spapr->rtas_size);
     if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
         hw_error("qemu: could not load LPAR rtas '%s'\n", filename);

Aravinda Prasad

author

2014-09-04 11:14 UTC #4 lore raw

PATCH v2 2/4 target-ppc: Register and handle HCALL to receive updated RTAS region

In reply to Aravinda Prasad

Receive updates from SLOF about the updated rtas-base. A separate patch for SLOF [1] adds functionality to invoke a a private HCALL whenever OS issues instantiate-rtas with a new rtas-base.

This is required as qemu needs to know the updated rtas-base as it allocates error reporting structure in RTAS space upon a machine check exception.

[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-August/120386.html

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr_hcall.c   |    8 ++++++++
 include/hw/ppc/spapr.h |    3 ++-
 2 files changed, 10 insertions(+), 1 deletion(-)

hw/ppc/spapr_hcall.c +8 -0

index 8651447..01650ba 100644
@@ -579,6 +579,13 @@ static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                            nret, rtas_r3 + 12 + 4*nargs);
 }
 
+static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+                                  target_ulong opcode, target_ulong *args)
+{
+    spapr->rtas_addr = args[0];
+    return 0;
+}
+
 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                                    target_ulong opcode, target_ulong *args)
 {

@@ -1003,6 +1010,7 @@ static void hypercall_register_types(void)
 
     /* qemu/KVM-PPC specific hcalls */
     spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
+    spapr_register_hypercall(KVMPPC_H_RTAS_UPDATE, h_rtas_update);
 
     spapr_register_hypercall(H_SET_MODE, h_set_mode);

include/hw/ppc/spapr.h +2 -1

index 749daf4..908db26 100644
@@ -308,7 +308,8 @@ typedef struct sPAPREnvironment {
 #define KVMPPC_H_LOGICAL_MEMOP  (KVMPPC_HCALL_BASE + 0x1)
 /* Client Architecture support */
 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
-#define KVMPPC_HCALL_MAX        KVMPPC_H_CAS
+#define KVMPPC_H_RTAS_UPDATE    (KVMPPC_HCALL_BASE + 0x3)
+#define KVMPPC_HCALL_MAX        KVMPPC_H_RTAS_UPDATE
 
 extern sPAPREnvironment *spapr;

Aravinda Prasad

author

2014-09-04 11:14 UTC #5 lore raw

PATCH v2 3/4 target-ppc: Build error log

In reply to Aravinda Prasad

Whenever there is a physical memory error due to bit flips, which cannot be corrected by hardware, the error is passed on to the kernel. If the memory address in error belongs to guest address space then guest kernel is responsible to take action. Hence the error is passed on to guest via KVM by invoking 0x200 NMI vector.

However, guest OS, as per PAPR, expects an error log upon such error. This patch registers a new hcall which is issued from 0x200 interrupt vector and builds the error log, copies the error log to rtas space and passes the address of the error log to guest

Enhancement to KVM to perform above functionality is already in upstream kernel.

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)

hw/ppc/spapr_hcall.c +154 -0

index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved
+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};
+
+/*
+ * Data format in RTAS-Blob
+ *
+ * This structure contains error information related to Machine
+ * Check exception. This is filled up and copied to rtas-blob
+ * upon machine check exception.
+ */
+struct rtas_mc_log {
+    target_ulong srr0;
+    target_ulong srr1;
+    /*
+     * Beginning of error log address. This is properly
+     * populated and passed on to OS registered machine
+     * check notification routine upon machine check
+     * exception
+     */
+    target_ulong r3;
+    struct rtas_error_log err_log;
+};
+
 static void do_spr_sync(void *arg)
 {
     struct SPRSyncState *s = arg;

@@ -586,6 +668,77 @@ static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     return 0;
 }
 
+static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+                                 target_ulong opcode, target_ulong *args)
+{
+    struct rtas_mc_log mc_log;
+    CPUPPCState *env = &cpu->env;
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+    /*
+     * We save the original r3 register in SPRG2 in 0x200 vector,
+     * which is patched during call to ibm.nmi-register. Original
+     * r3 is required to be included in error log
+     */
+    mc_log.r3 = env->spr[SPR_SPRG2];
+
+    /*
+     * SRR0 and SRR1, containing nip and msr at the time of exception,
+     * are clobbered when we return from this hcall. Hence they
+     * need to be properly saved and restored. We save srr0
+     * and srr1 in rtas blob and restore it in 0x200 vector
+     * before branching to OS registered machine check handler
+     */
+    mc_log.srr0 = env->spr[SPR_SRR0];
+    mc_log.srr1 = env->spr[SPR_SRR1];
+
+    /* Set error log fields */
+    mc_log.err_log.byte0 = 0x00;
+    mc_log.err_log.byte1 =
+        (RTAS_SEVERITY_ERROR_SYNC << RTAS_ELOG_SEVERITY_SHIFT);
+    mc_log.err_log.byte1 |=
+        (RTAS_DISP_NOT_RECOVERED << RTAS_ELOG_DISPOSITION_SHIFT);
+    mc_log.err_log.byte2 =
+        (RTAS_INITIATOR_MEMORY << RTAS_ELOG_INITIATOR_SHIFT);
+    mc_log.err_log.byte2 |= RTAS_TARGET_MEMORY;
+
+    if (env->spr[SPR_DSISR] & P7_DSISR_MC_UE) {
+        mc_log.err_log.byte3 = RTAS_TYPE_ECC_UNCORR;
+    } else {
+        mc_log.err_log.byte3 = 0x0;
+    }
+
+    /* Handle all Host/Guest LE/BE combinations */
+    if ((*pcc->interrupts_big_endian)(cpu)) {
+        mc_log.srr0 = cpu_to_be64(mc_log.srr0);
+        mc_log.srr1 = cpu_to_be64(mc_log.srr1);
+        mc_log.r3 = cpu_to_be64(mc_log.r3);
+    } else {
+        mc_log.srr0 = cpu_to_le64(mc_log.srr0);
+        mc_log.srr1 = cpu_to_le64(mc_log.srr1);
+        mc_log.r3 = cpu_to_le64(mc_log.r3);
+    }
+
+    cpu_physical_memory_write(spapr->rtas_addr + RTAS_ERROR_OFFSET,
+                              &mc_log, sizeof(mc_log));
+
+    /*
+     * spapr->rtas_addr + RTAS_ERROR_OFFSET now contains srr0, srr1,
+     * original r3, followed by the error log structure. The address
+     * of the error log should be passed on to guest's machine check
+     * notification routine. As this hcall is directly called from
+     * 0x200 interrupt vector and returns to assembly routine, we
+     * return (spapr->rtas_addr + RTAS_ERROR_OFFSET) instead of
+     * H_SUCCESS. Upon return, We restore srr0 and srr1, increment
+     * r3 to point to the error log and branch to machine check
+     * notification routine in 0x200. r3 containing the error address
+     * is now argument to OS registered machine check notification
+     * routine. This way we also avoids clobbering additional
+     * registers in 0x200 vector.
+     */
+    return spapr->rtas_addr + RTAS_ERROR_OFFSET;
+}
+
 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr,
                                    target_ulong opcode, target_ulong *args)
 {

@@ -1011,6 +1164,7 @@ static void hypercall_register_types(void)
     /* qemu/KVM-PPC specific hcalls */
     spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
     spapr_register_hypercall(KVMPPC_H_RTAS_UPDATE, h_rtas_update);
+    spapr_register_hypercall(KVMPPC_H_REPORT_MC_ERR, h_report_mc_err);
 
     spapr_register_hypercall(H_SET_MODE, h_set_mode);

include/hw/ppc/spapr.h +3 -1

index 908db26..74cf881 100644
@@ -309,7 +309,9 @@ typedef struct sPAPREnvironment {
 /* Client Architecture support */
 #define KVMPPC_H_CAS            (KVMPPC_HCALL_BASE + 0x2)
 #define KVMPPC_H_RTAS_UPDATE    (KVMPPC_HCALL_BASE + 0x3)
-#define KVMPPC_HCALL_MAX        KVMPPC_H_RTAS_UPDATE
+/* Report Machine Check error */
+#define KVMPPC_H_REPORT_MC_ERR  (KVMPPC_HCALL_BASE + 0x4)
+#define KVMPPC_HCALL_MAX        KVMPPC_H_REPORT_MC_ERR
 
 extern sPAPREnvironment *spapr;

Aravinda Prasad

author

2014-09-04 11:14 UTC #12 lore raw

PATCH v2 4/4 target-ppc: Handle ibm, nmi-register RTAS call

In reply to Aravinda Prasad

This patch adds FWNMI support in qemu for powerKVM guests by handling the ibm,nmi-register rtas call. Whenever OS issues ibm,nmi-register RTAS call, the machine check notification address is saved and the machine check interrupt vector 0x200 is patched to issue a private hcall.

This patch also handles the cases when multi-processors experience machine check at or about the same time. As per PAPR, subsequent processors serialize waiting for the first processor to issue the ibm,nmi-interlock call. The second processor retries if the first processor which received a machine check is still reading the error log and is yet to issue ibm,nmi-interlock call.

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr_hcall.c   |   16 +++++++
 hw/ppc/spapr_rtas.c    |  116 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    8 +++
 3 files changed, 139 insertions(+), 1 deletion(-)

hw/ppc/spapr_hcall.c +16 -0

index c3aa448..380e75c 100644
@@ -96,6 +96,9 @@ struct rtas_mc_log {
     struct rtas_error_log err_log;
 };
 
+/* Whether machine check handling is in progress by any CPU */
+bool mc_in_progress;
+
 static void do_spr_sync(void *arg)
 {
     struct SPRSyncState *s = arg;

@@ -676,6 +679,19 @@ static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 
     /*
+     * Only one VCPU can process machine check NMI at a time. Hence
+     * set the lock mc_in_progress. Once the VCPU finishes processing
+     * NMI, it executes ibm,nmi-interlock and mc_in_progress is unset
+     * in ibm,nmi-interlock handler. Meanwhile if other VCPUs encounter
+     * NMI we return 0 asking the VCPU to retry h_report_mc_err
+     */
+    if (mc_in_progress == 1) {
+        return 0;
+    }
+
+    mc_in_progress = 1;
+
+    /*
      * We save the original r3 register in SPRG2 in 0x200 vector,
      * which is patched during call to ibm.nmi-register. Original
      * r3 is required to be included in error log

hw/ppc/spapr_rtas.c +116 -0

134 lines not on this page · raw message

include/hw/ppc/spapr.h +7 -1

index 74cf881..bbb2747 100644
@@ -384,8 +384,10 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi);
 #define RTAS_GET_SENSOR_STATE                   (RTAS_TOKEN_BASE + 0x1D)
 #define RTAS_IBM_CONFIGURE_CONNECTOR            (RTAS_TOKEN_BASE + 0x1E)
 #define RTAS_IBM_OS_TERM                        (RTAS_TOKEN_BASE + 0x1F)
+#define RTAS_IBM_NMI_REGISTER                   (RTAS_TOKEN_BASE + 0x20)
+#define RTAS_IBM_NMI_INTERLOCK                  (RTAS_TOKEN_BASE + 0x21)
 
-#define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x20)
+#define RTAS_TOKEN_MAX                          (RTAS_TOKEN_BASE + 0x22)
 
 /* RTAS ibm,get-system-parameter token values */
 #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS      20

@@ -483,4 +485,8 @@ int spapr_dma_dt(void *fdt, int node_off, const char *propname,
 int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname,
                       sPAPRTCETable *tcet);
 
+/* Machine Check Interrupt related macros */
+#define MC_INTERRUPT_VECTOR           0x200
+#define MC_INTERRUPT_VECTOR_SIZE      0x100
+
 #endif /* !defined (__HW_SPAPR_H__) */

Alexey Kardashevskiy

2014-09-05 02:15 UTC #6 lore raw

Re: [Qemu-devel] [PATCH v2 3/4] target-ppc: Build error log

In reply to Aravinda Prasad

Quoted 81 lines · Aravinda Prasad

Enhancement to KVM to perform above functionality is already in upstream kernel.

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)

hw/ppc/spapr_hcall.c +51 -0

index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 77

Quoted 10 lines

hw/ppc/spapr_hcall.c +10 -0

+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};

Any particular reason not to copy rtas_error_log as is?

Signature · 5 lines

Alexey Kardashevskiy
IBM OzLabs, LTC Team

e-mail: [email protected]
notes: Alexey Kardashevskiy/Australia/IBM

Alexander Graf

2014-09-05 07:42 UTC #2 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 1/4] target-ppc: Extend rtas-blob

In reply to Aravinda Prasad

Quoted 14 lines · Aravinda Prasad

Extend rtas-blob to accommodate error log. Error log structure is saved in rtas space upon a machine check exception.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr.c |    4 ++++
 1 file changed, 4 insertions(+)
hw/ppc/spapr.c +0 -0
index 4b20e36..4a7c0ae 100644

hw/ppc/spapr.c static void ppc_spapr_init(MachineState *machine) · line 1414

Quoted 6 lines

hw/ppc/spapr.c +3 -0

@@ -1409,6 +1409,10 @@ static void ppc_spapr_init(MachineState *machine)
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
     spapr->rtas_size = get_image_size(filename);
+
+    /* Resize blob to accommodate error log at a page aligned address */
+    spapr->rtas_size = TARGET_PAGE_ALIGN(spapr->rtas_size) + TARGET_PAGE_SIZE;

I think it's clearer if you do

#define RTAS_ERROR_LOG_SIZE 4096

and add this to the aligned size instead.

Alex

Aravinda Prasad

author

2014-09-05 07:57 UTC #3 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 1/4] target-ppc: Extend rtas-blob

Quoted 26 lines · Alexander Graf

Quoted 14 lines · Aravinda Prasad
Extend rtas-blob to accommodate error log. Error log structure is saved in rtas space upon a machine check exception.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr.c |    4 ++++
 1 file changed, 4 insertions(+)
hw/ppc/spapr.c +0 -0
index 4b20e36..4a7c0ae 100644
hw/ppc/spapr.c static void ppc_spapr_init(MachineState *machine) · line 1414
Quoted 6 lines
hw/ppc/spapr.c +3 -0
@@ -1409,6 +1409,10 @@ static void ppc_spapr_init(MachineState *machine)
 
     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
     spapr->rtas_size = get_image_size(filename);
+
+    /* Resize blob to accommodate error log at a page aligned address */
+    spapr->rtas_size = TARGET_PAGE_ALIGN(spapr->rtas_size) + TARGET_PAGE_SIZE;
I think it's clearer if you do

Quoted 3 lines

#define RTAS_ERROR_LOG_SIZE 4096
and add this to the aligned size instead.

sure

Quoted 4 lines

Alex

Signature · 2 lines

Regards,
Aravinda

Alexander Graf

2014-09-05 08:05 UTC #8 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/4] target-ppc: Build error log

In reply to Aravinda Prasad

Quoted 27 lines · Aravinda Prasad

Whenever there is a physical memory error due to bit flips, which cannot be corrected by hardware, the error is passed on to the kernel. If the memory address in error belongs to guest address space then guest kernel is responsible to take action. Hence the error is passed on to guest via KVM by invoking 0x200 NMI vector.
However, guest OS, as per PAPR, expects an error log upon such error. This patch registers a new hcall which is issued from 0x200 interrupt vector and builds the error log, copies the error log to rtas space and passes the address of the error log to guest
Enhancement to KVM to perform above functionality is already in upstream kernel.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)
hw/ppc/spapr_hcall.c +0 -0
index 01650ba..c3aa448 100644

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 18

Quoted 5 lines

hw/ppc/spapr_hcall.c +2 -0

@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)

You can't assume this. Please compute the value at the same place you compute the rtas-size.

Quoted 23 lines

hw/ppc/spapr_hcall.c +23 -0

+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 51

Quoted 10 lines

hw/ppc/spapr_hcall.c +10 -0

+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h

Please don't include Linux code. This file is GPLv2+ licensed and I don't want to taint it as GPLv2 only just for the sake of mce.

Quoted 57 lines

hw/ppc/spapr_hcall.c +50 -0

+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved
+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};
+
+/*
+ * Data format in RTAS-Blob
+ *
+ * This structure contains error information related to Machine
+ * Check exception. This is filled up and copied to rtas-blob
+ * upon machine check exception.
+ */
+struct rtas_mc_log {
+    target_ulong srr0;
+    target_ulong srr1;
+    /*
+     * Beginning of error log address. This is properly
+     * populated and passed on to OS registered machine
+     * check notification routine upon machine check
+     * exception
+     */
+    target_ulong r3;
+    struct rtas_error_log err_log;
+};
+
 static void do_spr_sync(void *arg)
 {
     struct SPRSyncState *s = arg;

@@ -586,6 +668,77 @@ static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     return 0;
 }
 
+static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+                                 target_ulong opcode, target_ulong *args)
+{

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 683

Quoted 10 lines

hw/ppc/spapr_hcall.c +10 -0

+    struct rtas_mc_log mc_log;
+    CPUPPCState *env = &cpu->env;
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+    /*
+     * We save the original r3 register in SPRG2 in 0x200 vector,
+     * which is patched during call to ibm.nmi-register. Original
+     * r3 is required to be included in error log
+     */
+    mc_log.r3 = env->spr[SPR_SPRG2];

Don't you have to call cpu_synchronize_registers() before you access SPRG2? Otherwise the value may be stale.

Quoted 19 lines

hw/ppc/spapr_hcall.c +19 -0

+
+    /*
+     * SRR0 and SRR1, containing nip and msr at the time of exception,
+     * are clobbered when we return from this hcall. Hence they
+     * need to be properly saved and restored. We save srr0
+     * and srr1 in rtas blob and restore it in 0x200 vector
+     * before branching to OS registered machine check handler
+     */
+    mc_log.srr0 = env->spr[SPR_SRR0];
+    mc_log.srr1 = env->spr[SPR_SRR1];
+
+    /* Set error log fields */
+    mc_log.err_log.byte0 = 0x00;
+    mc_log.err_log.byte1 =
+        (RTAS_SEVERITY_ERROR_SYNC << RTAS_ELOG_SEVERITY_SHIFT);
+    mc_log.err_log.byte1 |=
+        (RTAS_DISP_NOT_RECOVERED << RTAS_ELOG_DISPOSITION_SHIFT);
+    mc_log.err_log.byte2 =
+        (RTAS_INITIATOR_MEMORY << RTAS_ELOG_INITIATOR_SHIFT);

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 712

Quoted 10 lines

hw/ppc/spapr_hcall.c +10 -0

+    mc_log.err_log.byte2 |= RTAS_TARGET_MEMORY;
+
+    if (env->spr[SPR_DSISR] & P7_DSISR_MC_UE) {
+        mc_log.err_log.byte3 = RTAS_TYPE_ECC_UNCORR;
+    } else {
+        mc_log.err_log.byte3 = 0x0;
+    }
+
+    /* Handle all Host/Guest LE/BE combinations */
+    if ((*pcc->interrupts_big_endian)(cpu)) {

This should check MSR.LE, not ILE.

Alex

Aravinda Prasad

author

2014-09-05 08:08 UTC #7 lore raw

Re: [Qemu-devel] [PATCH v2 3/4] target-ppc: Build error log

In reply to Alexey Kardashevskiy

Quoted 87 lines · Alexey Kardashevskiy

Quoted 86 lines · Aravinda Prasad

Enhancement to KVM to perform above functionality is already in upstream kernel.

Signed-off-by Aravinda Prasad <[email protected]>

---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)

hw/ppc/spapr_hcall.c +56 -0

index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved
+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX

Quoted 8 lines

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 77
Quoted 5 lines
hw/ppc/spapr_hcall.c +5 -0
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};
Any particular reason not to copy rtas_error_log as is?

No specific reason. I overlooked it when I moved my code form early prototype version. Will include rest all members.

Regards,
Aravinda

Quoted 4 lines

Signature · 2 lines

Regards,
Aravinda

Aravinda Prasad

author

2014-09-05 08:28 UTC #9 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/4] target-ppc: Build error log

In reply to Alexander Graf

Quoted 33 lines · Alexander Graf

Quoted 30 lines · Aravinda Prasad
Whenever there is a physical memory error due to bit flips, which cannot be corrected by hardware, the error is passed on to the kernel. If the memory address in error belongs to guest address space then guest kernel is responsible to take action. Hence the error is passed on to guest via KVM by invoking 0x200 NMI vector.
However, guest OS, as per PAPR, expects an error log upon such error. This patch registers a new hcall which is issued from 0x200 interrupt vector and builds the error log, copies the error log to rtas space and passes the address of the error log to guest
Enhancement to KVM to perform above functionality is already in upstream kernel.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)
hw/ppc/spapr_hcall.c +0 -0
index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 

Quoted 5 lines

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 18
Quoted 2 lines
hw/ppc/spapr_hcall.c +2 -0
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
You can't assume this. Please compute the value at the same place you compute the rtas-size.

sure

Quoted 29 lines

hw/ppc/spapr_hcall.c +28 -0

+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors

Quoted 8 lines

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 51
Quoted 5 lines
hw/ppc/spapr_hcall.c +5 -0
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
Please don't include Linux code. This file is GPLv2+ licensed and I don't want to taint it as GPLv2 only just for the sake of mce.

Hmm.. ok. In that case I should not copy rtas_error_log structure below from kernel source as well.

Quoted 55 lines

hw/ppc/spapr_hcall.c +47 -0

+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved
+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};
+
+/*
+ * Data format in RTAS-Blob
+ *
+ * This structure contains error information related to Machine
+ * Check exception. This is filled up and copied to rtas-blob
+ * upon machine check exception.
+ */
+struct rtas_mc_log {
+    target_ulong srr0;
+    target_ulong srr1;
+    /*
+     * Beginning of error log address. This is properly
+     * populated and passed on to OS registered machine
+     * check notification routine upon machine check
+     * exception
+     */
+    target_ulong r3;
+    struct rtas_error_log err_log;
+};
+
 static void do_spr_sync(void *arg)
 {
     struct SPRSyncState *s = arg;

@@ -586,6 +668,77 @@ static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     return 0;
 }

Quoted 16 lines

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 683

Quoted 13 lines

hw/ppc/spapr_hcall.c +13 -0

+static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+                                 target_ulong opcode, target_ulong *args)
+{
+    struct rtas_mc_log mc_log;
+    CPUPPCState *env = &cpu->env;
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+    /*
+     * We save the original r3 register in SPRG2 in 0x200 vector,
+     * which is patched during call to ibm.nmi-register. Original
+     * r3 is required to be included in error log
+     */
+    mc_log.r3 = env->spr[SPR_SPRG2];

Don't you have to call cpu_synchronize_registers() before you access SPRG2? Otherwise the value may be stale.

Yes true. Will include.

Quoted 24 lines

hw/ppc/spapr_hcall.c +23 -0

+
+    /*
+     * SRR0 and SRR1, containing nip and msr at the time of exception,
+     * are clobbered when we return from this hcall. Hence they
+     * need to be properly saved and restored. We save srr0
+     * and srr1 in rtas blob and restore it in 0x200 vector
+     * before branching to OS registered machine check handler
+     */
+    mc_log.srr0 = env->spr[SPR_SRR0];
+    mc_log.srr1 = env->spr[SPR_SRR1];
+
+    /* Set error log fields */
+    mc_log.err_log.byte0 = 0x00;
+    mc_log.err_log.byte1 =
+        (RTAS_SEVERITY_ERROR_SYNC << RTAS_ELOG_SEVERITY_SHIFT);
+    mc_log.err_log.byte1 |=
+        (RTAS_DISP_NOT_RECOVERED << RTAS_ELOG_DISPOSITION_SHIFT);
+    mc_log.err_log.byte2 =
+        (RTAS_INITIATOR_MEMORY << RTAS_ELOG_INITIATOR_SHIFT);
+    mc_log.err_log.byte2 |= RTAS_TARGET_MEMORY;
+
+    if (env->spr[SPR_DSISR] & P7_DSISR_MC_UE) {
+        mc_log.err_log.byte3 = RTAS_TYPE_ECC_UNCORR;

Quoted 8 lines

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 712
Quoted 6 lines
hw/ppc/spapr_hcall.c +6 -0
+    } else {
+        mc_log.err_log.byte3 = 0x0;
+    }
+
+    /* Handle all Host/Guest LE/BE combinations */
+    if ((*pcc->interrupts_big_endian)(cpu)) {
This should check MSR.LE, not ILE.

I did not quite get you. Did you mean to say I should check LE bit in MSR instead of invoking pcc->interrupts_big_endian?

If so I should also change that check in 4/4 where I patch 0x200.

Regards,
Aravinda

Quoted 4 lines

Alex

Signature · 2 lines

Regards,
Aravinda

Alexander Graf

2014-09-05 08:39 UTC #10 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/4] target-ppc: Build error log

Quoted 193 lines · Aravinda Prasad

Quoted 33 lines · Alexander Graf

Quoted 30 lines · Aravinda Prasad
Whenever there is a physical memory error due to bit flips, which cannot be corrected by hardware, the error is passed on to the kernel. If the memory address in error belongs to guest address space then guest kernel is responsible to take action. Hence the error is passed on to guest via KVM by invoking 0x200 NMI vector.
However, guest OS, as per PAPR, expects an error log upon such error. This patch registers a new hcall which is issued from 0x200 interrupt vector and builds the error log, copies the error log to rtas space and passes the address of the error log to guest
Enhancement to KVM to perform above functionality is already in upstream kernel.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)
hw/ppc/spapr_hcall.c +0 -0
index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 

Quoted 5 lines

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 18
Quoted 2 lines
hw/ppc/spapr_hcall.c +2 -0
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
You can't assume this. Please compute the value at the same place you compute the rtas-size.

sure

Quoted 29 lines

hw/ppc/spapr_hcall.c +28 -0

+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors

Quoted 8 lines

hw/ppc/spapr_hcall.c struct SPRSyncState { · line 51
Quoted 5 lines
hw/ppc/spapr_hcall.c +5 -0
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
Please don't include Linux code. This file is GPLv2+ licensed and I don't want to taint it as GPLv2 only just for the sake of mce.

Hmm.. ok. In that case I should not copy rtas_error_log structure below from kernel source as well.

Quoted 55 lines

hw/ppc/spapr_hcall.c +47 -0

+ */
+#define PPC_BIT(bit)                (0x8000000000000000ULL >> bit)
+#define P7_DSISR_MC_UE              (PPC_BIT(48))  /* P8 too */
+
+/* Adopted from kernel source arch/powerpc/include/asm/rtas.h */
+struct rtas_error_log {
+    /* Byte 0 */
+    uint8_t     byte0;          /* Architectural version */
+
+    /* Byte 1 */
+    uint8_t     byte1;
+    /* XXXXXXXX
+     * XXX      3: Severity level of error
+     *    XX    2: Degree of recovery
+     *      X   1: Extended log present?
+     *       XX 2: Reserved
+     */
+
+    /* Byte 2 */
+    uint8_t     byte2;
+    /* XXXXXXXX
+     * XXXX     4: Initiator of event
+     *     XXXX 4: Target of failed operation
+     */
+    uint8_t     byte3;          /* General event or error*/
+};
+
+/*
+ * Data format in RTAS-Blob
+ *
+ * This structure contains error information related to Machine
+ * Check exception. This is filled up and copied to rtas-blob
+ * upon machine check exception.
+ */
+struct rtas_mc_log {
+    target_ulong srr0;
+    target_ulong srr1;
+    /*
+     * Beginning of error log address. This is properly
+     * populated and passed on to OS registered machine
+     * check notification routine upon machine check
+     * exception
+     */
+    target_ulong r3;
+    struct rtas_error_log err_log;
+};
+
 static void do_spr_sync(void *arg)
 {
     struct SPRSyncState *s = arg;

@@ -586,6 +668,77 @@ static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     return 0;
 }

Quoted 16 lines

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 683

Quoted 13 lines

hw/ppc/spapr_hcall.c +13 -0

+static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr,
+                                 target_ulong opcode, target_ulong *args)
+{
+    struct rtas_mc_log mc_log;
+    CPUPPCState *env = &cpu->env;
+    PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+    /*
+     * We save the original r3 register in SPRG2 in 0x200 vector,
+     * which is patched during call to ibm.nmi-register. Original
+     * r3 is required to be included in error log
+     */
+    mc_log.r3 = env->spr[SPR_SPRG2];

Don't you have to call cpu_synchronize_registers() before you access SPRG2? Otherwise the value may be stale.

Yes true. Will include.

Quoted 24 lines

hw/ppc/spapr_hcall.c +23 -0

+
+    /*
+     * SRR0 and SRR1, containing nip and msr at the time of exception,
+     * are clobbered when we return from this hcall. Hence they
+     * need to be properly saved and restored. We save srr0
+     * and srr1 in rtas blob and restore it in 0x200 vector
+     * before branching to OS registered machine check handler
+     */
+    mc_log.srr0 = env->spr[SPR_SRR0];
+    mc_log.srr1 = env->spr[SPR_SRR1];
+
+    /* Set error log fields */
+    mc_log.err_log.byte0 = 0x00;
+    mc_log.err_log.byte1 =
+        (RTAS_SEVERITY_ERROR_SYNC << RTAS_ELOG_SEVERITY_SHIFT);
+    mc_log.err_log.byte1 |=
+        (RTAS_DISP_NOT_RECOVERED << RTAS_ELOG_DISPOSITION_SHIFT);
+    mc_log.err_log.byte2 =
+        (RTAS_INITIATOR_MEMORY << RTAS_ELOG_INITIATOR_SHIFT);
+    mc_log.err_log.byte2 |= RTAS_TARGET_MEMORY;
+
+    if (env->spr[SPR_DSISR] & P7_DSISR_MC_UE) {
+        mc_log.err_log.byte3 = RTAS_TYPE_ECC_UNCORR;

Quoted 8 lines

hw/ppc/spapr_hcall.c static target_ulong h_rtas_update(PowerPCCPU *cpu, sPAPREnvironment *spapr, · line 712
Quoted 6 lines
hw/ppc/spapr_hcall.c +6 -0
+    } else {
+        mc_log.err_log.byte3 = 0x0;
+    }
+
+    /* Handle all Host/Guest LE/BE combinations */
+    if ((*pcc->interrupts_big_endian)(cpu)) {
This should check MSR.LE, not ILE.

Quoted 4 lines

I did not quite get you. Did you mean to say I should check LE bit in MSR instead of invoking pcc->interrupts_big_endian?
If so I should also change that check in 4/4 where I patch 0x200.

Not quite - the 0x200 patch should look at ILE, because it gets executed with ILE endianness. But at the point in time when this hypercall gets issued, ILE doesn't contain useful information for us - what we care about is whether the hypercall was triggered from little endian context.

Alex

Alexey Kardashevskiy

2014-09-11 01:24 UTC #11 lore raw

Re: [Qemu-devel] [Qemu-ppc] [PATCH v2 3/4] target-ppc: Build error log

In reply to Aravinda Prasad

Quoted 83 lines · Aravinda Prasad

Quoted 33 lines · Alexander Graf
Quoted 30 lines · Aravinda Prasad
Whenever there is a physical memory error due to bit flips, which cannot be corrected by hardware, the error is passed on to the kernel. If the memory address in error belongs to guest address space then guest kernel is responsible to take action. Hence the error is passed on to guest via KVM by invoking 0x200 NMI vector.
However, guest OS, as per PAPR, expects an error log upon such error. This patch registers a new hcall which is issued from 0x200 interrupt vector and builds the error log, copies the error log to rtas space and passes the address of the error log to guest
Enhancement to KVM to perform above functionality is already in upstream kernel.
Signed-off-by Aravinda Prasad <[email protected]>
---
 hw/ppc/spapr_hcall.c   |  154 ++++++++++++++++++++++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |    4 +
 2 files changed, 157 insertions(+), 1 deletion(-)
hw/ppc/spapr_hcall.c +0 -0
index 01650ba..c3aa448 100644
@@ -14,6 +14,88 @@ struct SPRSyncState {
     target_ulong mask;
 };
 
Quoted 5 lines
hw/ppc/spapr_hcall.c struct SPRSyncState { · line 18
Quoted 2 lines
hw/ppc/spapr_hcall.c +2 -0
+/* Offset from rtas-base where error log is placed */
+#define RTAS_ERROR_OFFSET       (TARGET_PAGE_SIZE)
You can't assume this. Please compute the value at the same place you compute the rtas-size.
sure
Quoted 29 lines
Quoted 29 lines
hw/ppc/spapr_hcall.c +28 -0
+
+#define RTAS_ELOG_SEVERITY_SHIFT         0x5
+#define RTAS_ELOG_DISPOSITION_SHIFT      0x3
+#define RTAS_ELOG_INITIATOR_SHIFT        0x4
+
+/*
+ * Only required RTAS event severity, disposition, initiator
+ * target and type are copied from arch/powerpc/include/asm/rtas.h
+ */
+
+/* RTAS event severity */
+#define RTAS_SEVERITY_ERROR_SYNC    0x3
+
+/* RTAS event disposition */
+#define RTAS_DISP_NOT_RECOVERED     0x2
+
+/* RTAS event initiator */
+#define RTAS_INITIATOR_MEMORY       0x4
+
+/* RTAS event target */
+#define RTAS_TARGET_MEMORY          0x4
+
+/* RTAS event type */
+#define RTAS_TYPE_ECC_UNCORR        0x09
+
+/*
+ * Currently KVM only passes on the uncorrected machine
+ * check memory error to guest. Other machine check errors
Quoted 8 lines
hw/ppc/spapr_hcall.c struct SPRSyncState { · line 51
Quoted 5 lines
hw/ppc/spapr_hcall.c +5 -0
+ * such as SLB multi-hit and TLB multi-hit are recovered
+ * in KVM and are not passed on to guest.
+ *
+ * DSISR Bit for uncorrected machine check error. Based
+ * on arch/powerpc/include/asm/mce.h
Please don't include Linux code. This file is GPLv2+ licensed and I don't want to taint it as GPLv2 only just for the sake of mce.

Quoted 2 lines

Hmm.. ok. In that case I should not copy rtas_error_log structure below from kernel source as well.

I double checked with Alex and since arch/powerpc/include/asm/mce.h is GPL2+ and spapr_hcall.c does not have a license so it is what QEMU's license is (which is also GPL2+), copying is fine here.

Signature · 5 lines

Alexey Kardashevskiy
IBM OzLabs, LTC Team

e-mail: [email protected]
notes: Alexey Kardashevskiy/Australia/IBM