KVM: x86: nVMX: support for MSR loading/storing
PATCH 1/1 KVM: x86: nVMX: support for MSR loading/storing
Several hypervisors use MSR loading/storing to run guests on VMX. This patch implements emulation of this feature and allows these hypervisors to work in L1.
The following is emulated:
- Loading MSRs on VM-entries
- Saving MSRs on VM-exits
- Loading MSRs on VM-exits
Actions taken on loading MSRs:
- MSR load area is verified
- For each MSR entry from load area:
- MSR load entry is read and verified
- MSR value is safely written
Actions taken on storing MSRs:
- MSR store area is verified
- For each MSR entry from store area:
- MSR entry is read and verified
- MSR value is safely read using MSR index from MSR entry
- MSR value is written to MSR entry
The code performs checks required by Intel Software Developer Manual.
--- arch/x86/include/asm/vmx.h | 6 + arch/x86/include/uapi/asm/msr-index.h | 3 + arch/x86/include/uapi/asm/vmx.h | 2 + arch/x86/kvm/vmx.c | 206 ++++++++++++++++++++++++++++++++-- virt/kvm/kvm_main.c | 1 + 5 files changed, 211 insertions(+), 7 deletions(-)
arch/x86/include/asm/vmx.h +6 -0
@@ -457,6 +457,12 @@ struct vmx_msr_entry {#define ENTRY_FAIL_VMCS_LINK_PTR 4/* +* VMX Abort codes +*/ +#define VMX_ABORT_MSR_STORE_FAILURE 1 +#define VMX_ABORT_MSR_LOAD_FAILURE 4 + +/* * VM-instruction error numbers */ enum vm_instruction_error_number {
arch/x86/include/uapi/asm/msr-index.h +3 -0
@@ -316,6 +316,9 @@#define MSR_IA32_UCODE_WRITE 0x00000079#define MSR_IA32_UCODE_REV 0x0000008b +#define MSR_IA32_SMM_MONITOR_CTL 0x0000009b +#define MSR_IA32_SMBASE 0x0000009e +#define MSR_IA32_PERF_STATUS 0x00000198#define MSR_IA32_PERF_CTL 0x00000199#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064
arch/x86/include/uapi/asm/vmx.h +2 -0
@@ -56,6 +56,7 @@#define EXIT_REASON_MSR_READ 31#define EXIT_REASON_MSR_WRITE 32#define EXIT_REASON_INVALID_STATE 33 +#define EXIT_REASON_MSR_LOAD_FAILURE 34#define EXIT_REASON_MWAIT_INSTRUCTION 36#define EXIT_REASON_MONITOR_INSTRUCTION 39#define EXIT_REASON_PAUSE_INSTRUCTION 40
@@ -116,6 +117,7 @@ { EXIT_REASON_APIC_WRITE, "APIC_WRITE" }, \ { EXIT_REASON_EOI_INDUCED, "EOI_INDUCED" }, \ { EXIT_REASON_INVALID_STATE, "INVALID_STATE" }, \ + { EXIT_REASON_MSR_LOAD_FAILURE, "MSR_LOAD_FAILURE" }, \ { EXIT_REASON_INVD, "INVD" }, \ { EXIT_REASON_INVVPID, "INVVPID" }, \ { EXIT_REASON_INVPCID, "INVPCID" }, \
arch/x86/kvm/vmx.c +199 -7
250 lines not on this page · raw message
virt/kvm/kvm_main.c +1 -0
@@ -1579,6 +1579,7 @@ int kvm_write_guest(struct kvm *kvm, gpa_t gpa, const void *data, }return 0 ; } +EXPORT_SYMBOL_GPL (kvm_write_guest);int kvm_gfn_to_hva_cache_init (struct kvm *kvm,struct gfn_to_hva_cache *ghc,gpa_t gpa,unsigned long len)
Signature · 1 line
2.0.4
2014-12-10 00:18+0300, Eugene Korenevsky:
Quoted 2 lines
arch/x86/kvm/vmx.c +2
-0+static bool vmx_load_msr_entry_verify (struct kvm_vcpu *vcpu, +struct vmx_msr_entry *e)
[...]
arch/x86/kvm/vmx.c static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12) · line 8629
Quoted 3 lines
arch/x86/kvm/vmx.c +3
-0+/* x2APIC MSR accesses are not allowed */ +if (apic_x2apic_mode (vcpu->arch.apic) && (e->index >>24 ) ==0x800 ) +return false;
GCC doesn't warn that "((u32)e->index >> 24) == 0x800" is always false? I think SDM says '(e->index >> 8) == 0x8'.
Quoted 2 lines
GCC doesn't warn that "((u32)e->index >> 24) ==
0x800" is always false? I think SDM says '(e->index>> 8) ==0x8'.
Missed that. Thank you.
Signature · 1 line
Eugene
Will send fixed patch this evening.
Signature · 1 line
Eugene
Quoted 1 line · Eugene Korenevsky
Will send fixed patch this evening.
Please see my reply to another thread.
Quoted 7 lines
Signature · 6 lines
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