PCI: PCIe endpoint initiating write request to RC

Hi,

I have a doubt, hope some one would have come across the same,

For a root complex to send data to PCIe endpoints, Then it has to write data that could hit the BAR region of PCIe endpoints.

For a vice versa, if PCIe endpoint which doesn't has DMA descriptor in it and it is trying to send data. which address I need to configure? Any physical address of ram or physical address got for kmalloc or endpoint BAR?

If PCIe endpoint can access the entire memory does it has a permission to corrupt the host memory from external. We know linux handle memory violation for process by memory structure assigned in each task_struct. But can someone explain me how it been managed for data comming out from endpoint to Root complex?

Regards
Nobel