x86 fixes
Linus,
Please pull the latest x86-urgent-for-linus git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-urgent-for-linus
# HEAD: 452308de61056a539352a9306c46716d7af8a1f1 x86/efi: Fix boot crash by always mapping boot service regions into new EFI page tables
This fixes 3 FPU handling related bugs, an EFI boot crash and a runtime warning.
The EFI fix arrived late but I didn't want to delay it to after v4.5 because the effects are pretty bad for the systems that are affected by it.
Thanks,
Ingo
------------------>
Andy Lutomirski (1):
x86/fpu: Fix 'no387' regression
Borislav Petkov (2):
x86/delay: Avoid preemptible context checks in delay_mwaitx() x86/fpu: Fix eager-FPU handling on legacy FPU machines
Matt Fleming (1):
x86/efi: Fix boot crash by always mapping boot service regions into new EFI page tables
Yu-cheng Yu (1):
x86/fpu: Revert ("x86/fpu: Disable AVX when eagerfpu is off")
arch/x86/include/asm/fpu/xstate.h | 9 ++--- arch/x86/kernel/fpu/core.c | 4 +- arch/x86/kernel/fpu/init.c | 22 +++++------ arch/x86/lib/delay.c | 2 +- arch/x86/platform/efi/quirks.c | 79 ++++++++++++++++++++++++++++++--------- 5 files changed, 79 insertions(+), 37 deletions(-)
arch/x86/include/asm/fpu/xstate.h +4 -5
@@ -20,16 +20,15 @@/* Supported features which support lazy state saving */ #define XFEATURE_MASK_LAZY (XFEATURE_MASK_FP | \ - XFEATURE_MASK_SSE) - -/* Supported features which require eager state saving */ -#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | \ - XFEATURE_MASK_BNDCSR | \ + XFEATURE_MASK_SSE | \ XFEATURE_MASK_YMM | \ XFEATURE_MASK_OPMASK | \ XFEATURE_MASK_ZMM_Hi256 | \ XFEATURE_MASK_Hi16_ZMM) +/* Supported features which require eager state saving */ +#define XFEATURE_MASK_EAGER (XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR) +/* All currently supported features */ #define XCNTXT_MASK (XFEATURE_MASK_LAZY | XFEATURE_MASK_EAGER)
arch/x86/kernel/fpu/core.c +3 -1
@@ -409,8 +409,10 @@ static inline void copy_init_fpstate_to_fpregs(void) {if (use_xsave ())copy_kernel_to_xregs (&init_fpstate.xsave,-1 ); -else +else if (static_cpu_has (X86_FEATURE_FXSR ))copy_kernel_to_fxregs (&init_fpstate.fxsave); +else +copy_kernel_to_fregs (&init_fpstate.fsave); }/*
arch/x86/kernel/fpu/init.c +9 -13
@@ -78,13 +78,15 @@ static void fpu__init_system_early_generic(struct cpuinfo_x86 *c) cr0 &= ~(X86_CR0_TS |X86_CR0_EM );write_cr0 (cr0); - asmvolatile ("fninit ; fnstsw %0 ; fnstcw %1" - :"+m" (fsw),"+m" (fcw)); +if (!test_bit (X86_FEATURE_FPU , (unsigned long *)cpu_caps_cleared)) { + asmvolatile ("fninit ; fnstsw %0 ; fnstcw %1" + :"+m" (fsw),"+m" (fcw)); -if (fsw ==0 && (fcw &0x103f ) ==0x003f ) -set_cpu_cap (c,X86_FEATURE_FPU ); -else -clear_cpu_cap (c,X86_FEATURE_FPU ); +if (fsw ==0 && (fcw &0x103f ) ==0x003f ) +set_cpu_cap (c,X86_FEATURE_FPU ); +else +clear_cpu_cap (c,X86_FEATURE_FPU ); + }#ifndef CONFIG_MATH_EMULATION if (!cpu_has_fpu) {
@@ -132,7 +134,7 @@ static void __init fpu__init_system_generic(void)* Set up the legacy init FPU context. (xstate init might overwrite this * with a more modern format, if the CPU supports it.) */ -fpstate_init_fxstate (&init_fpstate.fxsave); +fpstate_init (&init_fpstate);fpu__init_system_mxcsr (); }
@@ -300,12 +302,6 @@ u64 __init fpu__get_supported_xfeatures_mask(void)static void __init fpu__clear_eager_fpu_features (void ) {setup_clear_cpu_cap (X86_FEATURE_MPX ); -setup_clear_cpu_cap (X86_FEATURE_AVX ); -setup_clear_cpu_cap (X86_FEATURE_AVX2 ); -setup_clear_cpu_cap (X86_FEATURE_AVX512F ); -setup_clear_cpu_cap (X86_FEATURE_AVX512PF ); -setup_clear_cpu_cap (X86_FEATURE_AVX512ER ); -setup_clear_cpu_cap (X86_FEATURE_AVX512CD ); }/*
arch/x86/lib/delay.c +1 -1
@@ -102,7 +102,7 @@ static void delay_mwaitx(unsigned long __loops)* Use cpu_tss as a cacheline-aligned, seldomly * accessed per-cpu variable as the monitor target. */ -__monitorx (this_cpu_ptr (&cpu_tss),0 ,0 ); +__monitorx (raw_cpu_ptr (&cpu_tss),0 ,0 );/* * AMD, like Intel, supports the EAX hint and EAX=0xf
arch/x86/platform/efi/quirks.c +62 -17
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