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perf fixes

GIT PULL Ingo Molnar 1 participant 1 message Apr 28, 2016

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Ingo Molnar

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Linus,

Please pull the latest perf-urgent-for-linus git tree from:

git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-for-linus

# HEAD: cf3beb7c90a8efa16a06b26634cddddc92bb819c perf/x86/intel: Fix incorrect lbr_sel_mask value

x86 PMU driver fixes plus a core code race fix.

Thanks,

Ingo

------------------>
Adam Borowski (1):
perf/x86/amd: Set the size of event map array to PERF_COUNT_HW_MAX

Alexander Shishkin (1):
perf/x86/intel/pt: Don't die on VMXON

Andi Kleen (1):
perf/x86/intel: Add model number for Skylake Server to perf

Kan Liang (1):
perf/x86/intel: Fix incorrect lbr_sel_mask value

Peter Zijlstra (2):
perf/core: Make sysctl_perf_cpu_time_max_percent conform to documentation perf/core: Fix perf_event_open() vs. execve() race

Srinivas Pandruvada (1):
perf/x86/intel/rapl: Add missing Haswell model

 arch/x86/events/amd/core.c        |  2 +-
 arch/x86/events/intel/core.c      |  1 +
 arch/x86/events/intel/lbr.c       |  6 ++--
 arch/x86/events/intel/pt.c        | 75 +++++++++++++++++++++++++++++++++------
 arch/x86/events/intel/pt.h        |  3 ++
 arch/x86/events/intel/rapl.c      |  1 +
 arch/x86/include/asm/perf_event.h |  4 +++
 arch/x86/kvm/vmx.c                |  4 +++
 kernel/events/core.c              | 55 +++++++++++++++++++---------
 9 files changed, 120 insertions(+), 31 deletions(-)
arch/x86/events/amd/core.c +1 -1
index 86a9bec18dab..bd3e8421b57c 100644
@@ -115,7 +115,7 @@ static __initconst const u64 amd_hw_cache_event_ids
 /*
  * AMD Performance Monitor K7 and later.
  */
-static const u64 amd_perfmon_event_map[] =
+static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
 {
   [PERF_COUNT_HW_CPU_CYCLES]			= 0x0076,
   [PERF_COUNT_HW_INSTRUCTIONS]			= 0x00c0,
arch/x86/events/intel/core.c +1 -0
index 68fa55b4d42e..aff79884e17d 100644
@@ -3639,6 +3639,7 @@ __init int intel_pmu_init(void)
 
 	case 78: /* 14nm Skylake Mobile */
 	case 94: /* 14nm Skylake Desktop */
+	case 85: /* 14nm Skylake Server */
 		x86_pmu.late_ack = true;
 		memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
arch/x86/events/intel/lbr.c +4 -2
index 6c3b7c1780c9..1ca5d1e7d4f2 100644
@@ -63,7 +63,7 @@ static enum {
 
 #define LBR_PLM (LBR_KERNEL | LBR_USER)
 
-#define LBR_SEL_MASK	0x1ff	/* valid bits in LBR_SELECT */
+#define LBR_SEL_MASK	0x3ff	/* valid bits in LBR_SELECT */
 #define LBR_NOT_SUPP	-1	/* LBR filter not supported */
 #define LBR_IGN		0	/* ignored */
 

@@ -610,8 +610,10 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
 	 * The first 9 bits (LBR_SEL_MASK) in LBR_SELECT operate
 	 * in suppress mode. So LBR_SELECT should be set to
 	 * (~mask & LBR_SEL_MASK) | (mask & ~LBR_SEL_MASK)
+	 * But the 10th bit LBR_CALL_STACK does not operate
+	 * in suppress mode.
 	 */
-	reg->config = mask ^ x86_pmu.lbr_sel_mask;
+	reg->config = mask ^ (x86_pmu.lbr_sel_mask & ~LBR_CALL_STACK);
 
 	if ((br_type & PERF_SAMPLE_BRANCH_NO_CYCLES) &&
 	    (br_type & PERF_SAMPLE_BRANCH_NO_FLAGS) &&
arch/x86/events/intel/pt.c +64 -11

131 lines not on this page · raw message

arch/x86/events/intel/pt.h +3 -0
index 336878a5d205..3abb5f5cccc8 100644
@@ -65,6 +65,7 @@ enum pt_capabilities {
 struct pt_pmu {
 	struct pmu		pmu;
 	u32			caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
+	bool			vmx;
 };
 
 /**

@@ -107,10 +108,12 @@ struct pt_buffer {
  * struct pt - per-cpu pt context
  * @handle:	perf output handle
  * @handle_nmi:	do handle PT PMI on this cpu, there's an active event
+ * @vmx_on:	1 if VMX is ON on this cpu
  */
 struct pt {
 	struct perf_output_handle handle;
 	int			handle_nmi;
+	int			vmx_on;
 };
 
 #endif /* __INTEL_PT_H__ */
arch/x86/events/intel/rapl.c +1 -0
index 70c93f9b03ac..1705c9d75e44 100644
@@ -718,6 +718,7 @@ static int __init rapl_pmu_init(void)
 		break;
 	case 60: /* Haswell */
 	case 69: /* Haswell-Celeron */
+	case 70: /* Haswell GT3e */
 	case 61: /* Broadwell */
 	case 71: /* Broadwell-H */
 		rapl_cntr_mask = RAPL_IDX_HSW;
arch/x86/include/asm/perf_event.h +4 -0
index 5a2ed3ed2f26..f353061bba1d 100644
@@ -285,6 +285,10 @@ static inline void perf_events_lapic_init(void)	{ }
 static inline void perf_check_microcode(void) { }
 #endif
 
+#ifdef CONFIG_CPU_SUP_INTEL
+ extern void intel_pt_handle_vmx(int on);
+#endif
+
 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
  extern void amd_pmu_enable_virt(void);
  extern void amd_pmu_disable_virt(void);
arch/x86/kvm/vmx.c +4 -0
index ee1c8a93871c..133679d520af 100644
@@ -3103,6 +3103,8 @@ static __init int vmx_disabled_by_bios(void)
 
 static void kvm_cpu_vmxon(u64 addr)
 {
+	intel_pt_handle_vmx(1);
+
 	asm volatile (ASM_VMX_VMXON_RAX
 			: : "a"(&addr), "m"(addr)
 			: "memory", "cc");

@@ -3172,6 +3174,8 @@ static void vmclear_local_loaded_vmcss(void)
 static void kvm_cpu_vmxoff(void)
 {
 	asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
+
+	intel_pt_handle_vmx(0);
 }
 
 static void hardware_disable(void)
kernel/events/core.c +38 -17

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