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ARM: socfpga: add support for IS1 board

U-Boot Superseded Pavel Machek 2 participants 8 messages Jun 1, 2016 – Jun 8, 2016

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Pavel Machek

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#0 lore raw

This adds support for IS1 board.

Signed-off-by Pavel Machek <[email protected]>
arch/arm/dts/Makefile +1 -0
index 92c7545..a397c69 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
arch/arm/dts/socfpga_cyclone5_is1.dts new file +109 -0

109 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index dea4ce5..b11d510 100644
@@ -31,6 +31,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -53,6 +57,7 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "is1" if TARGET_SOCFPGA_IS1
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -73,5 +78,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 
 endif
board/is1/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..a737e13
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <[email protected]>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
board/is1/Makefile new file +5 -0
new file mode 100644
index 0000000..9ae6c0c
@@ -0,0 +1,5 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
board/is1/qts/iocsr_config.h new file +660 -0

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board/is1/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/is1/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/is1/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

configs/socfpga_is1_defconfig new file +43 -0

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include/configs/socfpga_is1.h new file +83 -0

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Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#1 lore raw
Quoted 1 line · Pavel Machek

This adds support for IS1 board.

Detailed description of the board would help.

arch/arm/dts/Makefile dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

Quoted 7 lines
Signed-off-by Pavel Machek <[email protected]>
arch/arm/dts/Makefile +0 -0
index 92c7545..a397c69 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb

Please send a patch with diffstat, it's impossible to tell whether everything is in the patch if there are such big files like the stuff in qts/ .

Signature · 2 lines
Best regards,
Marek Vasut
author
#2 lore raw

PATCH v2 1/1 ARM: socfpga: add support for IS1 board

In reply to Pavel Machek

This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.

Signed-off-by Pavel Machek <[email protected]>

---

v2: add diffstat

 arch/arm/dts/Makefile                 |    1 
 arch/arm/dts/socfpga_cyclone5_is1.dts |  109 +++++
 arch/arm/mach-socfpga/Kconfig         |    6 
 board/is1/MAINTAINERS                 |    6 
 board/is1/Makefile                    |    5 
 board/is1/qts/iocsr_config.h          |  660 ++++++++++++++++++++++++++++++++++
 board/is1/qts/pinmux_config.h         |  219 +++++++++++
 board/is1/qts/pll_config.h            |   85 ++++
 board/is1/qts/sdram_config.h          |  341 +++++++++++++++++
 configs/socfpga_is1_defconfig         |   43 ++
 include/configs/socfpga_is1.h         |   83 ++++
 11 files changed, 1558 insertions(+)
arch/arm/dts/Makefile +1 -0
index 92c7545..a397c69 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
arch/arm/dts/socfpga_cyclone5_is1.dts new file +109 -0

109 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index dea4ce5..b11d510 100644
@@ -31,6 +31,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -53,6 +57,7 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "is1" if TARGET_SOCFPGA_IS1
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -73,5 +78,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 
 endif
board/is1/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..a737e13
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <[email protected]>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
board/is1/Makefile new file +5 -0
new file mode 100644
index 0000000..9ae6c0c
@@ -0,0 +1,5 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
board/is1/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/is1/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/is1/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/is1/qts/sdram_config.h new file +341 -0

341 lines not on this page · raw message

configs/socfpga_is1_defconfig new file +43 -0

43 lines not on this page · raw message

include/configs/socfpga_is1.h new file +83 -0

83 lines not on this page · raw message

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
#3 lore raw

PATCH v2 1/1 ARM: socfpga: add support for IS1 board

Quoted 42 lines · Pavel Machek

This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.

Signed-off-by Pavel Machek <[email protected]>

---

v2: add diffstat

 arch/arm/dts/Makefile                 |    1 
 arch/arm/dts/socfpga_cyclone5_is1.dts |  109 +++++
 arch/arm/mach-socfpga/Kconfig         |    6 
 board/is1/MAINTAINERS                 |    6 
 board/is1/Makefile                    |    5 
 board/is1/qts/iocsr_config.h          |  660 ++++++++++++++++++++++++++++++++++
 board/is1/qts/pinmux_config.h         |  219 +++++++++++
 board/is1/qts/pll_config.h            |   85 ++++
 board/is1/qts/sdram_config.h          |  341 +++++++++++++++++
 configs/socfpga_is1_defconfig         |   43 ++
 include/configs/socfpga_is1.h         |   83 ++++
 11 files changed, 1558 insertions(+)
arch/arm/dts/Makefile +1 -0
index 92c7545..a397c69 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
arch/arm/dts/socfpga_cyclone5_is1.dts new file +0 -0
new file mode 100644
index 0000000..cdd2c99

arch/arm/dts/socfpga_cyclone5_is1.dts line 2

Quoted 2 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +2 -0
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>

This copyright notice needs to be updated.

arch/arm/dts/socfpga_cyclone5_is1.dts line 11

Quoted 8 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +8 -0
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "Altera SOCFPGA IS1 board";
+	compatible = "altr,socfpga-cyclone5", "altr,socfpga";

The compatible string needs at least one vendor-specific entry.

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +4 -0
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+

arch/arm/dts/socfpga_cyclone5_is1.dts line 26

Quoted 10 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +10 -0
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x10000000>;
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environment variable contents
+		 * to be added to the gmac1 device tree blob.
+		 */

Please just drop this comment or fix the formatting of multiline comment.

Quoted 15 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +15 -0
+		ethernet0 = &gmac1;
+		udc0 = &usb1;
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};

[...]

include/configs/socfpga_is1.h line 2

Quoted 8 lines
include/configs/socfpga_is1.h new file +2 -0
new file mode 100644
index 0000000..77c3193
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2014 Marek Vasut <[email protected]>

This copyright notice needs to be updated.

Quoted 18 lines
include/configs/socfpga_is1.h new file +18 -0
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_IS1_H__
+#define __CONFIG_SOCFPGA_IS1_H__
+
+#include <asm/arch/base_addr_ac5.h>
+
+/* U-Boot Commands */
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x10000000
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3

include/configs/socfpga_is1.h line 31

Quoted 10 lines
include/configs/socfpga_is1.h new file +10 -0
+#define CONFIG_BOOTFILE		"zImage"
+#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND	"run qspiload"
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII

These two are controlled by OF and not needed here.

Quoted 6 lines
include/configs/socfpga_is1.h new file +6 -0
+#define PHY_ANEG_TIMEOUT	8000
+#define CONFIG_ARP_TIMEOUT		500UL
+
+
+/* PHY */
+#define CONFIG_PHY_MICREL

include/configs/socfpga_is1.h line 47

Quoted 10 lines
include/configs/socfpga_is1.h new file +10 -0
+#define CONFIG_PHY_MICREL_KSZ9021
+#endif
+
+/*
+ * enable UBIFS support, it's required to load the FPGA netlist
+ * and/or other boot files (kernel, device tree) from QSPI flash
+ * when these files do not reside in their individual partitions
+ */
+#define CONFIG_RBTREE
+#define CONFIG_LZO

I believe these two are already defined in socfpga_common.h

include/configs/socfpga_is1.h line 52

Quoted 4 lines
include/configs/socfpga_is1.h new file +4 -0
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

This loadaddr is set by CONFIG_LOADADDR (above)

Quoted 8 lines
include/configs/socfpga_is1.h new file +8 -0
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \

include/configs/socfpga_is1.h line 70

Quoted 10 lines
include/configs/socfpga_is1.h new file +10 -0
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"uboot_env_complete=yes\0"

Can we drop this extra environment? It looks like a copy of the CV SoCDK env, which is broken nonetheless, so unless it's used, drop it in V3 please.

Quoted 14 lines
include/configs/socfpga_is1.h new file +12 -0
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR       0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE
+ 
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_IS1_H__ */
Signature · 2 lines
Best regards,
Marek Vasut
author
#4 lore raw

PATCH v2 1/1 ARM: socfpga: add support for IS1 board

Hi!

Quoted 7 lines

arch/arm/dts/socfpga_cyclone5_is1.dts line 2

Quoted 5 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +2 -0
@@ -0,0 +1,109 @@
+/*
+ *  Copyright (C) 2012 Altera Corporation <www.altera.com>

This copyright notice needs to be updated.

How? dts is probably not copyrightable, and my changes are certainly not complex enough for copyright protection.

Quoted 6 lines

arch/arm/dts/socfpga_cyclone5_is1.dts line 6

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +4 -0
+/* Extra Environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \

This loadaddr is set by CONFIG_LOADADDR (above)

I'm not sure what you are trying to tell me, in any case socfpga_sr1500.h has same entry.

Quoted 14 lines
Quoted 14 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +14 -0
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiload=sf probe && mtdparts default && run ubiload\0" \
Quoted 8 lines

arch/arm/dts/socfpga_cyclone5_is1.dts line 24

Quoted 4 lines
arch/arm/dts/socfpga_cyclone5_is1.dts new file +4 -0
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"uboot_env_complete=yes\0"

Can we drop this extra environment? It looks like a copy of the CV SoCDK env, which is broken nonetheless, so unless it's used, drop it in V3 please.

We can drop the extra environment for now.

Best regards,
Pavel

Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#5 lore raw

PATCH v3 1/1 ARM: socfpga: add support for IS1 board

In reply to Pavel Machek

This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.

Signed-off-by Pavel Machek <[email protected]>

---

v2: add diffstat

v3: fixes from review, add empty socfpga.c to make build system happy.

 arch/arm/dts/Makefile                 |    1 
 arch/arm/dts/socfpga_cyclone5_is1.dts |  106 +++++
 arch/arm/mach-socfpga/Kconfig         |    6 
 board/is1/MAINTAINERS                 |    6 
 board/is1/Makefile                    |    7 
 board/is1/qts/iocsr_config.h          |  660 ++++++++++++++++++++++++++++++++++
 board/is1/qts/pinmux_config.h         |  219 +++++++++++
 board/is1/qts/pll_config.h            |   85 ++++
 board/is1/qts/sdram_config.h          |  341 +++++++++++++++++
 board/is1/socfpga.c                   |    4 
 configs/socfpga_is1_defconfig         |   43 ++
 include/configs/socfpga_is1.h         |   48 ++
 12 files changed, 1526 insertions(+)
arch/arm/dts/Makefile +1 -0
index 92c7545..a397c69 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
arch/arm/dts/socfpga_cyclone5_is1.dts new file +106 -0

106 lines not on this page · raw message

arch/arm/mach-socfpga/Kconfig +6 -0
index dea4ce5..b11d510 100644
@@ -31,6 +31,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -53,6 +57,7 @@ config SYS_BOARD
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "sr1500" if TARGET_SOCFPGA_SR1500
+	default "is1" if TARGET_SOCFPGA_IS1
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK

@@ -73,5 +78,6 @@ config SYS_CONFIG_NAME
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
 	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 
 endif
board/is1/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..a737e13
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <[email protected]>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
board/is1/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/is1/qts/iocsr_config.h new file +660 -0

660 lines not on this page · raw message

board/is1/qts/pinmux_config.h new file +219 -0

219 lines not on this page · raw message

board/is1/qts/pll_config.h new file +85 -0

85 lines not on this page · raw message

board/is1/qts/sdram_config.h new file +341 -0

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board/is1/socfpga.c new file +4 -0
new file mode 100644
index 0000000..2a543bf
@@ -0,0 +1,4 @@
+/*
+ * Currently nothing special is needed on this board, empty file to
+ * make build scripts happy
+ */
configs/socfpga_is1_defconfig new file +43 -0

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include/configs/socfpga_is1.h new file +48 -0

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Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
author
#6 lore raw

PATCH v4 1/1 ARM: socfpga: add support for IS1 board

This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.

Signed-off-by Pavel Machek <[email protected]>

---

v2: add diffstat

v3: fixes from review, add empty socfpga.c to make build system happy.

v4: fixes from review, declare that environment is in spi flash.

 arch/arm/dts/Makefile                 |    1 
 arch/arm/dts/socfpga_cyclone5_is1.dts |  106 +++++
 arch/arm/mach-socfpga/Kconfig         |    6 
 board/is1/MAINTAINERS                 |    6 
 board/is1/Makefile                    |    7 
 board/is1/qts/iocsr_config.h          |  660 ++++++++++++++++++++++++++++++++++
 board/is1/qts/pinmux_config.h         |  219 +++++++++++
 board/is1/qts/pll_config.h            |   85 ++++
 board/is1/qts/sdram_config.h          |  341 +++++++++++++++++
 board/is1/socfpga.c                   |    4 
 configs/socfpga_is1_defconfig         |   43 ++
 include/configs/socfpga_is1.h         |   49 ++
 12 files changed, 1527 insertions(+)
arch/arm/dts/Makefile +1 -0
index e76f56b..3738511 100644
@@ -102,6 +102,7 @@ dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
 
 dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_arria5_socdk.dtb			\
+	socfpga_cyclone5_is1.dtb			\
 	socfpga_cyclone5_mcvevk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
arch/arm/dts/socfpga_cyclone5_is1.dts new file +106 -0

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arch/arm/mach-socfpga/Kconfig +6 -0
index 1484607..cbc9cf6 100644
@@ -31,6 +31,10 @@ config TARGET_SOCFPGA_SR1500
 	bool "SR1500 (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_IS1
+	bool "IS1 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_EBV_SOCRATES
 	bool "EBV SoCrates (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5

@@ -53,6 +57,7 @@ config SYS_BOARD
 	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "is1" if TARGET_SOCFPGA_IS1	
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES

@@ -75,6 +80,7 @@ config SYS_CONFIG_NAME
 	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
 	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
+	default "socfpga_is1" if TARGET_SOCFPGA_IS1
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
 	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
board/is1/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..a737e13
@@ -0,0 +1,6 @@
+SOCFPGA IS1 BOARD
+M:	Pavel Machek <[email protected]>
+S:	Maintained
+F:	board/is1/
+F:	include/configs/socfpga_is1.h
+F:	configs/socfpga_is1_defconfig
board/is1/Makefile new file +7 -0
new file mode 100644
index 0000000..eae7ad0
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015 Stefan Roese <[email protected]>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
board/is1/qts/iocsr_config.h new file +660 -0

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board/is1/qts/pinmux_config.h new file +219 -0

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board/is1/qts/pll_config.h new file +85 -0

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board/is1/qts/sdram_config.h new file +341 -0

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board/is1/socfpga.c new file +4 -0
new file mode 100644
index 0000000..2a543bf
@@ -0,0 +1,4 @@
+/*
+ * Currently nothing special is needed on this board, empty file to
+ * make build scripts happy
+ */
configs/socfpga_is1_defconfig new file +43 -0

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include/configs/socfpga_is1.h new file +49 -0

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Signature · 2 lines
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
Applied
#7 lore raw

PATCH v4 1/1 ARM: socfpga: add support for IS1 board

Quoted 7 lines · Pavel Machek

This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA.

Signed-off-by Pavel Machek <[email protected]>

[...]

Applied, thanks.

Signature · 2 lines
Best regards,
Marek Vasut