spi: dw: round up result of calculation for clock divider
PATCH v2 2/2 spi: dw: round up result of calculation for clock divider
Avoid ending up with a higher frequency than requested
---
Previously failing example:
requested transfer freq: 16MHzmax_freq = 200MHz
calculated clk_div = 12
actual frequency = 200/12 = 16.6666MHz
--- drivers/spi/spi-dw.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/spi/spi-dw.c +2 -1
@@ -300,7 +300,8 @@ static int dw_spi_transfer_one(struct spi_master *master,if (transfer->speed_hz != dws->current_freq) {if (transfer->speed_hz != chip->speed_hz) {/* clk_div doesn't support odd number */ - chip->clk_div = (dws->max_freq / transfer->speed_hz +1 ) &0xfffe ; + chip->clk_div = ((dws->max_freq + transfer->speed_hz) / + transfer->speed_hz +1 ) &0xfffe ; chip->speed_hz = transfer->speed_hz; } dws->current_freq = transfer->speed_hz;
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drivers/spi/spi-dw.c static int dw_spi_transfer_one(struct spi_master *master, · line 304
Quoted 4 lines · Matthias Seidel
drivers/spi/spi-dw.c +2
-1/* clk_div doesn't support odd number */ - chip->clk_div = (dws->max_freq / transfer->speed_hz +1 ) &0xfffe ; + chip->clk_div = ((dws->max_freq + transfer->speed_hz) / + transfer->speed_hz +1 ) &0xfffe ;
Can we not use DIV_ROUND_UP here if that's what we're trying to do? The above probably needs a comment if not, I'm finding the intent rather confusing looking at the code.
PATCH v3 2/2 spi: dw: round up result of calculation for clock divider
In reply to a message not in the archiveAvoid ending up with a higher frequency than requested
---
Previously failing example:
requested transfer freq: 16MHzmax_freq = 200MHz
calculated clk_div = 12
actual frequency = 200/12 = 16.6666MHz
v3: I wasn't aware of this macro, better readability.
--- drivers/spi/spi-dw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/spi/spi-dw.c +1 -1
@@ -300,7 +300,7 @@ static int dw_spi_transfer_one(struct spi_master *master,if (transfer->speed_hz != dws->current_freq) {if (transfer->speed_hz != chip->speed_hz) {/* clk_div doesn't support odd number */ - chip->clk_div = (dws->max_freq / transfer->speed_hz +1 ) &0xfffe ; + chip->clk_div = (DIV_ROUND_UP (dws->max_freq, transfer->speed_hz) +1 ) &0xfffe ; chip->speed_hz = transfer->speed_hz; } dws->current_freq = transfer->speed_hz;
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Quoted 1 line · Matthias Seidel
Avoid ending up with a higher frequency than requested
I'm missing patch 1/2 here?
PATCH v4 1/1 spi: dw: round up result of calculation for clock divider
In reply to a message not in the archiveAvoid ending up with a higher frequency than requested
---
v4: Corrected subject, thanks for your work!
Previously failing example:
requested transfer freq: 16MHzmax_freq = 200MHz
calculated clk_div = 12
actual frequency = 200/12 = 16.6666MHz
--- drivers/spi/spi-dw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/spi/spi-dw.c +1 -1
@@ -300,7 +300,7 @@ static int dw_spi_transfer_one(struct spi_master *master,if (transfer->speed_hz != dws->current_freq) {if (transfer->speed_hz != chip->speed_hz) {/* clk_div doesn't support odd number */ - chip->clk_div = (dws->max_freq / transfer->speed_hz +1 ) &0xfffe ; + chip->clk_div = (DIV_ROUND_UP (dws->max_freq, transfer->speed_hz) +1 ) &0xfffe ; chip->speed_hz = transfer->speed_hz; } dws->current_freq = transfer->speed_hz;
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Applied "spi: dw: round up result of calculation for clock divider" to the spi tree
In reply to Matthias SeidelThe patch
spi: dw: round up result of calculation for clock divider
has been applied to the spi tree at
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying to this mail.
Thanks,
Mark
Quoted 1 line
From
3aef463222eaf1ca505629e93a0b64e4040a4472Mon Sep 17 00:00:00 2001
From: Matthias Seidel <[email protected]>
Date: Wed, 7 Sep 2016 17:45:30 +0200
Subject: [PATCH] spi: dw: round up result of calculation for clock divider
Avoid ending up with a higher frequency than requested
--- drivers/spi/spi-dw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/spi/spi-dw.c +1 -1
@@ -300,7 +300,7 @@ static int dw_spi_transfer_one(struct spi_master *master,if (transfer->speed_hz != dws->current_freq) {if (transfer->speed_hz != chip->speed_hz) {/* clk_div doesn't support odd number */ - chip->clk_div = (dws->max_freq / transfer->speed_hz +1 ) &0xfffe ; + chip->clk_div = (DIV_ROUND_UP (dws->max_freq, transfer->speed_hz) +1 ) &0xfffe ; chip->speed_hz = transfer->speed_hz; } dws->current_freq = transfer->speed_hz;
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