x86/platform/intel-mid: Add Intel Penwell to ID table

PATCH New Andy Shevchenko 2 participants 4 messages Sep 8, 2016

Subsystems (3)

x86 PCI Intel MID (Mobile Internet Device) platform

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Andy Shevchenko

author

2016-09-08 10:33 UTC #0 lore raw

PATCH 1/2 x86/platform/intel-mid: Add Intel Penwell to ID table

The commit ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell") enables the PWRMU driver on platforms based on Intel Penwell, unfortunately this is not enough.

Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the future add a comment to both drivers.

Fixes ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

Signed-off-by Andy Shevchenko <[email protected]>

---
 arch/x86/platform/intel-mid/pwr.c | 1 +
 drivers/pci/pci-mid.c             | 5 +++++
 2 files changed, 6 insertions(+)

arch/x86/platform/intel-mid/pwr.c +1 -0

index 2dfe998..146ed54 100644
@@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = {
 	.set_initial_state = mid_set_initial_state,
 };
 
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },

drivers/pci/pci-mid.c +5 -0

index b7ea64f..55f453d 100644
@@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = {
 
 #define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 
+/*
+ * This table should be in sync with the one in
+ * arch/x86/platform/intel-mid/pwr.c.
+ */
 static const struct x86_cpu_id lpss_cpu_ids[] = {
+	ICPU(INTEL_FAM6_ATOM_PENWELL),
 	ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
 	{}
 };

Signature · 1 line

2.9.3

Andy Shevchenko

author

2016-09-08 10:33 UTC #1 lore raw

PATCH 2/2 x86/platform/intel-mid: Keep SRAM powered on at boot

On Penwell SRAM has to be powered on, otherwise it prevents booting.

Fixes ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

Signed-off-by Andy Shevchenko <[email protected]>

---
 arch/x86/platform/intel-mid/pwr.c | 45 +++++++++++++++++++++++++++++++--------
 1 file changed, 36 insertions(+), 9 deletions(-)

arch/x86/platform/intel-mid/pwr.c +36 -9

index 146ed54..5d3b45a 100644
@@ -380,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	return 0;
 }
 
-static int mid_set_initial_state(struct mid_pwr *pwr)
+static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
 {
 	unsigned int i, j;
 	int ret;

@@ -405,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
 	 * NOTE: The actual device mapping is provided by a platform at run
 	 * time using vendor capability of PCI configuration space.
 	 */
-	mid_pwr_set_state(pwr, 0, 0xffffffff);
-	mid_pwr_set_state(pwr, 1, 0xffffffff);
-	mid_pwr_set_state(pwr, 2, 0xffffffff);
-	mid_pwr_set_state(pwr, 3, 0xffffffff);
+	mid_pwr_set_state(pwr, 0, states[0]);
+	mid_pwr_set_state(pwr, 1, states[1]);
+	mid_pwr_set_state(pwr, 2, states[2]);
+	mid_pwr_set_state(pwr, 3, states[3]);
 
 	/* Send command to SCU */
 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);

@@ -423,14 +423,41 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
 	return 0;
 }
 
-static const struct mid_pwr_device_info mid_info = {
-	.set_initial_state = mid_set_initial_state,
+static int pnw_set_initial_state(struct mid_pwr *pwr)
+{
+	/* On Penwell SRAM must stay powered on */
+	const u32 states[] = {
+		0xf00fffff,		/* PM_SSC(0) */
+		0xffffffff,		/* PM_SSC(1) */
+		0xffffffff,		/* PM_SSC(2) */
+		0xffffffff,		/* PM_SSC(3) */
+	};
+	return mid_set_initial_state(pwr, states);
+}
+
+static int tng_set_initial_state(struct mid_pwr *pwr)
+{
+	const u32 states[] = {
+		0xffffffff,		/* PM_SSC(0) */
+		0xffffffff,		/* PM_SSC(1) */
+		0xffffffff,		/* PM_SSC(2) */
+		0xffffffff,		/* PM_SSC(3) */
+	};
+	return mid_set_initial_state(pwr, states);
+}
+
+static const struct mid_pwr_device_info pnw_info = {
+	.set_initial_state = pnw_set_initial_state,
+};
+
+static const struct mid_pwr_device_info tng_info = {
+	.set_initial_state = tng_set_initial_state,
 };
 
 /* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
-	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
-	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
 	{}
 };

Signature · 1 line

2.9.3

tip-bot for Andy Shevchenko

merge bot

2016-09-08 13:20 UTC #2 lore raw

[tip:x86/platform] x86/platform/intel-mid: Keep SRAM powered on at boot

x86/platform/intel-mid: Keep SRAM powered on at boot

Commit-ID:  f43ea76cf310c3be95cb75ae1350cbe76a8f2380
Gitweb:     http://git.kernel.org/tip/f43ea76cf310c3be95cb75ae1350cbe76a8f2380
Author:     Andy Shevchenko <[email protected]>
AuthorDate: Thu, 8 Sep 2016 13:32:32 +0300
Committer:  Ingo Molnar <[email protected]>
CommitDate: Thu, 8 Sep 2016 14:07:54 +0200

x86/platform/intel-mid: Keep SRAM powered on at boot

On Penwell SRAM has to be powered on, otherwise it prevents booting.

Signed-off-by Andy Shevchenko <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Thomas Gleixner <[email protected]>

Fixes ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/platform/intel-mid/pwr.c | 45 +++++++++++++++++++++++++++++++--------
 1 file changed, 36 insertions(+), 9 deletions(-)

arch/x86/platform/intel-mid/pwr.c +36 -9

index 146ed54..5d3b45a 100644
@@ -380,7 +380,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 	return 0;
 }
 
-static int mid_set_initial_state(struct mid_pwr *pwr)
+static int mid_set_initial_state(struct mid_pwr *pwr, const u32 *states)
 {
 	unsigned int i, j;
 	int ret;

@@ -405,10 +405,10 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
 	 * NOTE: The actual device mapping is provided by a platform at run
 	 * time using vendor capability of PCI configuration space.
 	 */
-	mid_pwr_set_state(pwr, 0, 0xffffffff);
-	mid_pwr_set_state(pwr, 1, 0xffffffff);
-	mid_pwr_set_state(pwr, 2, 0xffffffff);
-	mid_pwr_set_state(pwr, 3, 0xffffffff);
+	mid_pwr_set_state(pwr, 0, states[0]);
+	mid_pwr_set_state(pwr, 1, states[1]);
+	mid_pwr_set_state(pwr, 2, states[2]);
+	mid_pwr_set_state(pwr, 3, states[3]);
 
 	/* Send command to SCU */
 	ret = mid_pwr_wait_for_cmd(pwr, CMD_SET_CFG);

@@ -423,14 +423,41 @@ static int mid_set_initial_state(struct mid_pwr *pwr)
 	return 0;
 }
 
-static const struct mid_pwr_device_info mid_info = {
-	.set_initial_state = mid_set_initial_state,
+static int pnw_set_initial_state(struct mid_pwr *pwr)
+{
+	/* On Penwell SRAM must stay powered on */
+	const u32 states[] = {
+		0xf00fffff,		/* PM_SSC(0) */
+		0xffffffff,		/* PM_SSC(1) */
+		0xffffffff,		/* PM_SSC(2) */
+		0xffffffff,		/* PM_SSC(3) */
+	};
+	return mid_set_initial_state(pwr, states);
+}
+
+static int tng_set_initial_state(struct mid_pwr *pwr)
+{
+	const u32 states[] = {
+		0xffffffff,		/* PM_SSC(0) */
+		0xffffffff,		/* PM_SSC(1) */
+		0xffffffff,		/* PM_SSC(2) */
+		0xffffffff,		/* PM_SSC(3) */
+	};
+	return mid_set_initial_state(pwr, states);
+}
+
+static const struct mid_pwr_device_info pnw_info = {
+	.set_initial_state = pnw_set_initial_state,
+};
+
+static const struct mid_pwr_device_info tng_info = {
+	.set_initial_state = tng_set_initial_state,
 };
 
 /* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
-	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
-	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&pnw_info },
+	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info },
 	{}
 };

tip-bot for Andy Shevchenko

merge bot

2016-09-08 13:20 UTC #3 lore raw

In reply to Andy Shevchenko

x86/platform/intel-mid: Add Intel Penwell to ID table

Commit-ID:  8e522e1d321b12829960c9b26668c92f14c68d7f
Gitweb:     http://git.kernel.org/tip/8e522e1d321b12829960c9b26668c92f14c68d7f
Author:     Andy Shevchenko <[email protected]>
AuthorDate: Thu, 8 Sep 2016 13:32:31 +0300
Committer:  Ingo Molnar <[email protected]>
CommitDate: Thu, 8 Sep 2016 14:07:53 +0200

x86/platform/intel-mid: Add Intel Penwell to ID table

Commit:

ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

... enabled the PWRMU driver on platforms based on Intel Penwell, but unfortunately this is not enough.

Add Intel Penwell ID to pci-mid.c driver as well. To avoid confusion in the future add a comment to both drivers.

Signed-off-by Andy Shevchenko <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Thomas Gleixner <[email protected]>

Fixes ca22312dc840 ("x86/platform/intel-mid: Extend PWRMU to support Penwell")

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/platform/intel-mid/pwr.c | 1 +
 drivers/pci/pci-mid.c             | 5 +++++
 2 files changed, 6 insertions(+)

arch/x86/platform/intel-mid/pwr.c +1 -0

index 2dfe998..146ed54 100644
@@ -427,6 +427,7 @@ static const struct mid_pwr_device_info mid_info = {
 	.set_initial_state = mid_set_initial_state,
 };
 
+/* This table should be in sync with the one in drivers/pci/pci-mid.c */
 static const struct pci_device_id mid_pwr_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info },
 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info },

drivers/pci/pci-mid.c +5 -0

index b7ea64f..55f453d 100644
@@ -60,7 +60,12 @@ static struct pci_platform_pm_ops mid_pci_platform_pm = {
 
 #define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 
+/*
+ * This table should be in sync with the one in
+ * arch/x86/platform/intel-mid/pwr.c.
+ */
 static const struct x86_cpu_id lpss_cpu_ids[] = {
+	ICPU(INTEL_FAM6_ATOM_PENWELL),
 	ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
 	{}
 };