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drm/fsl-dcu: initialization fixes

PATCH Superseded Stefan Agner 1 participant 8 messages Oct 5, 2016

Subsystems (3)
DRM drivers DRM misc DRM drivers for Freescale dcu

v2 of 3 Superseded Latest is v3 →

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Stefan Agner

author maintainer
#0 lore raw

v2 cover drm/fsl-dcu: initialization fixes

Hi All,

This is an assortment of fixes which solve issues seen using an external RGB converter and makes sure that pixel clock is only on when really required.

Meng, would be good if you can test it on a LS1021a.

--
Stefan

Changes since v1:
- add patch to no not transfer registers in mode_set_nofb
- add patch which only init fbdev if required
- remove disable unprepare pixel clock on module remove (already disabled in CRTC disable callback).
- remove unused label

Stefan Agner (5):
drm/fsl-dcu: enable TCON bypass mode by default drm/fsl-dcu: do not transfer registers on plane init drm/fsl-dcu: do not transfer registers in mode_set_nofb drm/fsl-dcu: enable pixel clock when enabling CRTC drm/fsl-dcu: only init fbdev if required

 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c  |  4 +--
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c   | 25 +++----------------
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c |  5 ----
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c   | 38 +++--------------------------
 4 files changed, 10 insertions(+), 62 deletions(-)
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#1 lore raw

PATCH v2 1/5 drm/fsl-dcu: enable TCON bypass mode by default

Do not use encoder disable/enable callbacks to control bypass mode as this seems to mess with the signals not liked by displays. This also makes more sense since the encoder is already defined to be parallel RGB/LVDS at creation time.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c |  1 +
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c | 38 ++++---------------------------
 2 files changed, 5 insertions(+), 34 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +1 -0
index 0884c45..68db834 100644
@@ -273,6 +273,7 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
 		goto disable_dcu_clk;
 	}
 
+	fsl_tcon_bypass_enable(fsl_dev->tcon);
 	fsl_dcu_drm_init_planes(fsl_dev->drm);
 	drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_rgb.c +4 -34
index 26edcc8..ec88719 100644
@@ -20,38 +20,6 @@
 #include "fsl_dcu_drm_drv.h"
 #include "fsl_tcon.h"
 
-static int
-fsl_dcu_drm_encoder_atomic_check(struct drm_encoder *encoder,
-				 struct drm_crtc_state *crtc_state,
-				 struct drm_connector_state *conn_state)
-{
-	return 0;
-}
-
-static void fsl_dcu_drm_encoder_disable(struct drm_encoder *encoder)
-{
-	struct drm_device *dev = encoder->dev;
-	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
-
-	if (fsl_dev->tcon)
-		fsl_tcon_bypass_disable(fsl_dev->tcon);
-}
-
-static void fsl_dcu_drm_encoder_enable(struct drm_encoder *encoder)
-{
-	struct drm_device *dev = encoder->dev;
-	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
-
-	if (fsl_dev->tcon)
-		fsl_tcon_bypass_enable(fsl_dev->tcon);
-}
-
-static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
-	.atomic_check = fsl_dcu_drm_encoder_atomic_check,
-	.disable = fsl_dcu_drm_encoder_disable,
-	.enable = fsl_dcu_drm_encoder_enable,
-};
-
 static void fsl_dcu_drm_encoder_destroy(struct drm_encoder *encoder)
 {
 	drm_encoder_cleanup(encoder);

@@ -68,13 +36,15 @@ int fsl_dcu_drm_encoder_create(struct fsl_dcu_drm_device *fsl_dev,
 	int ret;
 
 	encoder->possible_crtcs = 1;
+
+	/* Use bypass mode for parallel RGB/LVDS encoder */
+	fsl_tcon_bypass_enable(fsl_dev->tcon);
+
 	ret = drm_encoder_init(fsl_dev->drm, encoder, &encoder_funcs,
 			       DRM_MODE_ENCODER_LVDS, NULL);
 	if (ret < 0)
 		return ret;
 
-	drm_encoder_helper_add(encoder, &encoder_helper_funcs);
-
 	return 0;
 }
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#2 lore raw

PATCH v2 2/5 drm/fsl-dcu: do not explicitly transfer registers on plane init

In reply to Stefan Agner

There is no need to explicitly initiate a register transfer and turn off the DCU after initializing the plane registers. In fact, this is harmful and leads to unnecessary flickers if the DCU has been left on by the bootloader.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 5 -----
 1 file changed, 5 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c +0 -5
index a7e5486..9e6f7d8 100644
@@ -211,11 +211,6 @@ void fsl_dcu_drm_init_planes(struct drm_device *dev)
 		for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
 			regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
 	}
-	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
-			   DCU_MODE_DCU_MODE_MASK,
-			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 }
 
 struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
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author maintainer
#3 lore raw

PATCH v2 2/5 drm/fsl-dcu: do not transfer registers on plane init

In reply to Stefan Agner

There is no need to explicitly initiate a register transfer and turn off the DCU after initializing the plane registers. In fact, this is harmful and leads to unnecessary flickers if the DCU has been left on by the bootloader.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c | 5 -----
 1 file changed, 5 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c +0 -5
index a7e5486..9e6f7d8 100644
@@ -211,11 +211,6 @@ void fsl_dcu_drm_init_planes(struct drm_device *dev)
 		for (j = 1; j <= fsl_dev->soc->layer_regs; j++)
 			regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
 	}
-	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
-			   DCU_MODE_DCU_MODE_MASK,
-			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 }
 
 struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
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#4 lore raw

PATCH v2 3/5 drm/fsl-dcu: do not transfer register in mode_set_nofb

In reply to Stefan Agner

Do not schedule a transfer of mode settings early. Modes should get applied on on CRTC enable where we also enable the pixel clock.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 --
 1 file changed, 2 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +0 -2
index 3371635..5ad1d68 100644
@@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return;
 }
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#5 lore raw

PATCH v2 3/5 drm/fsl-dcu: do not transfer registers in mode_set_nofb

In reply to Stefan Agner

Do not schedule a transfer of mode settings early. Modes should get applied on on CRTC enable where we also enable the pixel clock.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 2 --
 1 file changed, 2 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +0 -2
index 3371635..5ad1d68 100644
@@ -116,8 +116,6 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
 		     DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 		     DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
-	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
-		     DCU_UPDATE_MODE_READREG);
 	return;
 }
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#6 lore raw

PATCH v2 4/5 drm/fsl-dcu: enable pixel clock when enabling CRTC

In reply to Stefan Agner

The pixel clock should not be on if the CRTC is not in use, hence move clock enable/disable calls into CRTC callbacks.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c |  2 ++
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c  | 21 +--------------------
 2 files changed, 3 insertions(+), 20 deletions(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c +2 -0
index 5ad1d68..b2d5e18 100644
@@ -51,6 +51,7 @@ static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
 			   DCU_MODE_DCU_MODE(DCU_MODE_OFF));
 	regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
 		     DCU_UPDATE_MODE_READREG);
+	clk_disable_unprepare(fsl_dev->pix_clk);
 }
 
 static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)

@@ -58,6 +59,7 @@ static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
 	struct drm_device *dev = crtc->dev;
 	struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
 
+	clk_prepare_enable(fsl_dev->pix_clk);
 	regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
 			   DCU_MODE_DCU_MODE_MASK,
 			   DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +1 -20
index 68db834..07969f5 100644
@@ -267,12 +267,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
 		return ret;
 	}
 
-	ret = clk_prepare_enable(fsl_dev->pix_clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to enable pix clk\n");
-		goto disable_dcu_clk;
-	}
-
 	fsl_tcon_bypass_enable(fsl_dev->tcon);
 	fsl_dcu_drm_init_planes(fsl_dev->drm);
 	drm_atomic_helper_resume(fsl_dev->drm, fsl_dev->state);

@@ -285,10 +279,6 @@ static int fsl_dcu_drm_pm_resume(struct device *dev)
 	enable_irq(fsl_dev->irq);
 
 	return 0;
-
-disable_dcu_clk:
-	clk_disable_unprepare(fsl_dev->clk);
-	return ret;
 }
 #endif
 

@@ -402,18 +392,12 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 		goto disable_clk;
 	}
 
-	ret = clk_prepare_enable(fsl_dev->pix_clk);
-	if (ret < 0) {
-		dev_err(dev, "failed to enable pix clk\n");
-		goto unregister_pix_clk;
-	}
-
 	fsl_dev->tcon = fsl_tcon_init(dev);
 
 	drm = drm_dev_alloc(driver, dev);
 	if (IS_ERR(drm)) {
 		ret = PTR_ERR(drm);
-		goto disable_pix_clk;
+		goto unregister_pix_clk;
 	}
 
 	fsl_dev->dev = dev;

@@ -434,8 +418,6 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
 	drm_dev_unref(drm);
-disable_pix_clk:
-	clk_disable_unprepare(fsl_dev->pix_clk);
 unregister_pix_clk:
 	clk_unregister(fsl_dev->pix_clk);
 disable_clk:

@@ -448,7 +430,6 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
 	struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
 	clk_disable_unprepare(fsl_dev->clk);
-	clk_disable_unprepare(fsl_dev->pix_clk);
 	clk_unregister(fsl_dev->pix_clk);
 	drm_put_dev(fsl_dev->drm);
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#7 lore raw

PATCH v2 5/5 drm/fsl-dcu: only init fbdev if required

In reply to Stefan Agner

There is no need to request a CMA backed framebuffer if fbdev emulation is not enabled.

Signed-off-by Stefan Agner <[email protected]>
---
 drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c +2 -1
index 07969f5..86dd4e3 100644
@@ -87,7 +87,8 @@ static int fsl_dcu_load(struct drm_device *dev, unsigned long flags)
 		goto done;
 	dev->irq_enabled = true;
 
-	fsl_dcu_fbdev_init(dev);
+	if (IS_ENABLED(CONFIG_DRM_FBDEV_EMULATION))
+		fsl_dcu_fbdev_init(dev);
 
 	return 0;
 done:
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