ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

PATCH RESEND Superseded Vignesh R 4 participants 7 messages Oct 31, 2016 – Nov 5, 2016

Subsystems (2)

Arm (32-bit) SPI

lore

Share & tools

lore

Vignesh R

author

2016-10-31 04:10 UTC #0 lore raw

PATCH RESEND v2 1/2 ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz.

Signed-off-by Vignesh R <[email protected]>

Reviewed-by Jagan Teki <[email protected]>

---

v2: No changes

 arch/arm/dts/dra7-evm.dts          | 2 +-
 arch/arm/dts/dra72-evm-common.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

arch/arm/dts/dra7-evm.dts +1 -1

index fe755c05841d..be36d456206d 100644
@@ -505,7 +505,7 @@
 	spi-max-frequency = <76800000>;
 	m25p80 at 0 {
 		compatible = "s25fl256s1","spi-flash";
-		spi-max-frequency = <64000000>;
+		spi-max-frequency = <76800000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;

arch/arm/dts/dra72-evm-common.dtsi +1 -1

index b0993e5bf7e0..1e1ca725577f 100644
@@ -441,7 +441,7 @@
 	spi-max-frequency = <76800000>;
 	m25p80 at 0 {
 		compatible = "s25fl256s1", "spi-flash";
-		spi-max-frequency = <64000000>;
+		spi-max-frequency = <76800000>;
 		reg = <0>;
 		spi-tx-bus-width = <1>;
 		spi-rx-bus-width = <4>;

Signature · 1 line

2.10.2

Vignesh R

author

2016-10-31 04:10 UTC #1 lore raw

PATCH RESEND v2 2/2 spi: ti_qspi: Fix baudrate divider calculation

Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed().

Signed-off-by Vignesh R <[email protected]>

---

v2: cleanup ti_spi_set_speed() a bit.

 drivers/spi/ti_qspi.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

drivers/spi/ti_qspi.c +7 -8

index 52520dff6325..b5de70bf40e3 100644
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
 	if (!hz)
 		clk_div = 0;
 	else
-		clk_div = (priv->fclk / hz) - 1;
-
-	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+		clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 
 	/* disable SCLK */
 	writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
 	       &priv->base->clk_ctrl);
 
-	/* assign clk_div values */
-	if (clk_div < 0)
-		clk_div = 0;
-	else if (clk_div > QSPI_CLK_DIV_MAX)
+	/* truncate clk_div value to QSPI_CLK_DIV_MAX */
+	if (clk_div > QSPI_CLK_DIV_MAX)
 		clk_div = QSPI_CLK_DIV_MAX;
 
-	/* enable SCLK */
+	debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+
+	/* enable SCLK and program the clk divider */
 	writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }

Signature · 1 line

2.10.2

Jagan Teki

2016-10-31 09:24 UTC #2 lore raw

PATCH RESEND v2 2/2 spi: ti_qspi: Fix baudrate divider calculation

Quoted 26 lines · Vignesh R

Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed().
Signed-off-by Vignesh R <[email protected]>
---
v2: cleanup ti_spi_set_speed() a bit.
 drivers/spi/ti_qspi.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)
drivers/spi/ti_qspi.c +1 -0
index 52520dff6325..b5de70bf40e3 100644
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)

drivers/spi/ti_qspi.c static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) · line 126

Quoted 10 lines

drivers/spi/ti_qspi.c +1 -3

                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
-
-       debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);

Move this before enable SCLK.

Quoted 5 lines

drivers/spi/ti_qspi.c +0 -4

-       /* assign clk_div values */
-       if (clk_div < 0)
-               clk_div = 0;
-       else if (clk_div > QSPI_CLK_DIV_MAX)

drivers/spi/ti_qspi.c static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) · line 136

Quoted 10 lines

drivers/spi/ti_qspi.c +5 -1

+       /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+       if (clk_div > QSPI_CLK_DIV_MAX)
                clk_div = QSPI_CLK_DIV_MAX;
 
-       /* enable SCLK */
+       debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+
+       /* enable SCLK and program the clk divider */
        writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
 }

thanks!

Signature · 4 lines

Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

Jagan Teki

2016-11-04 11:01 UTC #3 lore raw

PATCH RESEND v2 2/2 spi: ti_qspi: Fix baudrate divider calculation

Quoted 34 lines · Jagan Teki

Quoted 33 lines · Vignesh R

Signed-off-by Vignesh R <[email protected]>

---

v2: cleanup ti_spi_set_speed() a bit.

 drivers/spi/ti_qspi.c | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

drivers/spi/ti_qspi.c +2 -3

index 52520dff6325..b5de70bf40e3 100644
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)
                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
-
-       debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

Quoted 5 lines

drivers/spi/ti_qspi.c static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) · line 126
Quoted 3 lines
drivers/spi/ti_qspi.c +0 -0
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);
Move this before enable SCLK.

Do send the updated v3 or discusses further, I need to send the release PR?

thanks!

Signature · 4 lines

Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

R

2016-11-05 10:36 UTC #4 lore raw

PATCH RESEND v2 2/2 spi: ti_qspi: Fix baudrate divider calculation

[...]

Quoted 21 lines · Jagan Teki

Quoted 21 lines

drivers/spi/ti_qspi.c +2 -3

index 52520dff6325..b5de70bf40e3 100644
@@ -16,6 +16,7 @@
 #include <asm/omap_gpio.h>
 #include <asm/omap_common.h>
 #include <asm/ti-common/ti-edma3.h>
+#include <linux/kernel.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
        if (!hz)
                clk_div = 0;
        else
-               clk_div = (priv->fclk / hz) - 1;
-
-       debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+               clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;

Quoted 5 lines

Quoted 5 lines
Quoted 5 lines
Quoted 3 lines
drivers/spi/ti_qspi.c static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) · line 126
Quoted 3 lines
drivers/spi/ti_qspi.c +0 -0
        /* disable SCLK */
        writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN,
               &priv->base->clk_ctrl);
Move this before enable SCLK.

Ok...

Quoted 1 line

Do send the updated v3 or discusses further, I need to send the release PR?

Sorry for the delay.. Posted v3 with above change.

Signature · 2 lines

Regards
Vignesh

Tom Rini

2016-10-31 11:54 UTC #5 lore raw

PATCH RESEND v2 1/2 ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

In reply to Vignesh R

Quoted 6 lines · Vignesh R

Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz.
Signed-off-by Vignesh R <[email protected]>
Reviewed-by Jagan Teki <[email protected]>

And this is also done in the kernel right? Thanks!

Signature · 8 lines

Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 819 bytes
Desc: Digital signature
URL: <http://lists.denx.de/pipermail/u-boot/attachments/20161031/112aa489/attachment.sig>

R

2016-10-31 15:40 UTC #6 lore raw

PATCH RESEND v2 1/2 ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

Quoted 11 lines · Tom Rini

Quoted 6 lines · Vignesh R
Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz.
Signed-off-by Vignesh R <[email protected]>
Reviewed-by Jagan Teki <[email protected]>
And this is also done in the kernel right? Thanks!

Yes, the kernel patch is merged.

Signature · 2 lines

Regards
Vignesh