cpufreq: brcmstb-cpufreq: CPUfreq driver for older Broadcom STB SoCs
Subsystems (5)
v4 cover cpufreq: brcmstb-cpufreq: CPUfreq driver for older Broadcom STB SoCs
From: Markus Mayer <[email protected]>
This CPUfreq driver provides basic frequency scaling for older Broadcom STB SoCs that do not use AVS firmware with DVFS support. There is no support for voltage scaling.
v3 of this patch can be found here: https://lkml.org/lkml/2016/11/22/747
Changes since v3:
- added binding document
- got rid of calls to __clk_lookup(), using devm_clk_get() instead
- re-worked clock lookup code a bit, along with switching to devm_clk_get()
- get_frequencies() became a void function, removing the need for some error checking
- fixed CONFIG_ARM_BRCM_AVS_CPUFREQ typo
- fixed MODULE_DEVICE_TABLE declaration
Markus Mayer (2):
dt-bindings: brcm: clocks: add binding for brcmstb-cpu-clk-div
cpufreq: brcmstb-cpufreq: CPUfreq driver for older Broadcom STB SoCs
.../bindings/clock/brcm,brcmstb-cpu-clk-div.txt | 83 +++++ MAINTAINERS | 1 + drivers/cpufreq/Kconfig.arm | 12 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/brcmstb-cpufreq.c | 377 +++++++++++++++++++++ 5 files changed, 474 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt create mode 100644 drivers/cpufreq/brcmstb-cpufreq.c
Signature · 1 line
2.7.4
PATCH v4 1/2 dt-bindings: brcm: clocks: add binding for brcmstb-cpu-clk-div
From: Markus Mayer <[email protected]>
Add binding document for brcm,brcmstb-cpu-clk-div.
--- .../bindings/clock/brcm,brcmstb-cpu-clk-div.txt | 83 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +83 -0
@@ -0,0 +1,83 @@ +The CPU divider node serves as the sole clock for the CPU complex. It supports +power-of-2 clock division, with a divider of "1" as the default highest-speed +setting. + +Required properties: +- compatible: shall be "brcm,brcmstb-cpu-clk-div" +- reg: address and width of the divider configuration register +- #clock-cells: shall be set to 0 +- clocks: phandle of clock provider which provides the source clock + (this would typically be a "fixed-clock" type PLL) +- div-table: list of (raw_value,divider) ordered pairs that correspond to the + allowed clock divider settings +- div-shift-width: least-significant bit position and width of divider value + +Optional properties: +- clocks: additional clocks can be specified if needed +- clock-names: clocks can be named, so they can be looked up + +Example: + sw_scb: sw_scb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + }; + + fixed0: fixed0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <54000000>; + }; + + cpu_pdiv: cpu_pdiv at f04e0008 { + compatible = "divider-clock"; + #clock-cells = <0>; + reg = <0xf04e0008 0x4>; + bit-shift = <10>; + bit-mask = <0xf>; + index-starts-at-one; + clocks = <&fixed0>; + clock-names = "fixed0"; + }; + + cpu_ndiv_int: cpu_ndiv_int { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <167>; + clocks = <&cpu_pdiv>; + clock-names = "cpu_pdiv"; + }; + + cpu_mdiv_ch0: cpu_mdiv_ch0 at f04e0000 { + compatible = "divider-clock"; + #clock-cells = <0>; + reg = <0xf04e0000 0x4>; + bit-shift = <1>; + bit-mask = <0xff>; + index-starts-at-one; + clocks = <&cpu_ndiv_int>; + clock-names = "cpu_ndiv_int"; + }; + + cpupll: cpupll at 0 { + #clock-cells = <0>; + clock-frequency = <1503000000>; + compatible = "fixed-clock"; + }; + + cpuclkdiv: cpu-clk-div at 0 { + #clock-cells = <0>; + clock-names = "cpupll", + "cpu_mdiv_ch0", + "cpu_ndiv_int", + "sw_scb"; + clocks = <&cpupll, + &cpu_mdiv_ch0, + &cpu_ndiv_int, + &sw_scb>; + compatible = "brcm,brcmstb-cpu-clk-div"; + reg = <0xf03e257c 0x4>; + div-table = <0x00 1>; + div-shift-width = <0 5>; + };
MAINTAINERS +1 -0
@@ -2786,6 +2786,7 @@ M: bcm-kernel-feedback-list at broadcom.com L: linux-pm at vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/cpufreq/brcm,stb-avs-cpu-freq.txt +F: Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt F: drivers/cpufreq/brcmstb* BROADCOM SPECIFIC AMBA DRIVER (BCMA)
Signature · 1 line
2.7.4
Re: [PATCH v4 1/2] dt-bindings: brcm: clocks: add binding for brcmstb-cpu-clk-div
Quoted 32 lines · Markus Mayer
From: Markus Mayer <[email protected]>
Add binding document for brcm,brcmstb-cpu-clk-div.
Signed-off-by Markus Mayer <[email protected]>--- .../bindings/clock/brcm,brcmstb-cpu-clk-div.txt | 83 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txtDocumentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +15
-0@@ -0,0 +1,83 @@ +The CPU divider node serves as the sole clock for the CPU complex. It supports +power-of-2 clock division, with a divider of "1" as the default highest-speed +setting. + +Required properties: +- compatible: shall be "brcm,brcmstb-cpu-clk-div" +- reg: address and width of the divider configuration register +- #clock-cells: shall be set to 0 +- clocks: phandle of clock provider which provides the source clock + (this would typically be a "fixed-clock" type PLL) +- div-table: list of (raw_value,divider) ordered pairs that correspond to the + allowed clock divider settings +- div-shift-width: least-significant bit position and width of divider value + +Optional properties:
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 25
Quoted 10 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +10
-0+- clocks: additional clocks can be specified if needed +- clock-names: clocks can be named, so they can be looked up + +Example: + sw_scb: sw_scb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <432000000>; + }; +
Is this a PLL?
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 30
Quoted 5 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +5
-0+ fixed0: fixed0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <54000000>; + };
And perhaps some sort of oscillator?
Quoted 4 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +4
-0+ + cpu_pdiv: cpu_pdiv at f04e0008 { + compatible = "divider-clock"; + #clock-cells = <0>;
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 44
Quoted 10 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +10
-0+ reg = <0xf04e0008 0x4>; + bit-shift = <10>; + bit-mask = <0xf>; + index-starts-at-one; + clocks = <&fixed0>; + clock-names = "fixed0"; + }; + + cpu_ndiv_int: cpu_ndiv_int { + compatible = "fixed-factor-clock";
Ok..
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 53
Quoted 9 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +9
-0+ #clock-cells = <0>; + clock-div = <1>; + clock-mult = <167>; + clocks = <&cpu_pdiv>; + clock-names = "cpu_pdiv"; + }; + + cpu_mdiv_ch0: cpu_mdiv_ch0 at f04e0000 { + compatible = "divider-clock";
Is there a binding for this?
Quoted 6 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +6
-0+ #clock-cells = <0>; + reg = <0xf04e0000 0x4>; + bit-shift = <1>; + bit-mask = <0xff>; + index-starts-at-one; + clocks = <&cpu_ndiv_int>;
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 69
Quoted 10 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +10
-0+ clock-names = "cpu_ndiv_int"; + }; + + cpupll: cpupll at 0 { + #clock-cells = <0>; + clock-frequency = <1503000000>; + compatible = "fixed-clock"; + }; + + cpuclkdiv: cpu-clk-div at 0 {
Wrong unit address. Should be f03e257c?
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt line 82
Quoted 13 lines
Documentation/devicetree/bindings/clock/brcm,brcmstb-cpu-clk-div.txt new file +13
-0+ #clock-cells = <0>; + clock-names = "cpupll", + "cpu_mdiv_ch0", + "cpu_ndiv_int", + "sw_scb"; + clocks = <&cpupll, + &cpu_mdiv_ch0, + &cpu_ndiv_int, + &sw_scb>; + compatible = "brcm,brcmstb-cpu-clk-div"; + reg = <0xf03e257c 0x4>; + div-table = <0x00 1>; + div-shift-width = <0 5>;
This entire DT design seems wrong. We don't put these sorts of register level details into DT. There should be a driver that knows the type of device that is present and how to drive that hardware.
Quoted 1 line
From what I can tell there's something like a mux controller at
0xf04e0000 and then there's some sort of divider controller at 0xf03e0000. Perhaps those are two different devices that need independent drivers? My wild guess is the PLL control is in those register regions too, but we're not exposing control of them. That's ok, but don't put the PLL into the DT as a fixed clock. Just register it from the driver.
Signature · 2 lines
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v4 2/2 cpufreq: brcmstb-cpufreq: CPUfreq driver for older Broadcom STB SoCs
In reply to Markus MayerFrom: Markus Mayer <[email protected]>
This CPUfreq driver provides basic frequency scaling for older Broadcom STB SoCs that do not use AVS firmware with DVFS support. There is no support for voltage scaling.
--- drivers/cpufreq/Kconfig.arm | 12 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/brcmstb-cpufreq.c | 377 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/cpufreq/brcmstb-cpufreq.c
drivers/cpufreq/Kconfig.arm +12 -0
@@ -33,6 +33,18 @@ config ARM_BRCMSTB_AVS_CPUFREQ_DEBUG If in doubt, say N. +config ARM_BRCMSTB_CPUFREQ + tristate "Broadcom STB CPUfreq driver" + depends on ARCH_BRCMSTB || COMPILE_TEST + default y + help + Some Broadcom SoCs offer multiple operating frequencies that CPUfreq + can take advantage of to improve energy efficiency. + + Say Y, if you have a supported Broadcom SoC. If your Broadcom SoC + has AVS firmware with support for frequency and voltage scaling, + say N here and enable ARM_BRCMSTB_AVS_CPUFREQ instead. + config ARM_DT_BL_CPUFREQ tristate "Generic probing via DT for ARM big LITTLE CPUfreq driver" depends on ARM_BIG_LITTLE_CPUFREQ && OF
drivers/cpufreq/Makefile +1 -0
@@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_BIG_LITTLE_CPUFREQ) += arm_big_little.o obj-$(CONFIG_ARM_DT_BL_CPUFREQ) += arm_big_little_dt.o obj-$(CONFIG_ARM_BRCMSTB_AVS_CPUFREQ) += brcmstb-avs-cpufreq.o +obj-$(CONFIG_ARM_BRCMSTB_CPUFREQ) += brcmstb-cpufreq.o obj-$(CONFIG_ARCH_DAVINCI) += davinci-cpufreq.o obj-$(CONFIG_UX500_SOC_DB8500) += dbx500-cpufreq.o obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
drivers/cpufreq/brcmstb-cpufreq.c new file +377 -0
377 lines not on this page · raw message
Signature · 1 line
2.7.4
Viresh Kumar
maintainerQuoted 6 lines · Markus Mayer
From: Markus Mayer <[email protected]>
This CPUfreq driver provides basic frequency scaling for older Broadcom STB SoCs that do not use AVS firmware with DVFS support. There is no support for voltage scaling.
Quoted 7 lines
Signed-off-by Markus Mayer <[email protected]>--- drivers/cpufreq/Kconfig.arm | 12 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/brcmstb-cpufreq.c | 377 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/cpufreq/brcmstb-cpufreq.c
I am fine with this patch as I have already Acked V3 of it. But please fix the bindings improvement suggested by Stephen first.
Signature · 1 line
viresh
Quoted 15 lines · Viresh Kumar
Quoted 6 lines · Markus Mayer
From: Markus Mayer <[email protected]>
This CPUfreq driver provides basic frequency scaling for older Broadcom STB SoCs that do not use AVS firmware with DVFS support. There is no support for voltage scaling.
Quoted 7 lines
Signed-off-by Markus Mayer <[email protected]>--- drivers/cpufreq/Kconfig.arm | 12 ++ drivers/cpufreq/Makefile | 1 + drivers/cpufreq/brcmstb-cpufreq.c | 377 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 390 insertions(+) create mode 100644 drivers/cpufreq/brcmstb-cpufreq.c
Quoted 2 lines
I am fine with this patch as I have already Acked V3 of it. But please fix the bindings improvement suggested by Stephen first.
Yes, that is on my list of things to do. I will send an update hopefully next week.
Thanks,
-Markus