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MIPS: loongson1: Add PWM support for Loongson1 board

PATCH Superseded Yang Ling 1 participant 1 message Feb 13, 2017

Subsystems (2)
MIPS MIPS/LOONGSON1 architecture

v1 of 2 Superseded Latest is v2 →

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Yang Ling

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PATCH 2/2 MIPS: loongson1: Add PWM support for Loongson1 board

The patch adds PWM support for Loongson1 board.

Signed-off-by Yang Ling <[email protected]>
---
 arch/mips/configs/loongson1b_defconfig           |  2 ++
 arch/mips/configs/loongson1c_defconfig           |  2 ++
 arch/mips/include/asm/mach-loongson32/platform.h |  1 +
 arch/mips/include/asm/mach-loongson32/regs-pwm.h |  8 ++++----
 arch/mips/loongson32/common/platform.c           | 16 ++++++++++++++++
 arch/mips/loongson32/ls1b/board.c                |  1 +
 arch/mips/loongson32/ls1c/board.c                |  1 +
 7 files changed, 27 insertions(+), 4 deletions(-)
arch/mips/configs/loongson1b_defconfig +2 -0
index 914c867..0e6f7f6 100644
@@ -97,6 +97,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_LOONGSON1=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_LOONGSON1=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
arch/mips/configs/loongson1c_defconfig +2 -0
index 68e42ef..1f241af 100644
@@ -98,6 +98,8 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_LOONGSON1=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_LOONGSON1=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
arch/mips/include/asm/mach-loongson32/platform.h +1 -0
index 8f8fa43..f532d93 100644
@@ -24,6 +24,7 @@
 extern struct platform_device ls1x_gpio0_pdev;
 extern struct platform_device ls1x_gpio1_pdev;
 extern struct platform_device ls1x_nand_pdev;
+extern struct platform_device ls1x_pwm_pdev;
 extern struct platform_device ls1x_rtc_pdev;
 extern struct platform_device ls1x_wdt_pdev;
arch/mips/include/asm/mach-loongson32/regs-pwm.h +4 -4
index 4119600..210cec8 100644
@@ -13,10 +13,10 @@
 #define __ASM_MACH_LOONGSON32_REGS_PWM_H
 
 /* Loongson 1 PWM Timer Register Definitions */
-#define PWM_CNT			0x0
-#define PWM_HRC			0x4
-#define PWM_LRC			0x8
-#define PWM_CTRL		0xc
+#define PWM_CNT(n)		((n << 4) + 0x0)
+#define PWM_HRC(n)		((n << 4) + 0x4)
+#define PWM_LRC(n)		((n << 4) + 0x8)
+#define PWM_CTRL(n)		((n << 4) + 0xc)
 
 /* PWM Control Register Bits */
 #define CNT_RST			BIT(7)
arch/mips/loongson32/common/platform.c +16 -0
index a3dabe9..011ae6c 100644
@@ -372,3 +372,19 @@ struct platform_device ls1x_wdt_pdev = {
 	.num_resources	= ARRAY_SIZE(ls1x_wdt_resources),
 	.resource	= ls1x_wdt_resources,
 };
+
+/* PWM */
+static struct resource ls1x_pwm_resources[] = {
+	{
+		.start	= LS1X_PWM0_BASE,
+		.end	= LS1X_PWM0_BASE + SZ_64 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+struct platform_device ls1x_pwm_pdev = {
+	.name		= "ls1x-pwm",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ls1x_pwm_resources),
+	.resource	= ls1x_pwm_resources,
+};
arch/mips/loongson32/ls1b/board.c +1 -0
index 01aceaa..8bf0754 100644
@@ -71,6 +71,7 @@ struct plat_ls1x_nand ls1x_nand_pdata = {
 	&ls1x_gpio0_pdev,
 	&ls1x_gpio1_pdev,
 	&ls1x_nand_pdev,
+	&ls1x_pwm_pdev,
 	&ls1x_rtc_pdev,
 	&ls1x_wdt_pdev,
 };
arch/mips/loongson32/ls1c/board.c +1 -0
index eb2d913..2d6e3bb 100644
@@ -12,6 +12,7 @@
 static struct platform_device *ls1c_platform_devices[] __initdata = {
 	&ls1x_uart_pdev,
 	&ls1x_eth0_pdev,
+	&ls1x_pwm_pdev,
 	&ls1x_rtc_pdev,
 	&ls1x_wdt_pdev,
 };
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1.9.1