Small cleanups for UVD42 and VCE2
Subsystems (2)
Rounding off the SI cleanups for now are small NFC edits to the uvd42 and vce2 drivers.
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PATCH 1/4 drm/amd/amdgpu: Use 32/64-bit types in uvd42
Swap uNN for uintNN_t.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +6 -6
@@ -254,10 +254,10 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)struct amdgpu_ring *ring = &adev->uvd.ring;uint32_t rb_bufsz;int i, j, r; -u32 tmp; +uint32_t tmp;/* disable byte swapping */ -u32 lmi_swap_cntl =0 ; -u32 mp_swap_cntl =0 ; +uint32_t lmi_swap_cntl =0 ; +uint32_t mp_swap_cntl =0 ;/* set uvd busy */ WREG32_P (mmUVD_STATUS,1 <<2 , ~(1 <<2 ));
@@ -441,7 +441,7 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev)* * Write a fence and a trap command to the ring. */ -static void uvd_v4_2_ring_emit_fence (struct amdgpu_ring *ring,u64 addr,u64 seq, +static void uvd_v4_2_ring_emit_fence (struct amdgpu_ring *ring,uint64_t addr,uint64_t seq,unsigned flags) {WARN_ON (flags &AMDGPU_FENCE_FLAG_64BIT );
@@ -594,7 +594,7 @@ static void uvd_v4_2_mc_resume(struct amdgpu_device *adev)static void uvd_v4_2_enable_mgcg (struct amdgpu_device *adev,bool enable) { -u32 orig, data; +uint32_t orig, data;if (enable && (adev->cg_flags &AMD_CG_SUPPORT_UVD_MGCG )) { data =RREG32_UVD_CTX (ixUVD_CGC_MEM_CTRL);
@@ -620,7 +620,7 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev,static void uvd_v4_2_set_dcm (struct amdgpu_device *adev,bool sw_mode) { -u32 tmp, tmp2; +uint32_t tmp, tmp2;WREG32_FIELD (UVD_CGC_GATE ,REGS ,0 );
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2.12.0 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 2/4 drm/amd/amdgpu: Tidy up uvd_v4_2_start()
In reply to a message not in the archiveFix indentation and use WREG32_FIELD to clean up.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +6 -13
@@ -302,13 +302,9 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)/* enable UMC */ WREG32_P (mmUVD_LMI_CTRL2,0 , ~(1 <<8 )); - -WREG32_P (mmUVD_SOFT_RESET,0 , ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK ); - -WREG32_P (mmUVD_SOFT_RESET,0 , ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK ); - -WREG32_P (mmUVD_SOFT_RESET,0 , ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK ); - +WREG32_FIELD (UVD_SOFT_RESET ,LMI_SOFT_RESET ,0 ); +WREG32_FIELD (UVD_SOFT_RESET ,LMI_UMC_SOFT_RESET ,0 ); +WREG32_FIELD (UVD_SOFT_RESET ,VCPU_SOFT_RESET ,0 );mdelay (10 );for (i =0 ; i <10 ; ++i) {
@@ -324,10 +320,9 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)break ;DRM_ERROR ("UVD not responding, trying to reset the VCPU!!!\n" ); -WREG32_P (mmUVD_SOFT_RESET,UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK , - ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK ); +WREG32_FIELD (UVD_SOFT_RESET ,VCPU_SOFT_RESET ,1 );mdelay (10 ); -WREG32_P (mmUVD_SOFT_RESET,0 , ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK ); +WREG32_FIELD (UVD_SOFT_RESET ,VCPU_SOFT_RESET ,0 );mdelay (10 ); r =-1 ; }
@@ -339,7 +334,6 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)/* enable interupt */ WREG32_P (mmUVD_MASTINT_EN,3 <<1 , ~(3 <<1 )); -WREG32_P (mmUVD_STATUS,0 , ~(1 <<2 ));/* force RBC into idle state */
@@ -348,7 +342,7 @@ static int uvd_v4_2_start(struct amdgpu_device *adev)/* Set the write pointer delay */ WREG32 (mmUVD_RBC_RB_WPTR_CNTL,0 ); -/* programm the 4GB memory segment for rptr and ring buffer */ +/* program the 4GB memory segment for rptr and ring buffer */ WREG32 (mmUVD_LMI_EXT40_ADDR,upper_32_bits (ring->gpu_addr) | (0x7 <<16 ) | (0x1 <<31 ));
@@ -420,7 +414,6 @@ static void uvd_v4_2_stop(struct amdgpu_device *adev) }WREG32_P (0x3D49 ,0 , ~(1 <<2 )); -WREG32_P (mmUVD_VCPU_CNTL,0 , ~(1 <<9 ));/* put LMI, VCPU, RBC etc... into reset */
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PATCH 3/4 drm/amd/amdgpu: Cleanup uvd_v4_2_soft_reset()
In reply to a message not in the archiveUse WREG32_FIELD instead.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +1 -2
@@ -662,8 +662,7 @@ static int uvd_v4_2_soft_reset(void *handle)uvd_v4_2_stop (adev); -WREG32_P (mmSRBM_SOFT_RESET,SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK , - ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK ); +WREG32_FIELD (SRBM_SOFT_RESET ,SOFT_RESET_UVD ,1 );mdelay (5 );return uvd_v4_2_start (adev);
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PATCH 4/4 drm/amd/amdgpu: Use 32/64-bit types for VCE2
In reply to a message not in the archiveThe uintNN_t types were already in use except for a few spots.
Signed-off-by Tom St Denis <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +3 -3
@@ -146,7 +146,7 @@ static void vce_v2_0_disable_cg(struct amdgpu_device *adev)static void vce_v2_0_init_cg (struct amdgpu_device *adev) { -u32 tmp; +uint32_t tmp; tmp =RREG32 (mmVCE_CLOCK_GATING_A); tmp &= ~0xfff ;
@@ -309,7 +309,7 @@ static int vce_v2_0_stop(struct amdgpu_device *adev)static void vce_v2_0_set_sw_cg (struct amdgpu_device *adev,bool gated) { -u32 tmp; +uint32_t tmp;if (gated) { tmp =RREG32 (mmVCE_CLOCK_GATING_B);
@@ -344,7 +344,7 @@ static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)static void vce_v2_0_set_dyn_cg (struct amdgpu_device *adev,bool gated) { -u32 orig, tmp; +uint32_t orig, tmp;/* LMI_MC/LMI_UMC always set in dynamic, * set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0}
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