sf: improve support of (Q)SPI flash memories

From: Cyrille Pitchen <[email protected]>

This patch introduces 'struct spi_flash_command' and functions spi_is_flash_command_supported() / spi_exec_flash_command().

drivers/spi/spi-uclass.c +25 -0

+bool dm_spi_is_flash_command_supported(struct udevice *dev,
+                                      const struct spi_flash_command *cmd)
+{
+       struct udevice *bus = dev->parent;
+       struct dm_spi_ops *ops = spi_get_ops(bus);
+
+       if (ops->is_flash_command_supported)
+               return ops->is_flash_command_supported(dev, cmd);
+
+       return false;
+}
+
+int dm_spi_exec_flash_command(struct udevice *dev,
+                             const struct spi_flash_command *cmd)
+{
+       struct udevice *bus = dev->parent;
+       struct dm_spi_ops *ops = spi_get_ops(bus);
+
+       if (ops->exec_flash_command)
+               return ops->exec_flash_command(dev, cmd);
+
+       return -EINVAL;
+}
+
 int spi_claim_bus(struct spi_slave *slave)
 {
        return dm_spi_claim_bus(slave->dev);

@@ -107,6 +131,18 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
        return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
 }
 
+bool spi_is_flash_command_supported(struct spi_slave *slave,

drivers/spi/spi-uclass.c +5 -0

+
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 static int spi_child_post_bind(struct udevice *dev)
 {

@@ -144,6 +180,10 @@ static int spi_post_probe(struct udevice *bus)
                ops->set_mode += gd->reloc_off;
        if (ops->cs_info)
                ops->cs_info += gd->reloc_off;
+       if (ops->is_flash_command_supported)
+               ops->is_flash_command_supported += gd->reloc_off;
+       if (ops->exec_flash_command)
+               ops->exec_flash_command += gd->reloc_off;
 #endif
 
        return 0;

drivers/spi/spi.c +13 -0

index 7d81fbd7f8..e47acdc9e4 100644
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>

@@ -58,3 +59,15 @@ struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
        return spi_setup_slave(busnum, cs, max_hz, mode);
 }
 #endif
+
+__weak bool spi_is_flash_command_supported(struct spi_slave *slave,
+                                          const struct spi_flash_command *cmd)
+{
+       return false;
+}
+
+__weak int spi_exec_flash_command(struct spi_slave *slave,
+                                 const struct spi_flash_command *cmd)
+{
+       return -EINVAL;
+}

include/spi.h +26 -0

index 8c4b882c54..a090266b52 100644
@@ -10,6 +10,8 @@
 #ifndef _SPI_H_
 #define _SPI_H_
 
+#include <linux/string.h> /* memset() */
+
 /* SPI mode flags */
 #define SPI_CPHA       BIT(0)                  /* clock phase */
 #define SPI_CPOL       BIT(1)                  /* clock polarity */

@@ -64,6 +66,116 @@ struct dm_spi_slave_platdata {
 #endif /* CONFIG_DM_SPI */
 
 /**
+ * enum spi_flash_protocol - SPI flash command protocol
+ */
+#define SPI_FPROTO_INST_SHIFT  16
+#define SPI_FPROTO_INST_MASK   GENMASK(23, 16)
+#define SPI_FPROTO_INST(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_INST_SHIFT) &  \
+        SPI_FPROTO_INST_MASK)
+
+#define SPI_FPROTO_ADDR_SHIFT  8
+#define SPI_FPROTO_ADDR_MASK   GENMASK(15, 8)
+#define SPI_FPROTO_ADDR(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_ADDR_SHIFT) &  \
+        SPI_FPROTO_ADDR_MASK)
+
+#define SPI_FPROTO_DATA_SHIFT  0
+#define SPI_FPROTO_DATA_MASK   GENMASK(7, 0)
+#define SPI_FPROTO_DATA(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_DATA_SHIFT) &  \
+        SPI_FPROTO_DATA_MASK)
+
+#define SPI_FPROTO(inst_nbits, addr_nbits, data_nbits) \
+       (SPI_FPROTO_INST(inst_nbits) |                  \
+        SPI_FPROTO_ADDR(addr_nbits) |                  \
+        SPI_FPROTO_DATA(data_nbits))

include/spi.h +46 -0

+
+static inline
+u8 spi_flash_protocol_get_inst_nbits(enum spi_flash_protocol proto)
+{
+       return ((unsigned long)(proto & SPI_FPROTO_INST_MASK)) >>
+               SPI_FPROTO_INST_SHIFT;
+}
+
+static inline
+u8 spi_flash_protocol_get_addr_nbits(enum spi_flash_protocol proto)
+{
+       return ((unsigned long)(proto & SPI_FPROTO_ADDR_MASK)) >>
+               SPI_FPROTO_ADDR_SHIFT;
+}
+
+static inline
+u8 spi_flash_protocol_get_data_nbits(enum spi_flash_protocol proto)
+{
+       return ((unsigned long)(proto & SPI_FPROTO_DATA_MASK)) >>
+               SPI_FPROTO_DATA_SHIFT;
+}
+
+/**
+ * struct spi_flash_command - SPI flash command structure
+ *
+ * @instr:             Opcode sent to the SPI slave during instr clock cycles.
+ * @mode:              Value sent to the SPI slave during mode clock cycles.
+ * @num_mode_cycles:   Number of mode clock cycles.
+ * @num_wait_states:   Number of wait-state clock cycles.
+ * @addr_len:          Number of bytes sent during address clock cycles:
+ *                     should be 0, 3, or 4.
+ * @addr:              Value sent to the SPI slave during address clock cycles.
+ * @data_len:          Number of bytes to be sent during data clock cycles.
+ * @tx_data:           Data sent to the SPI slave during data clock cycles.
+ * @rx_data:           Data read from the SPI slave during data clock cycles.
+ */
+struct spi_flash_command {
+       enum spi_flash_protocol proto;
+       u8 flags;
+#define SPI_FCMD_TYPE          GENMASK(2, 0)
+#define SPI_FCMD_READ          (0x0U << 0)
+#define SPI_FCMD_WRITE         (0x1U << 0)
+#define SPI_FCMD_ERASE         (0x2U << 0)
+#define SPI_FCMD_READ_REG      (0x3U << 0)
+#define SPI_FCMD_WRITE_REG     (0x4U << 0)
+

-----Original Message-----
From: Jagan Teki [mailto:jagannadh.teki at gmail.com]
Sent: 2017年8月30日 21:50
To: Wenyou Yang - A41535 <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Marek Vasut <[email protected]>; Cyrille Pitchen <[email protected]>; Jagan Teki <[email protected]>
Subject: Re: [U-Boot] [PATCH v3 1/8] spi: add support of SPI flash commands

Quoted 5 lines · Wenyou Yang

From: Cyrille Pitchen <[email protected]>

This patch introduces 'struct spi_flash_command' and functions spi_is_flash_command_supported() / spi_exec_flash_command().

Answer for why this shouldn't be part of SPI area.

[snip]

drivers/spi and include/spi.h is Generic SPI area code - this can deal all connected slave devices like EEPROM, SPI-NOR etc drivers/mtd/spi and include/spi_flash.h is SPI-Flash or SPI-NOR code - this can handle only SPI flashes.

Quoted 29 lines

drivers/spi/spi-uclass.c +23 -0

+bool dm_spi_is_flash_command_supported(struct udevice *dev,
+                                      const struct spi_flash_command
+*cmd) {
+       struct udevice *bus = dev->parent;
+       struct dm_spi_ops *ops = spi_get_ops(bus);
+
+       if (ops->is_flash_command_supported)
+               return ops->is_flash_command_supported(dev, cmd);
+
+       return false;
+}
+
+int dm_spi_exec_flash_command(struct udevice *dev,
+                             const struct spi_flash_command *cmd) {
+       struct udevice *bus = dev->parent;
+       struct dm_spi_ops *ops = spi_get_ops(bus);
+
+       if (ops->exec_flash_command)
+               return ops->exec_flash_command(dev, cmd);
+
+       return -EINVAL;
+}
+
 int spi_claim_bus(struct spi_slave *slave)  {
        return dm_spi_claim_bus(slave->dev); @@ -107,6 +131,18 @@ int

spi_xfer(struct spi_slave *slave, unsigned int bitlen,

        return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);  }

Review

Quoted 8 lines

(quoted diff) +8 -0

+bool spi_is_flash_command_supported(struct spi_slave *slave,
+                                   const struct spi_flash_command
+*cmd) {
+       return dm_spi_is_flash_command_supported(slave->dev, cmd); }
+
+int spi_exec_flash_command(struct spi_slave *slave,
+                          const struct spi_flash_command *cmd) {
+       return dm_spi_exec_flash_command(slave->dev, cmd); }

Handling spi-flash stuff in spi core is not proper way of dealing, and I saw these functions are not-at-all needed for generic controller drivers in drivers/spi except the Atmel QSPI driver (in v3,8/8).

drivers/spi/spi.c struct spi_slave *spi_base_setup_slave_fdt(const void

Quoted 27 lines

drivers/spi/spi-uclass.c +6 -0

+
 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
 static int spi_child_post_bind(struct udevice *dev)  { @@ -144,6
+180,10 @@ static int spi_post_probe(struct udevice *bus)
                ops->set_mode += gd->reloc_off;
        if (ops->cs_info)
                ops->cs_info += gd->reloc_off;
+       if (ops->is_flash_command_supported)
+               ops->is_flash_command_supported += gd->reloc_off;
+       if (ops->exec_flash_command)
+               ops->exec_flash_command += gd->reloc_off;
 #endif
 
        return 0;

drivers/spi/spi.c index renamed from drivers/spi/spi.c +0 -0

7d81fbd7f8..e47acdc9e4 100644

drivers/spi/spi.c +1 -0

@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <errno.h>
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>

@@ -58,3 +59,15 @@ struct spi_slave *spi_base_setup_slave_fdt(const void

*blob, int busnum,

Quoted 52 lines

drivers/spi/spi.c +12 -0

        return spi_setup_slave(busnum, cs, max_hz, mode);  }  #endif
+
+__weak bool spi_is_flash_command_supported(struct spi_slave *slave,
+                                          const struct
+spi_flash_command *cmd) {
+       return false;
+}
+
+__weak int spi_exec_flash_command(struct spi_slave *slave,
+                                 const struct spi_flash_command *cmd)
+{
+       return -EINVAL;
+}

include/spi.h index renamed from include/spi.h +0 -0

8c4b882c54..a090266b52 100644

include/spi.h +2 -0

@@ -10,6 +10,8 @@
 #ifndef _SPI_H_
 #define _SPI_H_
 
+#include <linux/string.h> /* memset() */
+
 /* SPI mode flags */
 #define SPI_CPHA       BIT(0)                  /* clock phase */
 #define SPI_CPOL       BIT(1)                  /* clock polarity */

@@ -64,6 +66,116 @@ struct dm_spi_slave_platdata {  #endif /*

CONFIG_DM_SPI */

/**
+ * enum spi_flash_protocol - SPI flash command protocol */ #define

include/spi.h +21 -0

+SPI_FPROTO_INST_SHIFT  16
+#define SPI_FPROTO_INST_MASK   GENMASK(23, 16)
+#define SPI_FPROTO_INST(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_INST_SHIFT) &  \
+        SPI_FPROTO_INST_MASK)
+
+#define SPI_FPROTO_ADDR_SHIFT  8
+#define SPI_FPROTO_ADDR_MASK   GENMASK(15, 8)
+#define SPI_FPROTO_ADDR(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_ADDR_SHIFT) &  \
+        SPI_FPROTO_ADDR_MASK)
+
+#define SPI_FPROTO_DATA_SHIFT  0
+#define SPI_FPROTO_DATA_MASK   GENMASK(7, 0)
+#define SPI_FPROTO_DATA(nbits)                                 \
+       ((((unsigned long)(nbits)) << SPI_FPROTO_DATA_SHIFT) &  \
+        SPI_FPROTO_DATA_MASK)
+
+#define SPI_FPROTO(inst_nbits, addr_nbits, data_nbits) \
+       (SPI_FPROTO_INST(inst_nbits) |                  \
+        SPI_FPROTO_ADDR(addr_nbits) |                  \

include/spi.h struct dm_spi_slave_platdata {

Quoted 10 lines

include/spi.h +10 -0

+        SPI_FPROTO_DATA(data_nbits))
+
+enum spi_flash_protocol {
+       SPI_FPROTO_1_1_1 = SPI_FPROTO(1, 1, 1),
+       SPI_FPROTO_1_1_2 = SPI_FPROTO(1, 1, 2),
+       SPI_FPROTO_1_1_4 = SPI_FPROTO(1, 1, 4),
+       SPI_FPROTO_1_2_2 = SPI_FPROTO(1, 2, 2),
+       SPI_FPROTO_1_4_4 = SPI_FPROTO(1, 4, 4),
+       SPI_FPROTO_2_2_2 = SPI_FPROTO(2, 2, 2),
+       SPI_FPROTO_4_4_4 = SPI_FPROTO(4, 4, 4), };

these protocol also includes IO's like dual and quad and IO's which are specific for SPI-NOR flash and not Generic SPI protocols.

Quoted 40 lines

include/spi.h +40 -0

+
+static inline
+u8 spi_flash_protocol_get_inst_nbits(enum spi_flash_protocol proto) {
+       return ((unsigned long)(proto & SPI_FPROTO_INST_MASK)) >>
+               SPI_FPROTO_INST_SHIFT; }
+
+static inline
+u8 spi_flash_protocol_get_addr_nbits(enum spi_flash_protocol proto) {
+       return ((unsigned long)(proto & SPI_FPROTO_ADDR_MASK)) >>
+               SPI_FPROTO_ADDR_SHIFT; }
+
+static inline
+u8 spi_flash_protocol_get_data_nbits(enum spi_flash_protocol proto) {
+       return ((unsigned long)(proto & SPI_FPROTO_DATA_MASK)) >>
+               SPI_FPROTO_DATA_SHIFT; }
+
+/**
+ * struct spi_flash_command - SPI flash command structure
+ *
+ * @instr:             Opcode sent to the SPI slave during instr clock cycles.
+ * @mode:              Value sent to the SPI slave during mode clock cycles.
+ * @num_mode_cycles:   Number of mode clock cycles.
+ * @num_wait_states:   Number of wait-state clock cycles.
+ * @addr_len:          Number of bytes sent during address clock cycles:
+ *                     should be 0, 3, or 4.
+ * @addr:              Value sent to the SPI slave during address clock cycles.
+ * @data_len:          Number of bytes to be sent during data clock cycles.
+ * @tx_data:           Data sent to the SPI slave during data clock cycles.
+ * @rx_data:           Data read from the SPI slave during data clock cycles.
+ */
+struct spi_flash_command {
+       enum spi_flash_protocol proto;
+       u8 flags;
+#define SPI_FCMD_TYPE          GENMASK(2, 0)
+#define SPI_FCMD_READ          (0x0U << 0)
+#define SPI_FCMD_WRITE         (0x1U << 0)
+#define SPI_FCMD_ERASE         (0x2U << 0)
+#define SPI_FCMD_READ_REG      (0x3U << 0)
+#define SPI_FCMD_WRITE_REG     (0x4U << 0)
+

include/spi.h struct dm_spi_slave_platdata { · line 158

Quoted 10 lines

include/spi.h +10 -0

+       u8 inst;
+       u8 mode;
+       u8 num_mode_cycles;
+       u8 num_wait_states;
+       u8 addr_len;
+       u32 addr;
+       size_t data_len;
+       const void *tx_data;
+       void *rx_data;
+};

I saw from the other patches, this structure is initializing for each I/O interface between SPI to driver/mtd like spi_transfer, if so it shouldn't have flash attributes. Better to move flash contents to spi_flash structure and do the respective operations.

thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.

From: Cyrille Pitchen <[email protected]>

Now that the SPI sub-system API has been extended with 'struct spi_flash_command' and spi_is_flash_command_supported() / spi_exec_flash_command() functions, we update the SPI FLASH sub-system to use this new API.

Signed-off-by Cyrille Pitchen <[email protected]>

Signed-off-by Wenyou Yang <[email protected]>

---

Changes in v3: None
Changes in v2: None

 drivers/mtd/spi/sf.c           |  78 +++++++++++++----
 drivers/mtd/spi/sf_dataflash.c | 119 +++++++++++++-------------
 drivers/mtd/spi/sf_internal.h  |  24 +++---
 drivers/mtd/spi/spi_flash.c    | 184 +++++++++++++++++++++++------------------
 4 files changed, 236 insertions(+), 169 deletions(-)

drivers/mtd/spi/sf.c +60 -18

index d5e175ca00..6178b0aa98 100644
@@ -9,46 +9,88 @@
 
 #include <common.h>
 #include <spi.h>
+#include <spi_flash.h>
 
-static int spi_flash_read_write(struct spi_slave *spi,
-                               const u8 *cmd, size_t cmd_len,
-                               const u8 *data_out, u8 *data_in,
-                               size_t data_len)
+#include "sf_internal.h"
+
+static void spi_flash_addr(u32 addr, u8 addr_len, u8 *cmd_buf)
 {
+       u8 i;
+
+       for (i = 0; i < addr_len; i++)
+               cmd_buf[i] = addr >> ((addr_len - 1 - i) * 8);
+}
+
+static u8 spi_compute_num_dummy_bytes(enum spi_flash_protocol proto,
+                                     u8 num_dummy_clock_cycles)
+{
+       int shift = fls(spi_flash_protocol_get_addr_nbits(proto)) - 1;
+
+       if (shift < 0)
+               shift = 0;
+       return (num_dummy_clock_cycles << shift) >> 3;
+}
+
+static int spi_flash_exec(struct spi_flash *flash,
+                         const struct spi_flash_command *cmd)
+{
+       struct spi_slave *spi = flash->spi;
+       u8 cmd_buf[SPI_FLASH_CMD_LEN];
+       size_t cmd_len, num_dummy_bytes;
        unsigned long flags = SPI_XFER_BEGIN;
        int ret;
 
-       if (data_len == 0)
+       if (spi_is_flash_command_supported(spi, cmd))
+               return spi_exec_flash_command(spi, cmd);
+
+       if (cmd->data_len == 0)
                flags |= SPI_XFER_END;
 
-       ret = spi_xfer(spi, cmd_len * 8, cmd, NULL, flags);
+       cmd_buf[0] = cmd->inst;
+       spi_flash_addr(cmd->addr, cmd->addr_len, cmd_buf + 1);
+       cmd_len = 1 + cmd->addr_len;
+
+       num_dummy_bytes = spi_compute_num_dummy_bytes(cmd->proto,
+                                                     cmd->num_mode_cycles +
+                                                     cmd->num_wait_states);
+       memset(cmd_buf + cmd_len, 0xff, num_dummy_bytes);
+       cmd_len += num_dummy_bytes;
+
+       ret = spi_xfer(spi, cmd_len * 8, cmd_buf, NULL, flags);
        if (ret) {
                debug("SF: Failed to send command (%zu bytes): %d\n",
                      cmd_len, ret);
-       } else if (data_len != 0) {
-               ret = spi_xfer(spi, data_len * 8, data_out, data_in,
-                                       SPI_XFER_END);
+       } else if (cmd->data_len != 0) {
+               ret = spi_xfer(spi, cmd->data_len * 8,
+                              cmd->tx_data, cmd->rx_data,
+                              SPI_XFER_END);
                if (ret)
                        debug("SF: Failed to transfer %zu bytes of data: %d\n",
-                             data_len, ret);
+                             cmd->data_len, ret);
        }
 
        return ret;
 }
 
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
-               size_t cmd_len, void *data, size_t data_len)
+int spi_flash_cmd_read(struct spi_flash *flash,
+                      const struct spi_flash_command *cmd)
 {
-       return spi_flash_read_write(spi, cmd, cmd_len, NULL, data, data_len);
+       return spi_flash_exec(flash, cmd);
 }
 
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len)
+int spi_flash_cmd(struct spi_flash *flash, u8 instr, void *response, size_t len)
 {
-       return spi_flash_cmd_read(spi, &cmd, 1, response, len);
+       struct spi_flash_command cmd;
+       u8 flags = (response && len) ? SPI_FCMD_READ_REG : SPI_FCMD_WRITE_REG;
+
+       spi_flash_command_init(&cmd, instr, 0, flags);
+       cmd.data_len = len;
+       cmd.rx_data = response;
+       return spi_flash_exec(flash, &cmd);
 }
 
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
-               const void *data, size_t data_len)
+int spi_flash_cmd_write(struct spi_flash *flash,
+                       const struct spi_flash_command *cmd)
 {
-       return spi_flash_read_write(spi, cmd, cmd_len, data, NULL, data_len);
+       return spi_flash_exec(flash, cmd);
 }

drivers/mtd/spi/sf_dataflash.c +61 -58

index bcddfa0755..b2166ad4e5 100644
@@ -73,7 +73,7 @@ struct dataflash {
 };
 
 /* Return the status of the DataFlash device */
-static inline int dataflash_status(struct spi_slave *spi)
+static inline int dataflash_status(struct spi_flash *spi_flash)
 {
        int ret;
        u8 status;

@@ -81,7 +81,7 @@ static inline int dataflash_status(struct spi_slave *spi)
         * NOTE:  at45db321c over 25 MHz wants to write
         * a dummy byte after the opcode...
         */
-       ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
+       ret = spi_flash_cmd(spi_flash, OP_READ_STATUS, &status, 1);
        return ret ? -EIO : status;
 }
 

@@ -90,7 +90,7 @@ static inline int dataflash_status(struct spi_slave *spi)
  * This usually takes 5-20 msec or so; more for sector erase.
  * ready: return > 0
  */
-static int dataflash_waitready(struct spi_slave *spi)
+static int dataflash_waitready(struct spi_flash *spi_flash)
 {
        int status;
        int timeout = 2 * CONFIG_SYS_HZ;

@@ -98,7 +98,7 @@ static int dataflash_waitready(struct spi_slave *spi)
 
        timebase = get_timer(0);
        do {
-               status = dataflash_status(spi);
+               status = dataflash_status(spi_flash);
                if (status < 0)
                        status = 0;
 

@@ -114,11 +114,11 @@ static int dataflash_waitready(struct spi_slave *spi)
 /* Erase pages of flash */
 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 {
+       struct spi_flash_command        cmd;
        struct dataflash        *dataflash;
        struct spi_flash        *spi_flash;
        struct spi_slave        *spi;
        unsigned                blocksize;
-       uint8_t                 *command;
        uint32_t                rem;
        int                     status;
 

@@ -128,9 +128,6 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 
        blocksize = spi_flash->page_size << 3;
 
-       memset(dataflash->command, 0 , sizeof(dataflash->command));
-       command = dataflash->command;
-
        debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
 
        div_u64_rem(len, spi_flash->page_size, &rem);

@@ -146,6 +143,8 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
                return status;
        }
 
+       spi_flash_command_init(&cmd, OP_ERASE_BLOCK, SPI_FLASH_3B_ADDR_LEN,
+                              SPI_FCMD_ERASE);
        while (len > 0) {
                unsigned int    pageaddr;
                int             do_block;

@@ -157,23 +156,24 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
                do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
                pageaddr = pageaddr << dataflash->page_offset;
 
-               command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
-               command[1] = (uint8_t)(pageaddr >> 16);
-               command[2] = (uint8_t)(pageaddr >> 8);
-               command[3] = 0;
+               cmd.inst = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
+               cmd.addr = pageaddr & 0x00FFFF00;
 
                debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
                      dev->name, do_block ? "block" : "page",
-                     command[0], command[1], command[2], command[3],
+                     cmd.inst,
+                     (cmd.addr >> 16) & 0xff,
+                     (cmd.addr >>  8) & 0xff,
+                     (cmd.addr >>  0) & 0xff,
                      pageaddr);
 
-               status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+               status = spi_flash_cmd_write(spi_flash, &cmd);
                if (status < 0) {
                        debug("%s: erase send command error!\n", dev->name);
                        return -EIO;
                }
 
-               status = dataflash_waitready(spi);
+               status = dataflash_waitready(spi_flash);
                if (status < 0) {
                        debug("%s: erase waitready error!\n", dev->name);
                        return status;

@@ -202,23 +202,18 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
                              void *buf)
 {
+       struct spi_flash_command        cmd;
        struct dataflash        *dataflash;
        struct spi_flash        *spi_flash;
        struct spi_slave        *spi;
        unsigned int            addr;
-       uint8_t                 *command;
        int                     status;
 
        dataflash = dev_get_priv(dev);
        spi_flash = dev_get_uclass_priv(dev);
        spi = spi_flash->spi;
 
-       memset(dataflash->command, 0 , sizeof(dataflash->command));
-       command = dataflash->command;
-
-       debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
-       debug("READ: (%x) %x %x %x\n",
-             command[0], command[1], command[2], command[3]);
+       debug("%s: read addr=0x%x len 0x%x\n", dev->name, offset, len);
 
        /* Calculate flash page/byte address */
        addr = (((unsigned)offset / spi_flash->page_size)

@@ -236,13 +231,15 @@ static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
         * the peak rate available.  Some chips support commands with
         * fewer "don't care" bytes.  Both buffers stay unchanged.
         */
-       command[0] = OP_READ_CONTINUOUS;
-       command[1] = (uint8_t)(addr >> 16);
-       command[2] = (uint8_t)(addr >> 8);
-       command[3] = (uint8_t)(addr >> 0);
+       spi_flash_command_init(&cmd, OP_READ_CONTINUOUS, SPI_FLASH_3B_ADDR_LEN,
+                              SPI_FCMD_READ);
+       cmd.addr = addr;
+       cmd.num_wait_states = 4 * 8; /* 4 "don't care" bytes */
+       cmd.data_len = len;
+       cmd.rx_data = buf;
 
        /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
-       status = spi_flash_cmd_read(spi, command, 8, buf, len);
+       status = spi_flash_cmd_read(spi_flash, &cmd);
 
        spi_release_bus(spi);
 

@@ -258,10 +255,10 @@ static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
                        const void *buf)
 {
+       struct spi_flash_command        cmd;
        struct dataflash        *dataflash;
        struct spi_flash        *spi_flash;
        struct spi_slave        *spi;
-       uint8_t                 *command;
        unsigned int            pageaddr, addr, to, writelen;
        size_t                  remaining = len;
        u_char                  *writebuf = (u_char *)buf;

@@ -271,9 +268,6 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
        spi_flash = dev_get_uclass_priv(dev);
        spi = spi_flash->spi;
 
-       memset(dataflash->command, 0 , sizeof(dataflash->command));
-       command = dataflash->command;
-
        debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
 
        pageaddr = ((unsigned)offset / spi_flash->page_size);

@@ -289,6 +283,8 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
                return status;
        }
 
+       spi_flash_command_init(&cmd, OP_TRANSFER_BUF1, SPI_FLASH_3B_ADDR_LEN,
+                              SPI_FCMD_WRITE);
        while (remaining > 0) {
                debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
 

@@ -313,22 +309,25 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
 
                /* (1) Maybe transfer partial page to Buffer1 */
                if (writelen != spi_flash->page_size) {
-                       command[0] = OP_TRANSFER_BUF1;
-                       command[1] = (addr & 0x00FF0000) >> 16;
-                       command[2] = (addr & 0x0000FF00) >> 8;
-                       command[3] = 0;
+                       cmd.inst = OP_TRANSFER_BUF1;
+                       cmd.addr = (addr & 0x00FFFF00);
+                       cmd.data_len = 0;
+                       cmd.tx_data = NULL;
 
                        debug("TRANSFER: (%x) %x %x %x\n",
-                             command[0], command[1], command[2], command[3]);
+                             cmd.inst,
+                             (cmd.addr >> 16) & 0xff,
+                             (cmd.addr >>  8) & 0xff,
+                             (cmd.addr >>  0) & 0xff);
 
-                       status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+                       status = spi_flash_cmd_write(spi_flash, &cmd);
                        if (status < 0) {
                                debug("%s: write(<pagesize) command error!\n",
                                      dev->name);
                                return -EIO;
                        }
 
-                       status = dataflash_waitready(spi);
+                       status = dataflash_waitready(spi_flash);
                        if (status < 0) {
                                debug("%s: write(<pagesize) waitready error!\n",
                                      dev->name);

@@ -338,22 +337,24 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
 
                /* (2) Program full page via Buffer1 */
                addr += to;
-               command[0] = OP_PROGRAM_VIA_BUF1;
-               command[1] = (addr & 0x00FF0000) >> 16;
-               command[2] = (addr & 0x0000FF00) >> 8;
-               command[3] = (addr & 0x000000FF);
+               cmd.inst = OP_PROGRAM_VIA_BUF1;
+               cmd.addr = addr;
+               cmd.data_len = writelen;
+               cmd.tx_data = writebuf;
 
                debug("PROGRAM: (%x) %x %x %x\n",
-                     command[0], command[1], command[2], command[3]);
+                     cmd.inst,
+                     (cmd.addr >> 16) & 0xff,
+                     (cmd.addr >>  8) & 0xff,
+                     (cmd.addr >>  0) & 0xff);
 
-               status = spi_flash_cmd_write(spi, command,
-                                            4, writebuf, writelen);
+               status = spi_flash_cmd_write(spi_flash, &cmd);
                if (status < 0) {
                        debug("%s: write send command error!\n", dev->name);
                        return -EIO;
                }
 
-               status = dataflash_waitready(spi);
+               status = dataflash_waitready(spi_flash);
                if (status < 0) {
                        debug("%s: write waitready error!\n", dev->name);
                        return status;

@@ -362,16 +363,18 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
                /* (3) Compare to Buffer1 */
                addr = pageaddr << dataflash->page_offset;
-               command[0] = OP_COMPARE_BUF1;
-               command[1] = (addr & 0x00FF0000) >> 16;
-               command[2] = (addr & 0x0000FF00) >> 8;
-               command[3] = 0;
+               cmd.inst = OP_COMPARE_BUF1;
+               cmd.addr = addr & 0x00FFFF00;
+               cmd.data_len = writelen;
+               cmd.tx_data = writebuf;
 
                debug("COMPARE: (%x) %x %x %x\n",
-                     command[0], command[1], command[2], command[3]);
+                     cmd.inst,
+                     (cmd.addr >> 16) & 0xff,
+                     (cmd.addr >>  8) & 0xff,
+                     (cmd.addr >>  0) & 0xff);
 
-               status = spi_flash_cmd_write(spi, command,
-                                            4, writebuf, writelen);
+               status = spi_flash_cmd_write(spi, &cmd);
                if (status < 0) {
                        debug("%s: write(compare) send command error!\n",
                              dev->name);

@@ -496,7 +499,7 @@ static struct flash_info dataflash_data[] = {
        { "at45db642d",  0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
 };
 
-static struct flash_info *jedec_probe(struct spi_slave *spi)
+static struct flash_info *jedec_probe(struct spi_flash *spi_flash)
 {
        int                     tmp;
        uint8_t                 id[5];

@@ -513,7 +516,7 @@ static struct flash_info *jedec_probe(struct spi_slave *spi)
         * That's not an error; only rev C and newer chips handle it, and
         * only Atmel sells these chips.
         */
-       tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
+       tmp = spi_flash_cmd(spi_flash, CMD_READ_ID, id, sizeof(id));
        if (tmp < 0) {
                printf("dataflash: error %d reading JEDEC ID\n", tmp);
                return ERR_PTR(tmp);

@@ -532,7 +535,7 @@ static struct flash_info *jedec_probe(struct spi_slave *spi)
                        tmp++, info++) {
                if (info->jedec_id == jedec) {
                        if (info->flags & SUP_POW2PS) {
-                               status = dataflash_status(spi);
+                               status = dataflash_status(spi_flash);
                                if (status < 0) {
                                        debug("dataflash: status error %d\n",
                                              status);

@@ -596,7 +599,7 @@ static int spi_dataflash_probe(struct udevice *dev)
         * Both support the security register, though with different
         * write procedures.
         */
-       info = jedec_probe(spi);
+       info = jedec_probe(spi_flash);
        if (IS_ERR(info))
                goto err_jedec_probe;
        if (info != NULL) {

@@ -611,7 +614,7 @@ static int spi_dataflash_probe(struct udevice *dev)
        * Older chips support only legacy commands, identifing
        * capacity using bits in the status byte.
        */
-       status = dataflash_status(spi);
+       status = dataflash_status(spi_flash);
        if (status <= 0 || status == 0xff) {
                printf("dataflash: read status error %d\n", status);
                if (status == 0 || status == 0xff)

drivers/mtd/spi/sf_internal.h +12 -12

index 839cdbe1b0..5c551089d6 100644
@@ -27,7 +27,7 @@ enum spi_nor_option_flags {
 };
 
 #define SPI_FLASH_3B_ADDR_LEN          3
-#define SPI_FLASH_CMD_LEN              (1 + SPI_FLASH_3B_ADDR_LEN)
+#define SPI_FLASH_CMD_LEN              (1 + SPI_FLASH_3B_ADDR_LEN + 16)
 #define SPI_FLASH_16MB_BOUN            0x1000000
 
 /* CFI Manufacture ID's */

@@ -137,21 +137,21 @@ struct spi_flash_info {
 extern const struct spi_flash_info spi_flash_ids[];
 
 /* Send a single-byte command to the device and read the response */
-int spi_flash_cmd(struct spi_slave *spi, u8 cmd, void *response, size_t len);
+int spi_flash_cmd(struct spi_flash *flash, u8 instr, void *response, size_t len);
 
 /*
  * Send a multi-byte command to the device and read the response. Used
  * for flash array reads, etc.
  */
-int spi_flash_cmd_read(struct spi_slave *spi, const u8 *cmd,
-               size_t cmd_len, void *data, size_t data_len);
+int spi_flash_cmd_read(struct spi_flash *flash,
+                      const struct spi_flash_command *cmd);
 
 /*
  * Send a multi-byte command to the device followed by (optional)
  * data. Used for programming the flash array, etc.
  */
-int spi_flash_cmd_write(struct spi_slave *spi, const u8 *cmd, size_t cmd_len,
-               const void *data, size_t data_len);
+int spi_flash_cmd_write(struct spi_flash *flash,
+                       const struct spi_flash_command *cmd);
 
 
 /* Flash erase(sectors) operation, support all possible erase commands */

@@ -169,13 +169,13 @@ int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t len);
 /* Enable writing on the SPI flash */
 static inline int spi_flash_cmd_write_enable(struct spi_flash *flash)
 {
-       return spi_flash_cmd(flash->spi, CMD_WRITE_ENABLE, NULL, 0);
+       return spi_flash_cmd(flash, CMD_WRITE_ENABLE, NULL, 0);
 }
 
 /* Disable writing on the SPI flash */
 static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
 {
-       return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
+       return spi_flash_cmd(flash, CMD_WRITE_DISABLE, NULL, 0);
 }
 
 /*

@@ -186,8 +186,8 @@ static inline int spi_flash_cmd_write_disable(struct spi_flash *flash)
  * - spi_flash_wait_till_ready
  * - SPI release
  */
-int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
-               size_t cmd_len, const void *buf, size_t buf_len);
+int spi_flash_write_common(struct spi_flash *flash,
+                          const struct spi_flash_command *cmd);
 
 /*
  * Flash write operation, support all possible write commands.

@@ -201,8 +201,8 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
  * Same as spi_flash_cmd_read() except it also claims/releases the SPI
  * bus. Used as common part of the ->read() operation.
  */
-int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
-               size_t cmd_len, void *data, size_t data_len);
+int spi_flash_read_common(struct spi_flash *flash,
+                         const struct spi_flash_command *cmd);
 
 /* Flash read operation, support all possible read commands */
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,

drivers/mtd/spi/spi_flash.c +0 -8

index 0034a28d5f..80541d0ab4 100644
@@ -22,21 +22,15 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void spi_flash_addr(u32 addr, u8 *cmd)
-{
-       /* cmd[0] is actual command */
-       cmd[1] = addr >> 16;
-       cmd[2] = addr >> 8;
-       cmd[3] = addr >> 0;
-}
-
 static int read_sr(struct spi_flash *flash, u8 *rs)

From: Cyrille Pitchen <[email protected]>

This patch adds support to the Atmel Quad SPI controller.

Signed-off-by Cyrille Pitchen <[email protected]>

Signed-off-by Wenyou Yang <[email protected]>

---

Changes in v3: None
Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

 drivers/spi/Kconfig      |   7 +
 drivers/spi/Makefile     |   1 +
 drivers/spi/atmel_qspi.c | 404 +++++++++++++++++++++++++++++++++++++++++++++++
 drivers/spi/atmel_qspi.h | 169 ++++++++++++++++++++
 4 files changed, 581 insertions(+)
 create mode 100644 drivers/spi/atmel_qspi.c
 create mode 100644 drivers/spi/atmel_qspi.h

drivers/spi/Kconfig +7 -0

index 8a8e8e480f..b3e8cb941e 100644
@@ -32,6 +32,13 @@ config ATH79_SPI
          uses driver model and requires a device tree binding to operate.
          please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
 
+config ATMEL_QSPI
+       bool "Atmel QSPI driver"
+       depends on ARCH_AT91
+       help
+         Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be
+         used to access SPI NOR flashes.
+
 config ATMEL_SPI
        bool "Atmel SPI driver"
        depends on ARCH_AT91

drivers/spi/Makefile +1 -0

index 9f8b86de76..358db2b065 100644
@@ -18,6 +18,7 @@ endif
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
 obj-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel_qspi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_CADENCE_QSPI) += cadence_qspi.o cadence_qspi_apb.o
 obj-$(CONFIG_CF_SPI) += cf_spi.o

drivers/spi/atmel_qspi.c new file +292 -0

new file mode 100644
index 0000000000..0af7a4dc0a
@@ -0,0 +1,404 @@
+/*
+ * Copyright (C) 2017 Atmel Corporation
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <errno.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <mach/clk.h>
+#include "atmel_qspi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void atmel_qspi_memcpy_fromio(void *dst, unsigned long src, size_t len)
+{
+       u8 *d = (u8 *)dst;
+
+       while (len--) {
+               *d++ = readb(src);
+               src++;
+       }
+}
+
+static void atmel_qspi_memcpy_toio(unsigned long dst, const void *src,
+                                  size_t len)
+{
+       const u8 *s = (const u8 *)src;
+
+       while (len--) {
+               writeb(*s, dst);
+               dst++;
+               s++;
+       }
+}
+
+static int atmel_qspi_set_ifr_tfrtype(u8 flags, u32 *ifr)
+{
+       u32 ifr_tfrtype;
+
+       switch (flags & SPI_FCMD_TYPE) {
+       case SPI_FCMD_READ:
+               ifr_tfrtype = QSPI_IFR_TFRTYPE_READ_MEMORY;
+               break;
+
+       case SPI_FCMD_WRITE:
+               ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE_MEMORY;
+               break;
+
+       case SPI_FCMD_ERASE:
+       case SPI_FCMD_WRITE_REG:
+               ifr_tfrtype = QSPI_IFR_TFRTYPE_WRITE;
+               break;
+
+       case SPI_FCMD_READ_REG:
+               ifr_tfrtype = QSPI_IFR_TFRTYPE_READ;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       *ifr = (*ifr & ~QSPI_IFR_TFRTYPE) | ifr_tfrtype;
+       return 0;
+}
+
+static int atmel_qpsi_set_ifr_width(enum spi_flash_protocol proto, u32 *ifr)
+{
+       u32 ifr_width;
+
+       switch (proto) {
+       case SPI_FPROTO_1_1_1:
+               ifr_width = QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
+               break;
+
+       case SPI_FPROTO_1_1_2:
+               ifr_width = QSPI_IFR_WIDTH_DUAL_OUTPUT;
+               break;
+
+       case SPI_FPROTO_1_2_2:
+               ifr_width = QSPI_IFR_WIDTH_DUAL_IO;
+               break;
+
+       case SPI_FPROTO_2_2_2:
+               ifr_width = QSPI_IFR_WIDTH_DUAL_CMD;
+               break;
+
+       case SPI_FPROTO_1_1_4:
+               ifr_width = QSPI_IFR_WIDTH_QUAD_OUTPUT;
+               break;
+
+       case SPI_FPROTO_1_4_4:
+               ifr_width = QSPI_IFR_WIDTH_QUAD_IO;
+               break;
+
+       case SPI_FPROTO_4_4_4:
+               ifr_width = QSPI_IFR_WIDTH_QUAD_CMD;
+               break;
+
+       default:
+               return -EINVAL;
+       }
+
+       *ifr = (*ifr & ~QSPI_IFR_WIDTH) | ifr_width;
+       return 0;
+}
+
+static int atmel_qspi_xfer(struct udevice *dev, unsigned int bitlen,
+                          const void *dout, void *din, unsigned long flags)
+{
+       /* This controller can only be used with SPI NOR flashes. */
+       return -EINVAL;
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+       struct atmel_qspi_priv *aq = dev_get_priv(bus);
+       u32 scr, scbr, mask, new_value;
+
+       /* Compute the QSPI baudrate */
+       scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+       if (scbr > 0)
+               scbr--;
+
+       new_value = QSPI_SCR_SCBR_(scbr);
+       mask = QSPI_SCR_SCBR;
+
+       scr = qspi_readl(aq, QSPI_SCR);
+       if ((scr & mask) == new_value)
+               return 0;
+
+       scr = (scr & ~mask) | new_value;
+       qspi_writel(aq, QSPI_SCR, scr);
+
+       return 0;
+}
+
+static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
+{
+       struct atmel_qspi_priv *aq = dev_get_priv(bus);
+       u32 scr, mask, new_value;
+
+       new_value = (QSPI_SCR_CPOL_((mode & SPI_CPOL) != 0) |
+                    QSPI_SCR_CPHA_((mode & SPI_CPHA) != 0));
+       mask = (QSPI_SCR_CPOL | QSPI_SCR_CPHA);
+
+       scr = qspi_readl(aq, QSPI_SCR);
+       if ((scr & mask) == new_value)
+               return 0;
+
+       scr = (scr & ~mask) | new_value;
+       qspi_writel(aq, QSPI_SCR, scr);
+
+       return 0;
+}
+
+static bool
+atmel_qspi_is_flash_command_supported(struct udevice *dev,
+                                     const struct spi_flash_command *cmd)
+{
+       return true;
+}
+
+static int atmel_qspi_exec_flash_command(struct udevice *dev,
+                                        const struct spi_flash_command *cmd)
+{
+       struct udevice *bus = dev_get_parent(dev);
+       struct atmel_qspi_priv *aq = dev_get_priv(bus);
+       unsigned int iar, icr, ifr;
+       unsigned int offset;
+       unsigned int imr, sr;
+       unsigned long memaddr;
+       int err;
+
+       iar = 0;
+       icr = 0;
+       ifr = 0;
+
+       err = atmel_qspi_set_ifr_tfrtype(cmd->flags, &ifr);
+       if (err)
+               return err;
+
+       err = atmel_qpsi_set_ifr_width(cmd->proto, &ifr);
+       if (err)
+               return err;
+
+       /* Compute instruction parameters */
+       icr |= QSPI_ICR_INST_(cmd->inst);
+       ifr |= QSPI_IFR_INSTEN;
+
+       /* Compute address parameters. */
+       switch (cmd->addr_len) {
+       case 4:
+               ifr |= QSPI_IFR_ADDRL_32_BIT;
+               /*break;*/ /* fall through the 24bit (3 byte) address case */
+       case 3:
+               iar = cmd->data_len ? 0 : cmd->addr;
+               ifr |= QSPI_IFR_ADDREN;
+               offset = cmd->addr;
+               break;
+       case 0:
+               offset = 0;
+               break;
+       default:
+               return -EINVAL;
+       }
+
+       /* Compute option parameters. */
+       if (cmd->num_mode_cycles) {
+               unsigned int mode_cycle_bits, mode_bits;
+
+               icr |= QSPI_ICR_OPT_(cmd->mode);
+               ifr |= QSPI_IFR_OPTEN;
+
+               switch (ifr & QSPI_IFR_WIDTH) {
+               case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
+               case QSPI_IFR_WIDTH_DUAL_OUTPUT:
+               case QSPI_IFR_WIDTH_QUAD_OUTPUT:
+                       mode_cycle_bits = 1;
+                       break;
+               case QSPI_IFR_WIDTH_DUAL_IO:
+               case QSPI_IFR_WIDTH_DUAL_CMD:
+                       mode_cycle_bits = 2;
+                       break;
+               case QSPI_IFR_WIDTH_QUAD_IO:
+               case QSPI_IFR_WIDTH_QUAD_CMD:
+                       mode_cycle_bits = 4;
+                       break;
+               default:
+                       return -EINVAL;
+               }
+
+               mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
+               switch (mode_bits) {
+               case 1:
+                       ifr |= QSPI_IFR_OPTL_1BIT;
+                       break;
+
+               case 2:
+                       ifr |= QSPI_IFR_OPTL_2BIT;
+                       break;
+
+               case 4:
+                       ifr |= QSPI_IFR_OPTL_4BIT;
+                       break;
+
+               case 8:
+                       ifr |= QSPI_IFR_OPTL_8BIT;
+                       break;
+
+               default:
+                       return -EINVAL;
+               }
+       }
+
+       /* Set the number of dummy cycles. */
+       if (cmd->num_wait_states)
+               ifr |= QSPI_IFR_NBDUM_(cmd->num_wait_states);
+
+       /* Set data enable. */
+       if (cmd->data_len)
+               ifr |= QSPI_IFR_DATAEN;
+
+       /* Clear pending interrupts. */
+       (void)qspi_readl(aq, QSPI_SR);
+
+       /* Set QSPI Instruction Frame registers. */
+       qspi_writel(aq, QSPI_IAR, iar);
+       qspi_writel(aq, QSPI_ICR, icr);
+       qspi_writel(aq, QSPI_IFR, ifr);
+
+       /* Skip to the final steps if there is no data. */
+       if (!cmd->data_len)
+               goto no_data;
+
+       /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses. */
+       (void)qspi_readl(aq, QSPI_IFR);
+
+       /* Stop here for Continuous Read. */
+       memaddr = (unsigned long)(aq->membase + offset);
+       if (cmd->tx_data)
+               /* Write data. */
+               atmel_qspi_memcpy_toio(memaddr, cmd->tx_data, cmd->data_len);
+       else if (cmd->rx_data)
+               /* Read data. */
+               atmel_qspi_memcpy_fromio(cmd->rx_data, memaddr, cmd->data_len);
+
+       /* Release the chip-select. */
+       qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);

drivers/spi/atmel_qspi.c new file +85 -0

+
+
+static const struct dm_spi_ops atmel_qspi_ops = {
+       .xfer                           = atmel_qspi_xfer,
+       .set_speed                      = atmel_qspi_set_speed,
+       .set_mode                       = atmel_qspi_set_mode,
+       .is_flash_command_supported     = atmel_qspi_is_flash_command_supported,
+       .exec_flash_command             = atmel_qspi_exec_flash_command,
+};
+
+static int atmel_qspi_enable_clk(struct udevice *bus)
+{
+       struct atmel_qspi_priv *aq = dev_get_priv(bus);
+       struct clk clk;
+       ulong clk_rate;
+       int ret;
+
+       ret = clk_get_by_index(bus, 0, &clk);
+       if (ret)
+               return -EINVAL;
+
+       ret = clk_enable(&clk);
+       if (ret)
+               goto free_clock;
+
+       clk_rate = clk_get_rate(&clk);
+       if (!clk_rate) {
+               ret = -EINVAL;
+               goto free_clock;
+       }
+
+       aq->bus_clk_rate = clk_rate;
+
+free_clock:
+       clk_free(&clk);
+
+       return ret;
+}
+
+static int atmel_qspi_probe(struct udevice *bus)
+{
+       const struct atmel_qspi_platdata *plat = dev_get_platdata(bus);
+       struct atmel_qspi_priv *aq = dev_get_priv(bus);
+       u32 mr;
+       int ret;
+
+       ret = atmel_qspi_enable_clk(bus);
+       if (ret)
+               return ret;
+
+       aq->regbase = plat->regbase;
+       aq->membase = plat->membase;
+
+       /* Reset the QSPI controler */
+       qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
+
+       /* Set the QSPI controller in Serial Memory Mode */
+       mr = (QSPI_MR_NBBITS_8_BIT |
+             QSPI_MR_SMM_MEMORY |
+             QSPI_MR_CSMODE_LASTXFER);
+       qspi_writel(aq, QSPI_MR, mr);
+
+       /* Enable the QSPI controller */
+       qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
+
+       return 0;
+}
+
+static int atmel_qspi_ofdata_to_platdata(struct udevice *bus)
+{
+       struct atmel_qspi_platdata *plat = dev_get_platdata(bus);
+       const void *blob = gd->fdt_blob;
+       int node = dev_of_offset(bus);
+       u32 data[4];
+       int ret;
+
+       ret = fdtdec_get_int_array(blob, node, "reg", data, ARRAY_SIZE(data));
+       if (ret) {
+               printf("Error: Can't get base addresses (ret=%d)!\n", ret);
+               return -ENODEV;
+       }
+       plat->regbase = (void *)data[0];
+       plat->membase = (void *)data[2];
+
+       return 0;

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

  drivers/mtd/spi/Kconfig         |  16 +-
  drivers/mtd/spi/sf.c            |  78 ++++++--
  drivers/mtd/spi/sf_dataflash.c  | 119 ++++++------
  drivers/mtd/spi/sf_internal.h   |  48 +++--
  drivers/mtd/spi/spi_flash.c     | 341 +++++++++++++++++++++++----------
  drivers/mtd/spi/spi_flash_ids.c |   5 +
  drivers/spi/Kconfig             |   7 +
  drivers/spi/Makefile            |   1 +
  drivers/spi/atmel_qspi.c        | 404 ++++++++++++++++++++++++++++++++++++++++
  drivers/spi/atmel_qspi.h        | 169 +++++++++++++++++
  drivers/spi/spi-uclass.c        |  40 ++++
  drivers/spi/spi.c               |  13 ++
  include/spi.h                   | 168 +++++++++++++++++
  include/spi_flash.h             |   7 +
  14 files changed, 1226 insertions(+), 190 deletions(-)

create mode 100644 drivers/spi/atmel_qspi.c
create mode 100644 drivers/spi/atmel_qspi.h

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

  drivers/mtd/spi/Kconfig         |  16 +-
  drivers/mtd/spi/sf.c            |  78 ++++++--
  drivers/mtd/spi/sf_dataflash.c  | 119 ++++++------
  drivers/mtd/spi/sf_internal.h   |  48 +++--
  drivers/mtd/spi/spi_flash.c     | 341 +++++++++++++++++++++++----------
  drivers/mtd/spi/spi_flash_ids.c |   5 +
  drivers/spi/Kconfig             |   7 +
  drivers/spi/Makefile            |   1 +
  drivers/spi/atmel_qspi.c        | 404 ++++++++++++++++++++++++++++++++++++++++
  drivers/spi/atmel_qspi.h        | 169 +++++++++++++++++
  drivers/spi/spi-uclass.c        |  40 ++++
  drivers/spi/spi.c               |  13 ++
  include/spi.h                   | 168 +++++++++++++++++
  include/spi_flash.h             |   7 +
  14 files changed, 1226 insertions(+), 190 deletions(-)

create mode 100644 drivers/spi/atmel_qspi.c
create mode 100644 drivers/spi/atmel_qspi.h

Hi All,

Do you have some comment on it?

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

  drivers/mtd/spi/Kconfig         |  16 +-
  drivers/mtd/spi/sf.c            |  78 ++++++--
  drivers/mtd/spi/sf_dataflash.c  | 119 ++++++------
  drivers/mtd/spi/sf_internal.h   |  48 +++--
  drivers/mtd/spi/spi_flash.c     | 341 +++++++++++++++++++++++----------
  drivers/mtd/spi/spi_flash_ids.c |   5 +
  drivers/spi/Kconfig             |   7 +
  drivers/spi/Makefile            |   1 +
  drivers/spi/atmel_qspi.c        | 404 ++++++++++++++++++++++++++++++++++++++++
  drivers/spi/atmel_qspi.h        | 169 +++++++++++++++++
  drivers/spi/spi-uclass.c        |  40 ++++
  drivers/spi/spi.c               |  13 ++
  include/spi.h                   | 168 +++++++++++++++++
  include/spi_flash.h             |   7 +
  14 files changed, 1226 insertions(+), 190 deletions(-)

create mode 100644 drivers/spi/atmel_qspi.c
create mode 100644 drivers/spi/atmel_qspi.h

Hi,

This patch set has been here for a long time, could you have a look and take it?

Quoted 4 lines · Wenyou

Hi,

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Quoted 6 lines · Jagan Teki

Quoted 4 lines · Wenyou

Hi,

This patch set has been here for a long time, could you have a look and take it?

Quoted 2 lines

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

Quoted 4 lines · Marek Vasut

Quoted 3 lines · Jagan Teki

Quoted 2 lines · Wenyou

Hi,

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

Quoted 3 lines

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

I didn't write "this series holding spi-nor work" since it has some new features I'm taking time to review.

There is nothing wrong with
maintainer duties here, you must need to understand.

Quoted 5 lines · Jagan Teki

Quoted 4 lines · Marek Vasut

Quoted 3 lines · Jagan Teki

Quoted 2 lines · Wenyou

Hi,

Quoted 7 lines

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

You did not answer this question.

Quoted 6 lines

Quoted 3 lines

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

I didn't write "this series holding spi-nor work" since it has some new features I'm taking time to review.

I never implied this. Rather the opposite, you claim you do some work on the SPI NOR core, yet you let this patchset rot in the list for over a month now and gave the author zero feedback.

Notifying the author about the core changes early could've prevented a lot of wasted effort on his side. Reviewing early could've prevented a lot of frustration from patches being ignored.

Quoted 2 lines

There is nothing wrong with
maintainer duties here, you must need to understand.

I disagree.

Quoted 31 lines · Marek Vasut

Quoted 5 lines · Jagan Teki

Quoted 4 lines · Marek Vasut

Quoted 3 lines · Jagan Teki

Quoted 2 lines · Wenyou

Hi,

Quoted 7 lines

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

You did not answer this question.

Quoted 6 lines

Quoted 3 lines

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

I didn't write "this series holding spi-nor work" since it has some new features I'm taking time to review.

I never implied this. Rather the opposite, you claim you do some work on the SPI NOR core, yet you let this patchset rot in the list for over a month now and gave the author zero feedback.

Notifying the author about the core changes early could've prevented a lot of wasted effort on his side. Reviewing early could've prevented a lot of frustration from patches being ignored.

Quoted 5 lines

Quoted 2 lines

There is nothing wrong with
maintainer duties here, you must need to understand.

I disagree.

I agree with Marek here. I found it's really hard to get feedback for SF patches in time and what I have to do is to ping again and again.

Quoted 38 lines · Bin Meng

Quoted 36 lines · Marek Vasut

Quoted 5 lines · Jagan Teki

Quoted 4 lines · Marek Vasut

Quoted 3 lines · Jagan Teki

Quoted 2 lines · Wenyou

Hi,

Quoted 7 lines

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

You did not answer this question.

Quoted 6 lines

Quoted 3 lines

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

I didn't write "this series holding spi-nor work" since it has some new features I'm taking time to review.

I never implied this. Rather the opposite, you claim you do some work on the SPI NOR core, yet you let this patchset rot in the list for over a month now and gave the author zero feedback.

Notifying the author about the core changes early could've prevented a lot of wasted effort on his side. Reviewing early could've prevented a lot of frustration from patches being ignored.

Quoted 2 lines

There is nothing wrong with
maintainer duties here, you must need to understand.

I disagree.

Quoted 2 lines

I agree with Marek here. I found it's really hard to get feedback for SF patches in time and what I have to do is to ping again and again.

I agree that the SF side patches have got some delay recently, but ie something not intentional. SF stack is not stable as of now, so I'm working on SPI-NOR (v10)[1] the new patches for SF need to wait - please be patient.

[1] http://git.denx.de/?p=u-boot-spi.git;a=shortlog;h=refs/heads/mtd-spinor

thanks!

Quoted 39 lines · Jagan Teki

Quoted 38 lines · Bin Meng

Quoted 36 lines · Marek Vasut

Quoted 5 lines · Jagan Teki

Quoted 4 lines · Marek Vasut

Quoted 3 lines · Jagan Teki

Quoted 2 lines · Wenyou

Hi,

Quoted 7 lines

Quoted 7 lines

Quoted 5 lines

Quoted 2 lines

This patch set has been here for a long time, could you have a look and take it?

Yeah, I'm holding this because of my current spi-nor work. But anyway I will try to merge on coming MW If all OK.

Is your work posted somewhere or available in some git repository ?

You did not answer this question.

Quoted 6 lines

Quoted 3 lines

I don't see any reason why you should not perform your maintainer duties by reviewing/replying to an incoming patch, no matter what work you do to the subsystem though ...

I didn't write "this series holding spi-nor work" since it has some new features I'm taking time to review.

I never implied this. Rather the opposite, you claim you do some work on the SPI NOR core, yet you let this patchset rot in the list for over a month now and gave the author zero feedback.

Notifying the author about the core changes early could've prevented a lot of wasted effort on his side. Reviewing early could've prevented a lot of frustration from patches being ignored.

Quoted 2 lines

There is nothing wrong with
maintainer duties here, you must need to understand.

I disagree.

Quoted 7 lines

Quoted 2 lines

I agree with Marek here. I found it's really hard to get feedback for SF patches in time and what I have to do is to ping again and again.

I agree that the SF side patches have got some delay recently, but ie something not intentional. SF stack is not stable as of now, so I'm working on SPI-NOR (v10)[1] the new patches for SF need to wait - please be patient.

What are the problems with the stack causing this instability ?

How do you plan to stabilize the stack for the current release ?

Given how complex and incomplete this patch(set) [1] is and that it's already in v10, it seems it will take a while to get it into shape in which it can be included in mainline. Blocking all other contributions because of this patchset seems wrong and hurtful to the contributors to me.

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Hi,

Thanks for the changes.

Quoted 49 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 9 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]
bool above_16MB;

        ^~~~~~~~~~

CC spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

drivers/mtd/spi/spi_flash.c +3 -1

index 89ceae2..b5d8ef3 100644
@@ -558,13 +558,15 @@ int spi_flash_cmd_read_ops(struct spi_flashmake
 *flash, u32 offset,
          if (ret < 0)
              return ret;
          bank_sel = flash->bank_curr;
-#endif
          remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
                  (bank_sel + 1)) - offset;
          if (len < remain_len)
              read_len = len;
          else
              read_len = remain_len;
+#else
+        read_len = len;
+#endif
 
          cmd.addr = read_addr;

          cmd.data_len = read_len;

thanks!

Hi Jagan,

Quoted 67 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 50 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 9 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Quoted 4 lines

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

The spi_flash_command struct describes the relevant features of the spi controller, instead of the spi_flash device.
The purpose of patch set is used to supersede the spi_xfer() function to access the spi_flash device.
So putting it in include/spi.h is suitable, we should not move it in the spi_flash area.

Moreover, why do we write atmel_qspi with UCLASS_SPI_FLASH? It is not easy to understand.

Hi,

Thanks for the changes.

Quoted 49 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 9 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

   bool above_16MB;
        ^~~~~~~~~~

CC spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

drivers/mtd/spi/spi_flash.c +3 -1

index 89ceae2..b5d8ef3 100644
@@ -558,13 +558,15 @@ int spi_flash_cmd_read_ops(struct spi_flash
 *flash, u32 offset,
          if (ret < 0)
              return ret;
          bank_sel = flash->bank_curr;
-#endif
          remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
                  (bank_sel + 1)) - offset;
          if (len < remain_len)
              read_len = len;
          else
              read_len = remain_len;
+#else
+        read_len = len;
+#endif
 
          cmd.addr = read_addr;

          cmd.data_len = read_len;

thanks!

Quoted 84 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 50 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 9 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

   bool above_16MB;
        ^~~~~~~~~~

CC spl/lib/membuff.o

Quoted 5 lines

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

Will You send a separate patch? or I include it in this patch set?

Quoted 1 line

Quoted 20 lines

drivers/mtd/spi/spi_flash.c +3 -1

index 89ceae2..b5d8ef3 100644
@@ -558,13 +558,15 @@ int spi_flash_cmd_read_ops(struct spi_flash
 *flash, u32 offset,
          if (ret < 0)
              return ret;
          bank_sel = flash->bank_curr;
-#endif
          remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
                  (bank_sel + 1)) - offset;
          if (len < remain_len)
              read_len = len;
          else
              read_len = remain_len;
+#else
+        read_len = len;
+#endif
 

Quoted 3 lines

drivers/mtd/spi/spi_flash.c +0 -0

          cmd.addr = read_addr;

          cmd.data_len = read_len;

Quoted 83 lines · Wenyou

Quoted 81 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 49 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't know why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 9 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

    bool above_16MB;
         ^~~~~~~~~~
    CC      spl/lib/membuff.o

Quoted 6 lines

Quoted 5 lines

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

Quoted 21 lines

Quoted 21 lines

drivers/mtd/spi/spi_flash.c +3 -1

index 89ceae2..b5d8ef3 100644
@@ -558,13 +558,15 @@ int spi_flash_cmd_read_ops(struct spi_flash
 *flash, u32 offset,
           if (ret < 0)
               return ret;
           bank_sel = flash->bank_curr;
-#endif
           remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
                   (bank_sel + 1)) - offset;
           if (len < remain_len)
               read_len = len;
           else
               read_len = remain_len;
+#else
+        read_len = len;
+#endif
 

Quoted 3 lines

Quoted 3 lines

drivers/mtd/spi/spi_flash.c +0 -0

           cmd.addr = read_addr;

           cmd.data_len = read_len;

Regards,
Bin

Quoted 100 lines · Bin Meng

Quoted 97 lines · Wenyou

Quoted 93 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 52 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and
QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't
know

      why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 10 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write
commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

    bool above_16MB;
         ^~~~~~~~~~
    CC      spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

Quoted 4 lines

Quoted 1 line

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

But it is not introduced by this patch set. So should be a separate patch to fix.

Quoted 95 lines · Wenyou

Quoted 93 lines · Bin Meng

Quoted 91 lines · Wenyou

Quoted 89 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 51 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and
QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't
know

       why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 10 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write
commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

     bool above_16MB;
          ^~~~~~~~~~
     CC      spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Quoted 6 lines

Quoted 4 lines

Quoted 2 lines

Quoted 1 line

Will send separate patch for this.

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

But it is not introduced by this patch set. So should be a separate patch to fix.

Do you mean the build warnings exist in current u-boot/master?

If so, Jagan can you please explain why you mention this? This is nothing related to this patch review.

Regards,
Bin

Quoted 108 lines · Wenyou

Quoted 104 lines · Bin Meng

Quoted 91 lines · Wenyou

Quoted 88 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 52 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and
QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't
know

      why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 10 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write
commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

    bool above_16MB;
         ^~~~~~~~~~
    CC      spl/lib/membuff.o

Quoted 7 lines

Quoted 5 lines

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

Quoted 2 lines

But it is not introduced by this patch set. So should be a separate patch to fix.

Do you mean the build warnings exist in current u-boot/master?

If so, Jagan can you please explain why you mention this? This is nothing related to this patch review.

Hi Bin,

Quoted 112 lines · Bin Meng

Quoted 110 lines · Wenyou

Quoted 98 lines · Bin Meng

Quoted 95 lines · Wenyou

Quoted 92 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 52 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and
QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't
know

      why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 10 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write
commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

    bool above_16MB;
         ^~~~~~~~~~
    CC      spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Quoted 6 lines

Quoted 3 lines

Quoted 1 line

Will send separate patch for this.

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

But it is not introduced by this patch set. So should be a separate patch to fix.

Quoted 4 lines

Do you mean the build warnings exist in current u-boot/master?

If so, Jagan can you please explain why you mention this? This is nothing related to this patch review.

Please read my previous comments, I was clearly explain the issue and diff. Issue came up this series with 4BAIS on spi_flash_cmd_read_ops

Hi Jagan,

Quoted 120 lines · Jagan Teki

Hi Bin,

Quoted 116 lines · Bin Meng

Quoted 103 lines · Wenyou

Quoted 100 lines · Bin Meng

Quoted 97 lines · Wenyou

Quoted 93 lines · Jagan Teki

Hi,

Thanks for the changes.

Quoted 52 lines · Wenyou Yang

This series of patches are based and have been tested on the 'master' branch of the u-boot.git tree.

Tests were passed with a sama5d2 xplained board which embeds both SPI and
QSPI controllers.

The following tests have been passed:

- QSPI0 + Macronix MX25L25673G:
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-4 at offset 0x10000: OK
The Macronix datasheet tells that only Page Program 1-4-4 is supported, not Page Program 1-1-4, however it worked, I don't
know

      why...

- QSPI0 + Microchip SST26
+ probe: OK
+ Fast Read 1-1-4 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK
SST26 memories support Page Program 1-4-4 but with the op code of Page Program 1-1-4, which is not standard so I don't use it.

- QSPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x10000 (u-boot env): OK
+ Page Program 1-1-1 at offset 0x10000: OK

- SPI0 + Adesto AT25DF321A
+ probe: OK
+ Fast Read 1-1-1 at offset 0x6000 (u-boot env): OK
+ Page Program 1-1-1 at offest 0x6000: OK

- SPI1 + Atmel AT45
+ probe: OK
+ Read at offset 0 and other than 0: OK
+ Write at offset 0 and other than 0: OK

During my tests, I used:
- setenv/saveenv, reboot, printenv
or
- sf probe, sf read, sf write, sf erase and sf update.

Changes in v3:
- Add the include <spi.h> to fix build error for corvus_defconfig.

Changes in v2:
- Rebase on the latest u-boot/master(2710d54f5).

Quoted 10 lines

Cyrille Pitchen (8):
spi: add support of SPI flash commands
sf: describe all SPI flash commands with 'struct spi_flash_command'
sf: select the relevant SPI flash protocol for read and write
commands
sf: differentiate Page Program 1-1-4 and 1-4-4
sf: add 'addr_len' member to 'struct spi_flash'
sf: add new option to support SPI flash above 16MiB
sf: add support to Microchip SST26 QSPI memories
sf: add driver for Atmel QSPI controller

Comments:
How about writing struct spi_flash_command in spi_flash area (include/spi_flash.h)? and then write atmel_qspi with UCLASS_SPI_FLASH?

Testing:
Basic testing works fine.

Issues:
- Build issue: with zynq_microzed_defconfig drivers/mtd/spi/spi_flash.c: In function ‘spi_flash_scan’:
drivers/mtd/spi/spi_flash.c:1049:7: warning: variable ‘above_16MB’ set but not used [-Wunused-but-set-variable]

    bool above_16MB;
         ^~~~~~~~~~
    CC      spl/lib/membuff.o

- issue with spi_flash_cmd_read_ops 4BAIS
Need to calculate bank length only if BAR is in use. Otherwise, consider the given len as read_len.

Will send separate patch for this.

Quoted 7 lines

Quoted 4 lines

Quoted 1 line

Will You send a separate patch? or I include it in this patch set?

This should not be a separate patch. Since every patch needs to pass buildman testing.

But it is not introduced by this patch set. So should be a separate patch to fix.

Do you mean the build warnings exist in current u-boot/master?

If so, Jagan can you please explain why you mention this? This is nothing related to this patch review.