arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses

PATCH In review Alexey Brodkin 2 participants 4 messages Aug 1, 2017 – Aug 2, 2017 Synopsys ARC architecture

Share & tools

Alexey Brodkin

author

2017-08-01 09:58 UTC #0 lore raw

PATCH 1/1 arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses

It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner, for example on HSDK platform where PAE40 support exists in hardware we saw each and every SLC region op to take seconds (sic!).

Signed-off-by Alexey Brodkin <abrodkin at synopsys.com>

Reported-by Vladimir Kondratiev <vladimir.kondratiev at intel.com>

---
 arch/arc/include/asm/cache.h | 2 ++
 arch/arc/mm/cache.c          | 8 ++++++--
 2 files changed, 8 insertions(+), 2 deletions(-)

arch/arc/include/asm/cache.h +2 -0

index 35127ad95124..1f3c2f967471 100644
@@ -91,7 +91,9 @@ extern unsigned long perip_base, perip_end;
 #define ARC_REG_SLC_FLUSH	0x904
 #define ARC_REG_SLC_INVALIDATE	0x905
 #define ARC_REG_SLC_RGN_START	0x914
+#define ARC_REG_SLC_RGN_START1	0x915
 #define ARC_REG_SLC_RGN_END	0x916
+#define ARC_REG_SLC_RGN_END1	0x917
 
 /* Bit val in SLC_CONTROL */
 #define SLC_CTRL_DIS		0x001

arch/arc/mm/cache.c +6 -2

index b7a1face1584..0b4e2650c5de 100644
@@ -580,6 +580,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 	static DEFINE_SPINLOCK(lock);
 	unsigned long flags;
 	unsigned int ctrl;
+	phys_addr_t end;
 
 	spin_lock_irqsave(&lock, flags);

@@ -609,8 +610,11 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 	 * END needs to be setup before START (latter triggers the operation)
 	 * END can't be same as START, so add (l2_line_sz - 1) to sz
 	 */
-	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
-	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+	end = paddr + sz + l2_line_sz - 1;
+	write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
 
 	/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
 	read_aux_reg(ARC_REG_SLC_CTRL);

Signature · 1 line

2.11.0

Vineet Gupta

2017-08-02 03:39 UTC #1 lore raw

Quoted 40 lines · Alexey Brodkin

It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner, for example on HSDK platform where PAE40 support exists in hardware we saw each and every SLC region op to take seconds (sic!).
Signed-off-by Alexey Brodkin <abrodkin at synopsys.com>
Reported-by Vladimir Kondratiev <vladimir.kondratiev at intel.com>
---
  arch/arc/include/asm/cache.h | 2 ++
  arch/arc/mm/cache.c          | 8 ++++++--
  2 files changed, 8 insertions(+), 2 deletions(-)
arch/arc/include/asm/cache.h +2 -0
index 35127ad95124..1f3c2f967471 100644
@@ -91,7 +91,9 @@ extern unsigned long perip_base, perip_end;
  #define ARC_REG_SLC_FLUSH	0x904
  #define ARC_REG_SLC_INVALIDATE	0x905
  #define ARC_REG_SLC_RGN_START	0x914
+#define ARC_REG_SLC_RGN_START1	0x915
  #define ARC_REG_SLC_RGN_END	0x916
+#define ARC_REG_SLC_RGN_END1	0x917
 
  /* Bit val in SLC_CONTROL */
  #define SLC_CTRL_DIS		0x001
arch/arc/mm/cache.c +1 -0
index b7a1face1584..0b4e2650c5de 100644
@@ -580,6 +580,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
  	static DEFINE_SPINLOCK(lock);
  	unsigned long flags;
  	unsigned int ctrl;
+	phys_addr_t end;
 
  	spin_lock_irqsave(&lock, flags);
 

arch/arc/mm/cache.c noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · line 617

Quoted 10 lines

arch/arc/mm/cache.c +5 -2

@@ -609,8 +610,11 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
  	 * END needs to be setup before START (latter triggers the operation)
  	 * END can't be same as START, so add (l2_line_sz - 1) to sz
  	 */
-	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
-	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+	end = paddr + sz + l2_line_sz - 1;
+	write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));

Are these registers present even if PAE is not configured in hardware ?

Quoted 3 lines

arch/arc/mm/cache.c +0 -0

  	/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
  	read_aux_reg(ARC_REG_SLC_CTRL);

Alexey Brodkin

author

2017-08-02 08:03 UTC #2 lore raw

Hi Vineet,

Quoted 46 lines · Vineet Gupta

Quoted 45 lines · Alexey Brodkin
It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner, for example on HSDK platform where PAE40 support exists in hardware we saw each and every SLC region op to take seconds (sic!).
Signed-off-by Alexey Brodkin <abrodkin at synopsys.com>
Reported-by Vladimir Kondratiev <vladimir.kondratiev at intel.com>
---
? arch/arc/include/asm/cache.h | 2 ++
? arch/arc/mm/cache.c??????????| 8 ++++++-- ? 2 files changed, 8 insertions(+), 2 deletions(-)
arch/arc/include/asm/cache.h +0 -0
index 35127ad95124..1f3c2f967471 100644
@@ -91,7 +91,9 @@ extern unsigned long perip_base, perip_end;
? #define ARC_REG_SLC_FLUSH 0x904
? #define ARC_REG_SLC_INVALIDATE 0x905
? #define ARC_REG_SLC_RGN_START 0x914
+#define ARC_REG_SLC_RGN_START1 0x915
? #define ARC_REG_SLC_RGN_END 0x916
+#define ARC_REG_SLC_RGN_END1 0x917
??
? /* Bit val in SLC_CONTROL */
? #define SLC_CTRL_DIS 0x001
arch/arc/mm/cache.c +1 -0
index b7a1face1584..0b4e2650c5de 100644
@@ -580,6 +580,7 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 ??	static DEFINE_SPINLOCK(lock);
 ??	unsigned long flags;
 ??	unsigned int ctrl;
+	phys_addr_t end;
??
?? spin_lock_irqsave(&lock, flags);
??
arch/arc/mm/cache.c +0 -0
@@ -609,8 +610,11 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
 ??	?* END needs to be setup before START (latter triggers the operation)
?? ?* END can't be same as START, so add (l2_line_sz - 1) to sz
?? ?*/
arch/arc/mm/cache.c +0 -1
-	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));

Quoted 8 lines

arch/arc/mm/cache.c noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · line 617
Quoted 6 lines
arch/arc/mm/cache.c +5 -1
-	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+	end = paddr + sz + l2_line_sz - 1;
+	write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
Are these registers present even if PAE is not configured in hardware ?

Apparently no :(

I did test it on AXS103 but just now realized its latest firmware has PAE40. Retested on older firmware (still with HS 2.1) without PAE and indeed those AUX registers are not implemented:
----------------------->8----------------------
ehci-platform e0040000.ehci: new USB bus registered, assigned bus number 1
Path: (null)

CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.13.0-rc1-next-20170718-00001-g6f0be43cd25b-dirty #1

task: 9f02ba80 task.stack: 9f02c000

[ECR???]: 0x00020000 => Illegal Insn
[EFA???]: 0x8020bba2
[BLINK ]: slc_op+0x1a/0xac
[ERET??]: slc_op+0x4a/0xac
[STAT32]: 0x00080802 :???K?????
BTA: 0x8020bb80??SP: 0x9f02dd88??FP: 0x00000000
LPS: 0x80670da4 LPE: 0x80670db8 LPC: 0x00000000
r00: 0x00000031 r01: 0x00002000 r02: 0x9f38403f
r03: 0x00000917 r04: 0x00000031 r05: 0x9f38a5c0
r06: 0x9f0baf0d r07: 0x9f0baf0c r08: 0x00000000
r09: 0x00000000 r10: 0x00000000 r11: 0x80808080
r12: 0x8020bb72

Stack Trace:

? slc_op+0x4a/0xac
? arc_dma_alloc+0x7c/0xd8
? dma_pool_alloc+0x186/0x1d0
? ehci_qh_alloc+0x34/0xd4
? ehci_setup+0x15c/0x420
? ehci_platform_reset+0x48/0x68
? usb_add_hcd+0x186/0x624
? ehci_platform_probe+0x210/0x514
? platform_drv_probe+0x26/0x64
? really_probe+0x284/0x348
? __driver_attach+0xac/0xd4
? bus_for_each_dev+0x38/0x70
? bus_add_driver+0xc0/0x180
? driver_register+0x50/0xec
? do_one_initcall+0x32/0x118
? kernel_init_freeable+0x108/0x198

----------------------->8----------------------

So I'll respin this patch with conditional setup of those regs depending on PAE40 presence.

-Alexey

Vineet Gupta

2017-08-02 08:26 UTC #3 lore raw

Quoted 11 lines · Alexey Brodkin

Quoted 9 lines
arch/arc/mm/cache.c noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op) · line 617
Quoted 8 lines
arch/arc/mm/cache.c +5 -2
-	write_aux_reg(ARC_REG_SLC_RGN_END, (paddr + sz + l2_line_sz - 1));
-	write_aux_reg(ARC_REG_SLC_RGN_START, paddr);
+	end = paddr + sz + l2_line_sz - 1;
+	write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
+	write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
+	write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
Are these registers present even if PAE is not configured in hardware ?
Apparently no :(

Quoted 8 lines

I did test it on AXS103 but just now realized its latest firmware has PAE40. Retested on older firmware (still with HS 2.1) without PAE and indeed those AUX registers are not implemented:
----------------------->8----------------------
...
So I'll respin this patch with conditional setup of those regs depending on PAE40 presence.

And please also do another patch which converts the existing is_pae40_enabled() calls to is_pae40_exists() or somesuch, as apparently these regs needs to be cleared if hw has PAE and kernel not using PAE is immaterial.