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drm/i915: Speed up DMC firmware loading

PATCH Superseded David Weinehall 4 participants 5 messages Sep 1, 2017

Subsystems (2)
DRM drivers Intel i915

v1 of 4 Superseded Latest is v4 →

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David Weinehall

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#0 lore raw

PATCH 1/1 drm/i915: Speed up DMC firmware loading

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +14 -1
index 965988f79a55..b7a6ef7e0d53 100644
@@ -239,7 +239,9 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
 	u32 *payload = dev_priv->csr.dmc_payload;
+	enum forcewake_domains fw_domains;
 	uint32_t i, fw_size;
+	unsigned long flags;
 
 	if (!HAS_CSR(dev_priv)) {
 		DRM_ERROR("No CSR support available for this platform\n");

@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
 		return;
 	}
 
+	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+						    CSR_PROGRAM(0),
+						    FW_REG_WRITE);
+
 	fw_size = dev_priv->csr.dmc_fw_size;
+	assert_rpm_wakelock_held(dev_priv);
+	spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
+
 	for (i = 0; i < fw_size; i++)
-		I915_WRITE(CSR_PROGRAM(i), payload[i]);
+		I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);
 
 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 		I915_WRITE(dev_priv->csr.mmioaddr[i],
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2.14.1

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#1 lore raw

Quoting David Weinehall (2017-09-01 15:01:17)

Quoted 35 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +2 -0
index 965988f79a55..b7a6ef7e0d53 100644
@@ -239,7 +239,9 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
        u32 *payload = dev_priv->csr.dmc_payload;
+       enum forcewake_domains fw_domains;
        uint32_t i, fw_size;
+       unsigned long flags;
 
        if (!HAS_CSR(dev_priv)) {
                DRM_ERROR("No CSR support available for this platform\n");

@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
                return;

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 263

Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +7 -0
        }
 
+       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+                                                   CSR_PROGRAM(0),
+                                                   FW_REG_WRITE);
+
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);

One thing to note is that this platform doesn't have the concurrent mmio bug, so we can allow others to run concurrently:

if (fw_domains)

	intel_uncore_forcewake_get(dev_priv, fw_domains);

And I'm pretty confident that fw_domains is 0 here.

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 269

Quoted 7 lines
drivers/gpu/drm/i915/intel_csr.c +5 -1
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);

if (fw_domains)

	intel_uncore_forcewake_put(dev_priv, fw_domains);
Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +0 -0
        for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                I915_WRITE(dev_priv->csr.mmioaddr[i],
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#2 lore raw
Quoted 50 lines · Chris Wilson

Quoting David Weinehall (2017-09-01 15:01:17)

Quoted 35 lines

Currently we're doing:

1. acquire lock
2. write word to hardware
3. release lock
4. repeat from 1

to load the DMC firmware. Due to the cost of acquiring/releasing a lock, and the size of the DMC firmware, this slows down DMC loading a lot.

This patch simply acquires the lock, writes the entire firmware, then releases the lock. Testing shows resume speedups in the order of 10ms on platforms with DMC firmware (GEN9+).

Signed-off-by David Weinehall <[email protected]>
---
 drivers/gpu/drm/i915/intel_csr.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/intel_csr.c +2 -0
index 965988f79a55..b7a6ef7e0d53 100644
@@ -239,7 +239,9 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 {
        u32 *payload = dev_priv->csr.dmc_payload;
+       enum forcewake_domains fw_domains;
        uint32_t i, fw_size;
+       unsigned long flags;
 
        if (!HAS_CSR(dev_priv)) {
                DRM_ERROR("No CSR support available for this platform\n");

@@ -251,9 +253,20 @@ void intel_csr_load_program(struct drm_i915_private *dev_priv)
                return;

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 263

Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +7 -0
        }
 
+       fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
+                                                   CSR_PROGRAM(0),
+                                                   FW_REG_WRITE);
+
        fw_size = dev_priv->csr.dmc_fw_size;
+       assert_rpm_wakelock_held(dev_priv);
+       spin_lock_irqsave(&dev_priv->uncore.lock, flags);
+       intel_uncore_forcewake_get__locked(dev_priv, fw_domains);

One thing to note is that this platform doesn't have the concurrent mmio bug, so we can allow others to run concurrently:

Quoted 4 lines

if (fw_domains)

	intel_uncore_forcewake_get(dev_priv, fw_domains);

And I'm pretty confident that fw_domains is 0 here.

Yes, CSR_PROGRAM is 0x80000+ and all forcewake registers are below 0x40000, so we can omit the fw dance here as well.

Quoted 26 lines

drivers/gpu/drm/i915/intel_csr.c void intel_csr_load_program(struct drm_i915_private *dev_priv) · line 269

Quoted 8 lines
drivers/gpu/drm/i915/intel_csr.c +5 -1
+
        for (i = 0; i < fw_size; i++)
-               I915_WRITE(CSR_PROGRAM(i), payload[i]);
+               I915_WRITE_FW(CSR_PROGRAM(i), payload[i]);
+
+       intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
+       spin_unlock_irqrestore(&dev_priv->uncore.lock, flags);

if (fw_domains)

	intel_uncore_forcewake_put(dev_priv, fw_domains);
Quoted 10 lines
drivers/gpu/drm/i915/intel_csr.c +0 -0
        for (i = 0; i < dev_priv->csr.mmio_count; i++) {
                I915_WRITE(dev_priv->csr.mmioaddr[i],
Signature · 6 lines
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Signature · 6 lines
Ville Syrjälä
Intel OTC
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CI
#3 lore raw

✓ Fi.CI.BAT: success for drm/i915: Speed up DMC firmware loading

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading
URL : https://patchwork.freedesktop.org/series/29688/
State : success

== Summary ==

Series 29688v1 drm/i915: Speed up DMC firmware loading
https://patchwork.freedesktop.org/api/1.0/series/29688/revisions/1/mbox/

Test kms_cursor_legacy:

        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215

fi-bdw-5557u     total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:456s
fi-bdw-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:441s
fi-blb-e6850     total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  time:363s
fi-bsw-n3050     total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  time:557s
fi-bwr-2160      total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 time:257s
fi-bxt-j4205     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:518s
fi-byt-j1900     total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  time:530s
fi-byt-n2820     total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  time:515s
fi-elk-e7500     total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  time:441s
fi-glk-2a        total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:609s
fi-hsw-4770      total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:451s
fi-hsw-4770r     total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:425s
fi-ilk-650       total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:425s
fi-ivb-3520m     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:507s
fi-ivb-3770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:480s
fi-kbl-7500u     total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  time:517s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:598s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:605s
fi-pnv-d510      total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:526s
fi-skl-6260u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:478s
fi-skl-6700k     total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:541s
fi-skl-6770hq    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:488s
fi-skl-gvtdvm    total:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  time:444s
fi-skl-x1585l    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:492s
fi-snb-2520m     total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  time:549s
fi-snb-2600      total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  time:409s

8b962a9a16b3a4e3cc2a56cba82ee9c0dc0941b5 drm-tip: 2017y-09m-01d-13h-56m-06s UTC integration manifest eb9c2b9f1fdb drm/i915: Speed up DMC firmware loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5562/
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CI
#4 lore raw

✗ Fi.CI.IGT: warning for drm/i915: Speed up DMC firmware loading

In reply to David Weinehall
== Series Details ==

== Series Details ==

Series: drm/i915: Speed up DMC firmware loading
URL : https://patchwork.freedesktop.org/series/29688/
State : warning

== Summary ==

Test perf:

        Subgroup blocking:
                fail       -> PASS       (shard-hsw) fdo#102252
Test kms_busy:
        Subgroup extended-modeset-hang-newfb-with-reset-render-A:
                pass       -> DMESG-WARN (shard-hsw)
Test kms_plane:
        Subgroup plane-panning-bottom-right-suspend-pipe-B-planes:
                pass       -> SKIP       (shard-hsw)

fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw total:2218 pass:1206 dwarn:1 dfail:0 fail:13 skip:997 time:9347s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5562/shards.html
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