drm/amdgpu/pp: constify some powerplay tables
Subsystems (2)
PATCH 1/2 drm/amdgpu/pp: constify some powerplay tables
From: Dave Airlie <[email protected]>
Signed-off-by Dave Airlie <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +7 -7
@@ -312,37 +312,37 @@ static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, }/* temporary hardcoded clock voltage breakdown tables */ -DpmClock_t VddDcfClk[]= { +static const DpmClock_t VddDcfClk[]= { {300 ,2600 }, {600 ,3200 }, {600 ,3600 }, }; -DpmClock_t VddSocClk[]= { +static const DpmClock_t VddSocClk[]= { {478 ,2600 }, {722 ,3200 }, {722 ,3600 }, }; -DpmClock_t VddFClk[]= { +static const DpmClock_t VddFClk[]= { {400 ,2600 }, {1200 ,3200 }, {1200 ,3600 }, }; -DpmClock_t VddDispClk[]= { +static const DpmClock_t VddDispClk[]= { {435 ,2600 }, {661 ,3200 }, {1086 ,3600 }, }; -DpmClock_t VddDppClk[]= { +static const DpmClock_t VddDppClk[]= { {435 ,2600 }, {661 ,3200 }, {661 ,3600 }, }; -DpmClock_t VddPhyClk[]= { +static const DpmClock_t VddPhyClk[]= { {540 ,2600 }, {810 ,3200 }, {810 ,3600 },
@@ -350,7 +350,7 @@ DpmClock_t VddPhyClk[]= {static int rv_get_clock_voltage_dependency_table (struct pp_hwmgr *hwmgr,struct rv_voltage_dependency_table **pptable, -uint32_t num_entry,DpmClock_t *pclk_dependency_table) +uint32_t num_entry,const DpmClock_t *pclk_dependency_table) {uint32_t table_size, i;struct rv_voltage_dependency_table *ptable;
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 2/2 drm/amdgpu/vega10: static constify channel_number
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
Signed-off-by Dave Airlie <[email protected]>
--- drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c +1 -1
@@ -56,7 +56,7 @@#define HBM_MEMORY_CHANNEL_WIDTH 128 -uint32_t channel_number[] = {1 ,2 ,0 ,4 ,0 ,8 ,0 ,16 ,2 }; +static const uint32_t channel_number[] = {1 ,2 ,0 ,4 ,0 ,8 ,0 ,16 ,2 };#define MEM_FREQ_LOW_LATENCY 25000#define MEM_FREQ_HIGH_LATENCY 80000
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Alex Deucher
Reviewed-byQuoted 3 lines · Dave Airlie
From: Dave Airlie <[email protected]>
Signed-off-by Dave Airlie <[email protected]>
Series is:
Reviewed-by Alex Deucher <[email protected]>
Quoted 64 lines
--- drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c +7
-8@@ -312,37 +312,37 @@ static int rv_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, }/* temporary hardcoded clock voltage breakdown tables */ -DpmClock_t VddDcfClk[]= { +static const DpmClock_t VddDcfClk[]= { {300 ,2600 }, {600 ,3200 }, {600 ,3600 }, }; -DpmClock_t VddSocClk[]= { +static const DpmClock_t VddSocClk[]= { {478 ,2600 }, {722 ,3200 }, {722 ,3600 }, }; -DpmClock_t VddFClk[]= { +static const DpmClock_t VddFClk[]= { {400 ,2600 }, {1200 ,3200 }, {1200 ,3600 }, }; -DpmClock_t VddDispClk[]= { +static const DpmClock_t VddDispClk[]= { {435 ,2600 }, {661 ,3200 }, {1086 ,3600 }, }; -DpmClock_t VddDppClk[]= { +static const DpmClock_t VddDppClk[]= { {435 ,2600 }, {661 ,3200 }, {661 ,3600 }, }; -DpmClock_t VddPhyClk[]= { +static const DpmClock_t VddPhyClk[]= { {540 ,2600 }, {810 ,3200 }, {810 ,3600 },@@ -350,7 +350,7 @@ DpmClock_t VddPhyClk[]= {static int rv_get_clock_voltage_dependency_table (struct pp_hwmgr *hwmgr,struct rv_voltage_dependency_table **pptable, -uint32_t num_entry,DpmClock_t *pclk_dependency_table) +uint32_t num_entry,const DpmClock_t *pclk_dependency_table) {uint32_t table_size, i;struct rv_voltage_dependency_table *ptable; --2.9.4
Quoted 4 lines
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx