amdgpu/dc: make get_audio_clock_info return void.
Subsystems (3)
PATCH 1/9 amdgpu/dc: make get_audio_clock_info return void.
From: Dave Airlie <[email protected]>
This function never returned false under any sane circumstances.
--- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 75 ++++++++++------------ 1 file changed, 34 insertions(+), 41 deletions(-)
drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +34 -41
@@ -1238,7 +1238,7 @@ uint32_t calc_max_audio_packets_per_line(return max_packets_per_line; } -bool get_audio_clock_info( +void get_audio_clock_info( enum dc_color_depth color_depth, uint32_t crtc_pixel_clock_in_khz, uint32_t actual_pixel_clock_in_khz,
@@ -1249,9 +1249,6 @@ bool get_audio_clock_info(uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_in_khz /10 ;uint32_t audio_array_size; -if (audio_clock_info ==NULL ) -return false;/* should not happen */ -switch (color_depth) {case COLOR_DEPTH_161616 : clock_info = audio_clock_info_table_48bpc;
@@ -1280,7 +1277,7 @@ bool get_audio_clock_info( crtc_pixel_clock_in_10khz) {/* match found */ *audio_clock_info = clock_info[index]; -return true; +return ; } } }
@@ -1300,8 +1297,6 @@ bool get_audio_clock_info( audio_clock_info->n_32khz =4096 ; audio_clock_info->n_44khz =6272 ; audio_clock_info->n_48khz =6144 ; - -return true; } static void dce110_se_audio_setup(
@@ -1362,40 +1357,38 @@ static void dce110_se_setup_hdmi_audio( HDMI_ACR_AUDIO_PRIORITY, 0);/* Program audio clock sample/regeneration parameters */ -if (get_audio_clock_info ( - crtc_info->color_depth, - crtc_info->requested_pixel_clock, - crtc_info->calculated_pixel_clock, - &audio_clock_info)) { -dm_logger_write (enc->ctx->logger,LOG_HW_AUDIO , -"\n%s:Input::requested_pixel_clock = %d" \ -"calculated_pixel_clock = %d \n" , __func__,\ - crtc_info->requested_pixel_clock,\ - crtc_info->calculated_pixel_clock); - -/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ -REG_UPDATE (HDMI_ACR_32_0 ,HDMI_ACR_CTS_32 , audio_clock_info.cts_32khz); - -/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ -REG_UPDATE (HDMI_ACR_32_1 ,HDMI_ACR_N_32 , audio_clock_info.n_32khz); - -/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ -REG_UPDATE (HDMI_ACR_44_0 ,HDMI_ACR_CTS_44 , audio_clock_info.cts_44khz); - -/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ -REG_UPDATE (HDMI_ACR_44_1 ,HDMI_ACR_N_44 , audio_clock_info.n_44khz); - -/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ -REG_UPDATE (HDMI_ACR_48_0 ,HDMI_ACR_CTS_48 , audio_clock_info.cts_48khz); - -/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ -REG_UPDATE (HDMI_ACR_48_1 ,HDMI_ACR_N_48 , audio_clock_info.n_48khz); - -/* Video driver cannot know in advance which sample rate will -be used by HD Audio driver -HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is -programmed below in interruppt callback */ - }/* if */ +get_audio_clock_info (crtc_info->color_depth, + crtc_info->requested_pixel_clock, + crtc_info->calculated_pixel_clock, + &audio_clock_info); +dm_logger_write (enc->ctx->logger,LOG_HW_AUDIO , +"\n%s:Input::requested_pixel_clock = %d" \ +"calculated_pixel_clock = %d \n" , __func__, \ + crtc_info->requested_pixel_clock, \ + crtc_info->calculated_pixel_clock); + +/* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ +REG_UPDATE (HDMI_ACR_32_0 ,HDMI_ACR_CTS_32 , audio_clock_info.cts_32khz); + +/* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ +REG_UPDATE (HDMI_ACR_32_1 ,HDMI_ACR_N_32 , audio_clock_info.n_32khz); + +/* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ +REG_UPDATE (HDMI_ACR_44_0 ,HDMI_ACR_CTS_44 , audio_clock_info.cts_44khz); + +/* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ +REG_UPDATE (HDMI_ACR_44_1 ,HDMI_ACR_N_44 , audio_clock_info.n_44khz); + +/* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ +REG_UPDATE (HDMI_ACR_48_0 ,HDMI_ACR_CTS_48 , audio_clock_info.cts_48khz); + +/* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ +REG_UPDATE (HDMI_ACR_48_1 ,HDMI_ACR_N_48 , audio_clock_info.n_48khz); + +/* Video driver cannot know in advance which sample rate will +be used by HD Audio driver +HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is +programmed below in interruppt callback */ /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 2/9 amdgpu/dc: make program_regamma_pwl return void
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
The return value was unused.
--- drivers/gpu/drm/amd/display/dc/dce/dce_transform.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +--- drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 2 +- 6 files changed, 6 insertions(+), 12 deletions(-)
drivers/gpu/drm/amd/display/dc/dce/dce_transform.c +1 -3
@@ -1375,7 +1375,7 @@ static void regamma_config_regions_and_segments( -bool dce110_opp_program_regamma_pwl ( +void dce110_opp_program_regamma_pwl (struct transform *xfm,const struct pwl_params *params) {
@@ -1386,8 +1386,6 @@ bool dce110_opp_program_regamma_pwl(/* Program PWL */ program_pwl (xfm_dce, params); - -return true; } void dce110_opp_power_on_regamma_lut(
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +1 -1
@@ -506,7 +506,7 @@ void dce110_opp_power_on_regamma_lut(struct transform *xfm, bool power_on); -bool dce110_opp_program_regamma_pwl ( +void dce110_opp_program_regamma_pwl (struct transform *xfm,const struct pwl_params *params);
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_regamma_v.c +1 -3
@@ -490,7 +490,7 @@ static void program_pwl(struct dce_transform *xfm_dce, } } -bool dce110_opp_program_regamma_pwl_v ( +void dce110_opp_program_regamma_pwl_v (struct transform *xfm,const struct pwl_params *params) {
@@ -512,8 +512,6 @@ bool dce110_opp_program_regamma_pwl_v(/* Power return to auto back */ power_on_lut (xfm, false, false, true); - -return true; } void dce110_opp_power_on_regamma_lut_v(
drivers/gpu/drm/amd/display/dc/dce110/dce110_transform_v.h +1 -1
@@ -43,7 +43,7 @@ void dce110_opp_v_set_csc_adjustment( const struct out_csc_color_matrix *tbl_entry); -bool dce110_opp_program_regamma_pwl_v ( +void dce110_opp_program_regamma_pwl_v (struct transform *xfm,const struct pwl_params *params);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +1 -3
@@ -183,7 +183,7 @@ void dpp_reset(struct transform *xfm_base) -static bool dcn10_dpp_cm_set_regamma_pwl ( +static void dcn10_dpp_cm_set_regamma_pwl (struct transform *xfm_base,const struct pwl_params *params) {struct dcn10_dpp *xfm =TO_DCN10_DPP (xfm_base);
@@ -198,8 +198,6 @@ static bool dcn10_dpp_cm_set_regamma_pwl(dcn10_dpp_cm_program_regamma_lut ( xfm_base, params->rgb_resulted, params->hw_points_num); - -return true; } static void dcn10_dpp_cm_set_regamma_mode(
drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +1 -1
@@ -213,7 +213,7 @@ struct transform_funcs {struct transform *xfm, const struct pwl_params *params); -bool (*opp_program_regamma_pwl)( +void (*opp_program_regamma_pwl)(struct transform *xfm,const struct pwl_params *params); void (*opp_set_regamma_mode)(
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 3/9 amdgpu/dc: make some audio functions return void
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
There is no need to check for these pointers being valid at this level. Check earlier if required.
--- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-)
drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +2 -12
@@ -703,14 +703,11 @@ void dce_aud_az_configure(*/ /* search pixel clock value for Azalia HDMI Audio */ -static bool get_azalia_clock_info_hdmi ( +static void get_azalia_clock_info_hdmi (uint32_t crtc_pixel_clock_in_khz,uint32_t actual_pixel_clock_in_khz,struct azalia_clock_info *azalia_clock_info) { -if (azalia_clock_info ==NULL ) -return false; -/* audio_dto_phase= 24 * 10,000; * 24MHz in [100Hz] units */ azalia_clock_info->audio_dto_phase =
@@ -720,18 +717,13 @@ static bool get_azalia_clock_info_hdmi(* [khz] -> [100Hz] */ azalia_clock_info->audio_dto_module = actual_pixel_clock_in_khz *10 ; - -return true; } -static bool get_azalia_clock_info_dp ( +static void get_azalia_clock_info_dp (uint32_t requested_pixel_clock_in_khz,const struct audio_pll_info *pll_info,struct azalia_clock_info *azalia_clock_info) { -if (pll_info ==NULL || azalia_clock_info ==NULL ) -return false; -/* Reported dpDtoSourceClockInkhz value for * DCE8 already adjusted for SS, do not need any * adjustment here anymore
@@ -745,8 +737,6 @@ static bool get_azalia_clock_info_dp(* [khz] ->[100Hz] */ azalia_clock_info->audio_dto_module = pll_info->dp_dto_source_clock_in_khz *10 ; - -return true; } void dce_aud_wall_dto_setup(
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 4/9 amdgpu/dc: remove pointless returns in the i2caux constructor paths.
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
There was lots of return true, and error checking that was never used in these paths.
Just remove it all.
--- drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c | 6 ++-- drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h | 2 +- .../amd/display/dc/i2caux/dce100/i2caux_dce100.c | 21 +++++--------- .../display/dc/i2caux/dce110/aux_engine_dce110.c | 20 +++----------- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 24 ++++++---------- .../dc/i2caux/dce110/i2c_hw_engine_dce110.h | 4 --- .../dc/i2caux/dce110/i2c_sw_engine_dce110.c | 20 +++----------- .../amd/display/dc/i2caux/dce110/i2caux_dce110.c | 30 ++++++-------------- .../amd/display/dc/i2caux/dce110/i2caux_dce110.h | 2 +- .../amd/display/dc/i2caux/dce112/i2caux_dce112.c | 30 ++++++-------------- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 21 +++++--------- .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c | 32 ++++++++-------------- .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c | 17 +++--------- .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 19 +++---------- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 21 +++++--------- .../display/dc/i2caux/diagnostics/i2caux_diag.c | 20 +++----------- drivers/gpu/drm/amd/display/dc/i2caux/engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/engine_base.c | 3 +- drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c | 7 ++--- drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h | 2 +- .../amd/display/dc/i2caux/i2c_generic_hw_engine.c | 6 ++-- .../amd/display/dc/i2caux/i2c_generic_hw_engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c | 6 ++-- .../gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h | 2 +- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c | 17 +++--------- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h | 2 +- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 +-- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h | 2 +- 28 files changed, 100 insertions(+), 244 deletions(-)
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.c +2 -4
@@ -555,15 +555,13 @@ bool dal_aux_engine_submit_request(return result; } -bool dal_aux_engine_construct ( +void dal_aux_engine_construct (struct aux_engine *engine,struct dc_context *ctx) { -if (!dal_i2caux_construct_engine (&engine->base, ctx)) -return false; +dal_i2caux_construct_engine (&engine->base, ctx); engine->delay =0 ; engine->max_defer_write_retry =0 ; -return true; } void dal_aux_engine_destruct(
drivers/gpu/drm/amd/display/dc/i2caux/aux_engine.h +1 -1
@@ -100,7 +100,7 @@ struct aux_engine {bool acquire_reset; }; -bool dal_aux_engine_construct ( +void dal_aux_engine_construct (struct aux_engine *engine,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c +7 -14
@@ -95,18 +95,11 @@ struct i2caux *dal_i2caux_dce100_create(return NULL ; } -if (dal_i2caux_dce110_construct ( - i2caux_dce110, - ctx, - dce100_aux_regs, - dce100_hw_engine_regs, - &i2c_shift, - &i2c_mask)) -return &i2caux_dce110->base; - -ASSERT_CRITICAL (false); - -kfree (i2caux_dce110); - -return NULL ; +dal_i2caux_dce110_construct (i2caux_dce110, + ctx, + dce100_aux_regs, + dce100_hw_engine_regs, + &i2c_shift, + &i2c_mask); +return &i2caux_dce110->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +4 -16
@@ -426,22 +426,16 @@ static const struct engine_funcs engine_funcs = { .acquire = dal_aux_engine_acquire, }; -static bool construct ( +static void construct (struct aux_engine_dce110 *engine,const struct aux_engine_dce110_init_data *aux_init_data) { -if (!dal_aux_engine_construct ( - &engine->base, aux_init_data->ctx)) { -ASSERT_CRITICAL (false); -return false; - } +dal_aux_engine_construct (&engine->base, aux_init_data->ctx); engine->base.base.funcs = &engine_funcs; engine->base.funcs = &aux_engine_funcs; engine->timeout_period = aux_init_data->timeout_period; engine->regs = aux_init_data->regs; - -return true; } static void destruct(
@@ -471,12 +465,6 @@ struct aux_engine *dal_aux_engine_dce110_create(return NULL ; } -if (construct (engine, aux_init_data)) -return &engine->base; - -ASSERT_CRITICAL (false); - -kfree (engine); - -return NULL ; +construct (engine, aux_init_data); +return &engine->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +8 -16
@@ -498,17 +498,13 @@ static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = { .wait_on_operation_result = dal_i2c_hw_engine_wait_on_operation_result, }; -bool i2c_hw_engine_dce110_construct ( +static void construct (struct i2c_hw_engine_dce110 *hw_engine,const struct i2c_hw_engine_dce110_create_arg *arg) {uint32_t xtal_ref_div =0 ; -if (!arg->reference_frequency) -return false; - -if (!dal_i2c_hw_engine_construct (&hw_engine->base, arg->ctx)) -return false; +dal_i2c_hw_engine_construct (&hw_engine->base, arg->ctx); hw_engine->base.base.base.funcs = &engine_funcs; hw_engine->base.base.funcs = &i2c_engine_funcs;
@@ -545,8 +541,6 @@ bool i2c_hw_engine_dce110_construct(*/ hw_engine->reference_frequency = (arg->reference_frequency *2 ) / xtal_ref_div; - -return true; } struct i2c_engine *dal_i2c_hw_engine_dce110_create(
@@ -558,6 +552,10 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(ASSERT_CRITICAL (false);return NULL ; } +if (!arg->reference_frequency) { +ASSERT_CRITICAL (false); +return NULL ; + } engine_dce10 =kzalloc (sizeof (struct i2c_hw_engine_dce110 ),GFP_KERNEL );
@@ -567,12 +565,6 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create(return NULL ; } -if (i2c_hw_engine_dce110_construct (engine_dce10, arg)) -return &engine_dce10->base.base; - -ASSERT_CRITICAL (false); - -kfree (engine_dce10); - -return NULL ; +construct (engine_dce10, arg); +return &engine_dce10->base.base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.h +0 -4
@@ -207,8 +207,4 @@ struct i2c_hw_engine_dce110_create_arg {struct i2c_engine *dal_i2c_hw_engine_dce110_create (const struct i2c_hw_engine_dce110_create_arg *arg); -bool i2c_hw_engine_dce110_construct ( -struct i2c_hw_engine_dce110 *engine_dce110, -const struct i2c_hw_engine_dce110_create_arg *arg); -#endif
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c +4 -16
@@ -118,7 +118,7 @@ static const struct engine_funcs engine_funcs = { .submit_request = dal_i2c_sw_engine_submit_request, }; -static bool construct ( +static void construct (struct i2c_sw_engine_dce110 *engine_dce110,const struct i2c_sw_engine_dce110_create_arg *arg_dce110) {
@@ -127,11 +127,7 @@ static bool construct( arg_base.ctx = arg_dce110->ctx; arg_base.default_speed = arg_dce110->default_speed; -if (!dal_i2c_sw_engine_construct ( - &engine_dce110->base, &arg_base)) { -ASSERT_CRITICAL (false); -return false; - } +dal_i2c_sw_engine_construct (&engine_dce110->base, &arg_base);/*struct engine struct engine_funcs*/ engine_dce110->base.base.base.funcs = &engine_funcs;
@@ -139,8 +135,6 @@ static bool construct( engine_dce110->base.base.funcs = &i2c_engine_funcs; engine_dce110->base.default_speed = arg_dce110->default_speed; engine_dce110->engine_id = arg_dce110->engine_id; - -return true; } struct i2c_engine *dal_i2c_sw_engine_dce110_create(
@@ -161,12 +155,6 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create(return NULL ; } -if (construct (engine_dce110, arg)) -return &engine_dce110->base.base; - -ASSERT_CRITICAL (false); - -kfree (engine_dce110); - -return NULL ; +construct (engine_dce110, arg); +return &engine_dce110->base.base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c +9 -21
@@ -196,7 +196,7 @@ static const struct dce110_i2c_hw_engine_mask i2c_mask = {I2C_COMMON_MASK_SH_LIST_DCE110 (_MASK) }; -bool dal_i2caux_dce110_construct( +void dal_i2caux_dce110_construct( struct i2caux_dce110 *i2caux_dce110, struct dc_context *ctx, const struct dce110_aux_registers aux_regs[],
@@ -217,10 +217,7 @@ bool dal_i2caux_dce110_construct( base = &i2caux_dce110->base; -if (!dal_i2caux_construct (base, ctx)) { -ASSERT_CRITICAL (false); -return false; - } +dal_i2caux_construct (base, ctx); i2caux_dce110->base.funcs = &i2caux_funcs; i2caux_dce110->i2c_hw_buffer_in_use = false;
@@ -278,8 +275,6 @@ bool dal_i2caux_dce110_construct( }while (i <ARRAY_SIZE (hw_aux_lines));/*TODO Generic I2C SW and HW*/ - -return true; }/*
@@ -306,18 +301,11 @@ struct i2caux *dal_i2caux_dce110_create(return NULL ; } -if (dal_i2caux_dce110_construct ( - i2caux_dce110, - ctx, - dce110_aux_regs, - i2c_hw_engine_regs, - &i2c_shift, - &i2c_mask)) -return &i2caux_dce110->base; - -ASSERT_CRITICAL (false); - -kfree (i2caux_dce110); - -return NULL ; +dal_i2caux_dce110_construct (i2caux_dce110, + ctx, + dce110_aux_regs, + i2c_hw_engine_regs, + &i2c_shift, + &i2c_mask); +return &i2caux_dce110->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.h +1 -1
@@ -42,7 +42,7 @@ struct dce110_i2c_hw_engine_mask;struct i2caux *dal_i2caux_dce110_create (struct dc_context *ctx); -bool dal_i2caux_dce110_construct( +void dal_i2caux_dce110_construct( struct i2caux_dce110 *i2caux_dce110, struct dc_context *ctx, const struct dce110_aux_registers *aux_regs,
drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c +9 -21
@@ -87,22 +87,16 @@ static const struct dce110_i2c_hw_engine_mask i2c_mask = { I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) }; -static bool construct ( +static void construct (struct i2caux_dce110 *i2caux_dce110,struct dc_context *ctx) { -if (!dal_i2caux_dce110_construct ( - i2caux_dce110, - ctx, - dce112_aux_regs, - dce112_hw_engine_regs, - &i2c_shift, - &i2c_mask)) { -ASSERT_CRITICAL (false); -return false; - } - -return true; +dal_i2caux_dce110_construct (i2caux_dce110, + ctx, + dce112_aux_regs, + dce112_hw_engine_regs, + &i2c_shift, + &i2c_mask); }/*
@@ -129,12 +123,6 @@ struct i2caux *dal_i2caux_dce112_create(return NULL ; } -if (construct (i2caux_dce110, ctx)) -return &i2caux_dce110->base; - -ASSERT_CRITICAL (false); - -kfree (i2caux_dce110); - -return NULL ; +construct (i2caux_dce110, ctx); +return &i2caux_dce110->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +7 -14
@@ -108,18 +108,11 @@ struct i2caux *dal_i2caux_dce120_create(return NULL ; } -if (dal_i2caux_dce110_construct ( - i2caux_dce110, - ctx, - dce120_aux_regs, - dce120_hw_engine_regs, - &i2c_shift, - &i2c_mask)) -return &i2caux_dce110->base; - -ASSERT_CRITICAL (false); - -kfree (i2caux_dce110); - -return NULL ; +dal_i2caux_dce110_construct (i2caux_dce110, + ctx, + dce120_aux_regs, + dce120_hw_engine_regs, + &i2c_shift, + &i2c_mask); +return &i2caux_dce110->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c +11 -21
@@ -824,20 +824,11 @@ static const struct i2c_hw_engine_funcs i2c_hw_engine_funcs = { dal_i2c_hw_engine_wait_on_operation_result, }; -static bool construct ( +static void construct (struct i2c_hw_engine_dce80 *engine,const struct i2c_hw_engine_dce80_create_arg *arg) { -if (arg->engine_id >=sizeof (ddc_setup_offset) /sizeof (int32_t )) -return false; -if (arg->engine_id >=sizeof (ddc_speed_offset) /sizeof (int32_t )) -return false; - -if (!arg->reference_frequency) -return false; - -if (!dal_i2c_hw_engine_construct (&engine->base, arg->ctx)) -return false; +dal_i2c_hw_engine_construct (&engine->base, arg->ctx); engine->base.base.base.funcs = &engine_funcs; engine->base.base.funcs = &i2c_engine_funcs;
@@ -853,8 +844,6 @@ static bool construct( engine->buffer_used_bytes =0 ; engine->transaction_count =0 ; engine->engine_keep_power_up_count =1 ; - -return true; } struct i2c_engine *dal_i2c_hw_engine_dce80_create(
@@ -867,6 +856,13 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create(return NULL ; } +if ((arg->engine_id >=sizeof (ddc_setup_offset) /sizeof (int32_t )) || + (arg->engine_id >=sizeof (ddc_speed_offset) /sizeof (int32_t )) || + !arg->reference_frequency) { +BREAK_TO_DEBUGGER (); +return NULL ; + } + engine =kzalloc (sizeof (struct i2c_hw_engine_dce80 ),GFP_KERNEL );if (!engine) {
@@ -874,12 +870,6 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create(return NULL ; } -if (construct (engine, arg)) -return &engine->base.base; - -BREAK_TO_DEBUGGER (); - -kfree (engine); - -return NULL ; +construct (engine, arg); +return &engine->base.base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c +4 -13
@@ -133,7 +133,7 @@ static const struct engine_funcs engine_funcs = { .submit_request = dal_i2c_sw_engine_submit_request, }; -static bool construct ( +static void construct (struct i2c_sw_engine_dce80 *engine,const struct i2c_sw_engine_dce80_create_arg *arg) {
@@ -142,10 +142,7 @@ static bool construct( arg_base.ctx = arg->ctx; arg_base.default_speed = arg->default_speed; -if (!dal_i2c_sw_engine_construct (&engine->base, &arg_base)) { -BREAK_TO_DEBUGGER (); -return false; - } +dal_i2c_sw_engine_construct (&engine->base, &arg_base); engine->base.base.base.funcs = &engine_funcs; engine->base.base.funcs = &i2c_engine_funcs;
@@ -172,13 +169,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create(return NULL ; } -if (construct (engine, arg)) -return &engine->base.base; - -BREAK_TO_DEBUGGER (); - -kfree (engine); - -return NULL ; +construct (engine, arg); +return &engine->base.base; }
drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c +4 -15
@@ -187,7 +187,7 @@ static const struct i2caux_funcs i2caux_funcs = { .acquire_aux_engine = dal_i2caux_acquire_aux_engine, }; -static bool construct ( +static void construct (struct i2caux_dce80 *i2caux_dce80,struct dc_context *ctx) {
@@ -207,10 +207,7 @@ static bool construct(uint32_t i; -if (!dal_i2caux_construct (base, ctx)) { -BREAK_TO_DEBUGGER (); -return false; - } +dal_i2caux_construct (base, ctx); i2caux_dce80->base.funcs = &i2caux_funcs; i2caux_dce80->i2c_hw_buffer_in_use = false;
@@ -269,8 +266,6 @@ static bool construct( }while (i <ARRAY_SIZE (hw_aux_lines));/* TODO Generic I2C SW and HW */ - -return true; } struct i2caux *dal_i2caux_dce80_create(
@@ -284,12 +279,6 @@ struct i2caux *dal_i2caux_dce80_create(return NULL ; } -if (construct (i2caux_dce80, ctx)) -return &i2caux_dce80->base; - -BREAK_TO_DEBUGGER (); - -kfree (i2caux_dce80); - -return NULL ; +construct (i2caux_dce80, ctx); +return &i2caux_dce80->base; }
drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +7 -14
@@ -108,18 +108,11 @@ struct i2caux *dal_i2caux_dcn10_create(return NULL ; } -if (dal_i2caux_dce110_construct ( - i2caux_dce110, - ctx, - dcn10_aux_regs, - dcn10_hw_engine_regs, - &i2c_shift, - &i2c_mask)) -return &i2caux_dce110->base; - -ASSERT_CRITICAL (false); - -kfree (i2caux_dce110); - -return NULL ; +dal_i2caux_dce110_construct (i2caux_dce110, + ctx, + dcn10_aux_regs, + dcn10_hw_engine_regs, + &i2c_shift, + &i2c_mask); +return &i2caux_dce110->base; }
drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c +4 -16
@@ -73,18 +73,12 @@ static const struct i2caux_funcs i2caux_funcs = { .acquire_aux_engine = NULL, }; -static bool construct ( +static void construct (struct i2caux *i2caux,struct dc_context *ctx) { -if (!dal_i2caux_construct (i2caux, ctx)) { -ASSERT_CRITICAL (false); -return false; - } - +dal_i2caux_construct (i2caux, ctx); i2caux->funcs = &i2caux_funcs; - -return true; } struct i2caux *dal_i2caux_diag_fpga_create(
@@ -98,12 +92,6 @@ struct i2caux *dal_i2caux_diag_fpga_create(return NULL ; } -if (construct (i2caux, ctx)) -return i2caux; - -ASSERT_CRITICAL (false); - -kfree (i2caux); - -return NULL ; +construct (i2caux, ctx); +return i2caux; }
drivers/gpu/drm/amd/display/dc/i2caux/engine.h +1 -1
@@ -110,7 +110,7 @@ struct engine {struct dc_context *ctx; }; -bool dal_i2caux_construct_engine ( +void dal_i2caux_construct_engine (struct engine *engine,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/i2caux/engine_base.c +1 -2
@@ -36,13 +36,12 @@#include "engine.h" -bool dal_i2caux_construct_engine ( +void dal_i2caux_construct_engine (struct engine *engine,struct dc_context *ctx) { engine->ddc =NULL ; engine->ctx = ctx; -return true; } void dal_i2caux_destruct_engine(
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.c +2 -5
@@ -103,15 +103,12 @@ void dal_i2c_engine_process_channel_reply( } -bool dal_i2c_engine_construct ( +void dal_i2c_engine_construct (struct i2c_engine *engine,struct dc_context *ctx) { -if (!dal_i2caux_construct_engine (&engine->base, ctx)) -return false; - +dal_i2caux_construct_engine (&engine->base, ctx); engine->timeout_delay =0 ; -return true; } void dal_i2c_engine_destruct(
drivers/gpu/drm/amd/display/dc/i2caux/i2c_engine.h +1 -1
@@ -88,7 +88,7 @@ struct i2c_engine {uint32_t timeout_delay; }; -bool dal_i2c_engine_construct ( +void dal_i2c_engine_construct (struct i2c_engine *engine,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.c +2 -4
@@ -270,13 +270,11 @@ uint32_t dal_i2c_generic_hw_engine_get_transaction_timeout( (1 + (length <<3 ) +1 ); } -bool dal_i2c_generic_hw_engine_construct ( +void dal_i2c_generic_hw_engine_construct (struct i2c_generic_hw_engine *engine,struct dc_context *ctx) { -if (!dal_i2c_hw_engine_construct (&engine->base, ctx)) -return false; -return true; +dal_i2c_hw_engine_construct (&engine->base, ctx); } void dal_i2c_generic_hw_engine_destruct(
drivers/gpu/drm/amd/display/dc/i2caux/i2c_generic_hw_engine.h +1 -1
@@ -59,7 +59,7 @@ struct i2c_generic_hw_engine {const struct i2c_generic_hw_engine_funcs *funcs; }; -bool dal_i2c_generic_hw_engine_construct ( +void dal_i2c_generic_hw_engine_construct (struct i2c_generic_hw_engine *engine,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.c +2 -4
@@ -228,15 +228,13 @@ enum i2c_channel_operation_result dal_i2c_hw_engine_wait_on_operation_result(return result; } -bool dal_i2c_hw_engine_construct ( +void dal_i2c_hw_engine_construct (struct i2c_hw_engine *engine,struct dc_context *ctx) { -if (!dal_i2c_engine_construct (&engine->base, ctx)) -return false; +dal_i2c_engine_construct (&engine->base, ctx); engine->original_speed =I2CAUX_DEFAULT_I2C_HW_SPEED ; engine->default_speed =I2CAUX_DEFAULT_I2C_HW_SPEED ; -return true; } void dal_i2c_hw_engine_destruct(
drivers/gpu/drm/amd/display/dc/i2caux/i2c_hw_engine.h +1 -1
@@ -53,7 +53,7 @@ struct i2c_hw_engine {uint32_t default_speed; }; -bool dal_i2c_hw_engine_construct ( +void dal_i2c_hw_engine_construct (struct i2c_hw_engine *engine,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c +4 -13
@@ -569,17 +569,14 @@ static const struct engine_funcs engine_funcs = { .submit_request = dal_i2c_sw_engine_submit_request, }; -bool dal_i2c_sw_engine_construct ( +void dal_i2c_sw_engine_construct (struct i2c_sw_engine *engine,const struct i2c_sw_engine_create_arg *arg) { -if (!dal_i2c_engine_construct (&engine->base, arg->ctx)) -return false; - +dal_i2c_engine_construct (&engine->base, arg->ctx);dal_i2c_sw_engine_set_speed (&engine->base, arg->default_speed); engine->base.funcs = &i2c_engine_funcs; engine->base.base.funcs = &engine_funcs; -return true; } struct i2c_engine *dal_i2c_sw_engine_create(
@@ -599,12 +596,6 @@ struct i2c_engine *dal_i2c_sw_engine_create(return NULL ; } -if (dal_i2c_sw_engine_construct (engine, arg)) -return &engine->base; - -BREAK_TO_DEBUGGER (); - -kfree (engine); - -return NULL ; +dal_i2c_sw_engine_construct (engine, arg); +return &engine->base; }
drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.h +1 -1
@@ -48,7 +48,7 @@ struct i2c_sw_engine_create_arg {struct dc_context *ctx; }; -bool dal_i2c_sw_engine_construct ( +void dal_i2c_sw_engine_construct (struct i2c_sw_engine *engine,const struct i2c_sw_engine_create_arg *arg);
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +1 -3
@@ -423,7 +423,7 @@ void dal_i2caux_release_engine( engine->ddc =NULL ; } -bool dal_i2caux_construct ( +void dal_i2caux_construct (struct i2caux *i2caux,struct dc_context *ctx) {
@@ -451,8 +451,6 @@ bool dal_i2caux_construct( i2caux->default_i2c_hw_speed =DEFAULT_I2C_HW_SPEED ; i2caux->default_i2c_sw_speed =DEFAULT_I2C_SW_SPEED ; } - -return true; } void dal_i2caux_destruct(
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.h +1 -1
@@ -97,7 +97,7 @@ struct i2caux {uint32_t default_i2c_hw_speed; }; -bool dal_i2caux_construct ( +void dal_i2caux_construct (struct i2caux *i2caux,struct dc_context *ctx);
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 5/9 amdgpu/dc: cleanup construct returns in gpio.
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
This is similiar to previous patches, don't return when we don't need to, also do error checking before allocating memory, makes it simpler to cleanup after.
--- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 33 +++++++------------ drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c | 4 +-- drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 47 ++++++++++----------------- 4 files changed, 30 insertions(+), 56 deletions(-)
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +11 -22
@@ -199,25 +199,14 @@ static const struct hw_gpio_pin_funcs funcs = { .close = dal_hw_gpio_close, }; -static bool construct ( +static void construct (struct hw_ddc *ddc,enum gpio_id id,uint32_t en,struct dc_context *ctx) { -if ((en <GPIO_DDC_LINE_MIN ) || (en >GPIO_DDC_LINE_MAX )) { -ASSERT_CRITICAL (false); -return false; - } - -if (!dal_hw_gpio_construct (&ddc->base, id, en, ctx)) { -ASSERT_CRITICAL (false); -return false; - } - +dal_hw_gpio_construct (&ddc->base, id, en, ctx); ddc->base.base.funcs = &funcs; - -return true; } struct hw_gpio_pin *dal_hw_ddc_create(
@@ -225,19 +214,19 @@ struct hw_gpio_pin *dal_hw_ddc_create( enum gpio_id id, uint32_t en) { -struct hw_ddc *pin =kzalloc (sizeof (struct hw_ddc ),GFP_KERNEL ); +struct hw_ddc *pin; -if (!pin) { +if ((en <GPIO_DDC_LINE_MIN ) || (en >GPIO_DDC_LINE_MAX )) {ASSERT_CRITICAL (false);return NULL ; } -if (construct (pin, id, en, ctx)) -return &pin->base.base; - -ASSERT_CRITICAL (false); - -kfree (pin); + pin =kzalloc (sizeof (struct hw_ddc ),GFP_KERNEL ); +if (!pin) { +ASSERT_CRITICAL (false); +return NULL ; + } -return NULL ; +construct (pin, id, en, ctx); +return &pin->base.base; }
drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c +1 -3
@@ -176,7 +176,7 @@ enum gpio_result dal_hw_gpio_config_mode( } } -bool dal_hw_gpio_construct( +void dal_hw_gpio_construct( struct hw_gpio *pin, enum gpio_id id, uint32_t en,
@@ -194,8 +194,6 @@ bool dal_hw_gpio_construct( pin->store.mux =0 ; pin->mux_supported = false; - -return true; } void dal_hw_gpio_destruct(
drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h +1 -1
@@ -109,7 +109,7 @@ struct hw_gpio {#define HW_GPIO_FROM_BASE (hw_gpio_pin) \ container_of((hw_gpio_pin), struct hw_gpio, base) -bool dal_hw_gpio_construct( +void dal_hw_gpio_construct( struct hw_gpio *pin, enum gpio_id id, uint32_t en,
drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +17 -30
81 lines not on this page · raw message
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 6/9 amdgpu/dc: another round of dce/dcn construct cleanups.
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
This removes any remaining pointless return codepaths from the DCE code.
--- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce100/dce100_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce100/dce100_resource.c | 4 +--- .../drm/amd/display/dc/dce110/dce110_compressor.c | 11 +++-------- .../drm/amd/display/dc/dce110/dce110_compressor.h | 2 +- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c | 4 +--- drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h | 2 +- .../gpu/drm/amd/display/dc/dce110/dce110_resource.c | 6 ++---- .../display/dc/dce110/dce110_timing_generator_v.c | 7 +------ .../display/dc/dce110/dce110_timing_generator_v.h | 2 +- .../drm/amd/display/dc/dce112/dce112_compressor.c | 11 +++-------- .../drm/amd/display/dc/dce112/dce112_compressor.h | 2 +- .../drm/amd/display/dc/dce112/dce112_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce112/dce112_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 +-- .../drm/amd/display/dc/dce120/dce120_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce120/dce120_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 8 ++------ .../amd/display/dc/dce120/dce120_timing_generator.c | 7 +------ .../amd/display/dc/dce120/dce120_timing_generator.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_compressor.c | 11 +++-------- .../gpu/drm/amd/display/dc/dce80/dce80_compressor.h | 2 +- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.c | 4 +--- .../drm/amd/display/dc/dce80/dce80_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 9 +++------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 4 +--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c | 4 +--- .../gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 20 ++++++-------------- 32 files changed, 47 insertions(+), 108 deletions(-)
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +1 -3
@@ -142,13 +142,11 @@ void dce100_set_bandwidth(/**************************************************************************/ -bool dce100_hw_sequencer_construct (struct dc *dc) +void dce100_hw_sequencer_construct (struct dc *dc) {dce110_hw_sequencer_construct (dc); dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating; dc->hwss.set_bandwidth = dce100_set_bandwidth; - -return true; }
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +1 -1
@@ -31,7 +31,7 @@struct dc ;struct dc_state ; -bool dce100_hw_sequencer_construct (struct dc *dc); +void dce100_hw_sequencer_construct (struct dc *dc); void dce100_set_bandwidth( struct dc *dc,
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +1 -3
@@ -909,9 +909,7 @@ static bool construct( goto res_create_fail;/* Create hardware sequencer */ -if (!dce100_hw_sequencer_construct (dc)) - goto res_create_fail; - +dce100_hw_sequencer_construct (dc);return true; res_create_fail:
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +3 -8
@@ -393,12 +393,8 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx)if (!cp110)return NULL ; -if (dce110_compressor_construct (cp110, ctx)) -return &cp110->base; - -BREAK_TO_DEBUGGER (); -kfree (cp110); -return NULL ; +dce110_compressor_construct (cp110, ctx); +return &cp110->base; }void dce110_compressor_destroy (struct compressor **compressor)
@@ -485,7 +481,7 @@ static const struct compressor_funcs dce110_compressor_funcs = { }; -bool dce110_compressor_construct (struct dce110_compressor *compressor, +void dce110_compressor_construct (struct dce110_compressor *compressor,struct dc_context *ctx) {
@@ -522,6 +518,5 @@ bool dce110_compressor_construct(struct dce110_compressor *compressor, compressor->base.funcs = &dce110_compressor_funcs;#endif -return true; }
drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.h +1 -1
@@ -42,7 +42,7 @@ struct dce110_compressor {struct compressor *dce110_compressor_create (struct dc_context *ctx); -bool dce110_compressor_construct (struct dce110_compressor *cp110, +void dce110_compressor_construct (struct dce110_compressor *cp110,struct dc_context *ctx);void dce110_compressor_destroy (struct compressor **cp);
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +1 -3
@@ -2723,10 +2723,8 @@ static const struct hw_sequencer_funcs dce110_funcs = { }; -bool dce110_hw_sequencer_construct (struct dc *dc) +void dce110_hw_sequencer_construct (struct dc *dc) { dc->hwss = dce110_funcs; - -return true; }
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +1 -1
@@ -33,7 +33,7 @@ struct dc;struct dc_state ;struct dm_pp_display_configuration ; -bool dce110_hw_sequencer_construct (struct dc *dc); +void dce110_hw_sequencer_construct (struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( struct dc *dc,
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.c +1 -3
@@ -44,13 +44,11 @@ static const struct opp_funcs funcs = { dce110_opp_program_bit_depth_reduction }; -bool dce110_opp_v_construct (struct dce110_opp *opp110, +void dce110_opp_v_construct (struct dce110_opp *opp110,struct dc_context *ctx) { opp110->base.funcs = &funcs; opp110->base.ctx = ctx; - -return true; }
drivers/gpu/drm/amd/display/dc/dce110/dce110_opp_v.h +1 -1
@@ -29,7 +29,7 @@#include "opp.h" #include "core_types.h" -bool dce110_opp_v_construct (struct dce110_opp *opp110, +void dce110_opp_v_construct (struct dce110_opp *opp110,struct dc_context *ctx);/* underlay callbacks */
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +2 -4
@@ -1041,8 +1041,7 @@ static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) (dce110_oppv == NULL))return false; -if (!dce110_opp_v_construct (dce110_oppv, ctx)) -return false; +dce110_opp_v_construct (dce110_oppv, ctx);dce110_timing_generator_v_construct (dce110_tgv, ctx);dce110_mem_input_v_construct (dce110_miv, ctx);
@@ -1292,8 +1291,7 @@ static bool construct( goto res_create_fail;/* Create hardware sequencer */ -if (!dce110_hw_sequencer_construct (dc)) - goto res_create_fail; +dce110_hw_sequencer_construct (dc); dc->caps.max_planes = pool->base.pipe_count;
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c +1 -6
@@ -668,13 +668,10 @@ static const struct timing_generator_funcs dce110_tg_v_funcs = { dce110_timing_generator_v_enable_advanced_request }; -bool dce110_timing_generator_v_construct ( +void dce110_timing_generator_v_construct (struct dce110_timing_generator *tg110,struct dc_context *ctx) { -if (!tg110) -return false; - tg110->controller_id =CONTROLLER_ID_UNDERLAY0 ; tg110->base.funcs = &dce110_tg_v_funcs;
@@ -688,6 +685,4 @@ bool dce110_timing_generator_v_construct( tg110->min_h_blank =56 ; tg110->min_h_front_porch =4 ; tg110->min_h_back_porch =4 ; - -return true; }
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.h +1 -1
@@ -26,7 +26,7 @@#ifndef __DC_TIMING_GENERATOR_V_DCE110_H__#define __DC_TIMING_GENERATOR_V_DCE110_H__ -bool dce110_timing_generator_v_construct ( +void dce110_timing_generator_v_construct (struct dce110_timing_generator *tg110,struct dc_context *ctx);
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +3 -8
@@ -791,7 +791,7 @@ void dce112_compressor_set_fbc_invalidation_triggers(dm_write_reg (compressor->ctx, addr, value); } -bool dce112_compressor_construct (struct dce112_compressor *compressor, +void dce112_compressor_construct (struct dce112_compressor *compressor,struct dc_context *ctx) {struct dc_bios *bp = ctx->dc_bios;
@@ -833,7 +833,6 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, compressor->base.embedded_panel_v_size = panel_info.lcd_timing.vertical_addressable; } -return true; }struct compressor *dce112_compressor_create (struct dc_context *ctx)
@@ -844,12 +843,8 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx)if (!cp110)return NULL ; -if (dce112_compressor_construct (cp110, ctx)) -return &cp110->base; - -BREAK_TO_DEBUGGER (); -kfree (cp110); -return NULL ; +dce112_compressor_construct (cp110, ctx); +return &cp110->base; }void dce112_compressor_destroy (struct compressor **compressor)
drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.h +1 -1
@@ -42,7 +42,7 @@ struct dce112_compressor {struct compressor *dce112_compressor_create (struct dc_context *ctx); -bool dce112_compressor_construct (struct dce112_compressor *cp110, +void dce112_compressor_construct (struct dce112_compressor *cp110,struct dc_context *ctx);void dce112_compressor_destroy (struct compressor **cp);
drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.c +1 -3
@@ -152,14 +152,12 @@ static bool dce112_enable_display_power_gating(return false; } -bool dce112_hw_sequencer_construct (struct dc *dc) +void dce112_hw_sequencer_construct (struct dc *dc) {/* All registers used by dce11.2 match those in dce11 in offset and * structure */ dce110_hw_sequencer_construct (dc); dc->hwss.enable_display_power_gating = dce112_enable_display_power_gating; - -return true; }
drivers/gpu/drm/amd/display/dc/dce112/dce112_hw_sequencer.h +1 -1
@@ -30,7 +30,7 @@struct dc ; -bool dce112_hw_sequencer_construct (struct dc *dc); +void dce112_hw_sequencer_construct (struct dc *dc);#endif /* __DC_HWSS_DCE112_H__ */
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +1 -2
@@ -1256,8 +1256,7 @@ static bool construct( dc->caps.max_planes = pool->base.pipe_count;/* Create hardware sequencer */ -if (!dce112_hw_sequencer_construct (dc)) - goto res_create_fail; +dce112_hw_sequencer_construct (dc);bw_calcs_init (dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c +1 -3
@@ -245,7 +245,7 @@ static void dce120_update_dchub( -bool dce120_hw_sequencer_construct (struct dc *dc) +void dce120_hw_sequencer_construct (struct dc *dc) {/* All registers used by dce11.2 match those in dce11 in offset and * structure
@@ -253,7 +253,5 @@ bool dce120_hw_sequencer_construct(struct dc *dc)dce110_hw_sequencer_construct (dc); dc->hwss.enable_display_power_gating = dce120_enable_display_power_gating; dc->hwss.update_dchub = dce120_update_dchub; - -return true; }
drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h +1 -1
@@ -30,7 +30,7 @@struct dc ; -bool dce120_hw_sequencer_construct (struct dc *dc); +void dce120_hw_sequencer_construct (struct dc *dc);#endif /* __DC_HWSS_DCE112_H__ */
drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +2 -6
@@ -429,12 +429,8 @@ static struct timing_generator *dce120_timing_generator_create(if (!tg110)return NULL ; -if (dce120_timing_generator_construct (tg110, ctx, instance, offsets)) -return &tg110->base; - -BREAK_TO_DEBUGGER (); -kfree (tg110); -return NULL ; +dce120_timing_generator_construct (tg110, ctx, instance, offsets); +return &tg110->base; }static void dce120_transform_destroy (struct transform **xfm)
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +1 -6
@@ -1143,15 +1143,12 @@ static const struct timing_generator_funcs dce120_tg_funcs = { }; -bool dce120_timing_generator_construct ( +void dce120_timing_generator_construct (struct dce110_timing_generator *tg110,struct dc_context *ctx,uint32_t instance,const struct dce110_timing_generator_offsets *offsets) { -if (!tg110) -return false; - tg110->controller_id =CONTROLLER_ID_D0 + instance; tg110->base.inst = instance;
@@ -1175,6 +1172,4 @@ bool dce120_timing_generator_construct( tg110->min_h_sync_width =8 ; tg110->min_v_sync_width =1 ; tg110->min_v_blank =3 ; - -return true; }
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h +1 -1
@@ -32,7 +32,7 @@#include "dce110/dce110_timing_generator.h" -bool dce120_timing_generator_construct( +void dce120_timing_generator_construct( struct dce110_timing_generator *tg110, struct dc_context *ctx, uint32_t instance,
drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +3 -8
@@ -771,7 +771,7 @@ void dce80_compressor_set_fbc_invalidation_triggers(dm_write_reg (compressor->ctx, addr, value); } -bool dce80_compressor_construct (struct dce80_compressor *compressor, +void dce80_compressor_construct (struct dce80_compressor *compressor,struct dc_context *ctx) {struct dc_bios *bp = ctx->dc_bios;
@@ -813,7 +813,6 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, compressor->base.embedded_panel_v_size = panel_info.lcd_timing.vertical_addressable; } -return true; }struct compressor *dce80_compressor_create (struct dc_context *ctx)
@@ -824,12 +823,8 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx)if (!cp80)return NULL ; -if (dce80_compressor_construct (cp80, ctx)) -return &cp80->base; - -BREAK_TO_DEBUGGER (); -kfree (cp80); -return NULL ; +dce80_compressor_construct (cp80, ctx); +return &cp80->base; }void dce80_compressor_destroy (struct compressor **compressor)
drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.h +1 -1
@@ -42,7 +42,7 @@ struct dce80_compressor {struct compressor *dce80_compressor_create (struct dc_context *ctx); -bool dce80_compressor_construct (struct dce80_compressor *cp80, +void dce80_compressor_construct (struct dce80_compressor *cp80,struct dc_context *ctx);void dce80_compressor_destroy (struct compressor **cp);
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c +1 -3
@@ -106,14 +106,12 @@ static bool dce80_enable_display_power_gating(return false; } -bool dce80_hw_sequencer_construct (struct dc *dc) +void dce80_hw_sequencer_construct (struct dc *dc) {dce110_hw_sequencer_construct (dc); dc->hwss.enable_display_power_gating = dce80_enable_display_power_gating; dc->hwss.pipe_control_lock = dce_pipe_control_lock; dc->hwss.set_bandwidth = dce100_set_bandwidth; - -return true; }
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.h +1 -1
@@ -30,7 +30,7 @@struct dc ; -bool dce80_hw_sequencer_construct (struct dc *dc); +void dce80_hw_sequencer_construct (struct dc *dc);#endif /* __DC_HWSS_DCE80_H__ */
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +3 -6
@@ -910,8 +910,7 @@ static bool dce80_construct( goto res_create_fail;/* Create hardware sequencer */ -if (!dce80_hw_sequencer_construct (dc)) - goto res_create_fail; +dce80_hw_sequencer_construct (dc);return true;
@@ -1075,8 +1074,7 @@ static bool dce81_construct( goto res_create_fail;/* Create hardware sequencer */ -if (!dce80_hw_sequencer_construct (dc)) - goto res_create_fail; +dce80_hw_sequencer_construct (dc);return true;
@@ -1236,8 +1234,7 @@ static bool dce83_construct( goto res_create_fail;/* Create hardware sequencer */ -if (!dce80_hw_sequencer_construct (dc)) - goto res_create_fail; +dce80_hw_sequencer_construct (dc);return true;
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +1 -3
@@ -397,7 +397,7 @@ static const struct transform_funcs dcn10_dpp_funcs = {/* Constructor, Destructor */ /*****************************************/ -bool dcn10_dpp_construct( +void dcn10_dpp_construct( struct dcn10_dpp *xfm, struct dc_context *ctx, uint32_t inst,
@@ -421,6 +421,4 @@ bool dcn10_dpp_construct( xfm->lb_bits_per_entry =LB_BITS_PER_ENTRY ; xfm->lb_memory_size =LB_TOTAL_NUMBER_OF_ENTRIES ;/*0x1404*/ - -return true; }
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h +1 -1
@@ -1356,7 +1356,7 @@ void ippn10_cnv_setup (void ippn10_full_bypass (struct transform *xfm_base); -bool dcn10_dpp_construct(struct dcn10_dpp *xfm110, +void dcn10_dpp_construct(struct dcn10_dpp *xfm110, struct dc_context *ctx, uint32_t inst, const struct dcn_dpp_registers *tf_regs,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c +1 -3
@@ -786,7 +786,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {/* Constructor, Destructor */ /*****************************************/ -bool dcn10_mem_input_construct( +void dcn10_mem_input_construct( struct dcn10_mem_input *mi, struct dc_context *ctx, uint32_t inst,
@@ -802,7 +802,5 @@ bool dcn10_mem_input_construct( mi->base.inst = inst; mi->base.opp_id =0xf ; mi->base.mpcc_id =0xf ; - -return true; }
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h +1 -1
@@ -538,7 +538,7 @@ struct dcn10_mem_input {const struct dcn_mi_mask *mi_mask; }; -bool dcn10_mem_input_construct( +void dcn10_mem_input_construct( struct dcn10_mem_input *mi, struct dc_context *ctx, uint32_t inst,
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +6 -14
@@ -462,13 +462,9 @@ static struct transform *dcn10_dpp_create(if (!dpp)return NULL ; -if (dcn10_dpp_construct (dpp, ctx, inst, - &tf_regs[inst], &tf_shift, &tf_mask)) -return &dpp->base; - -BREAK_TO_DEBUGGER (); -kfree (dpp); -return NULL ; +dcn10_dpp_construct (dpp, ctx, inst, + &tf_regs[inst], &tf_shift, &tf_mask); +return &dpp->base; } static struct input_pixel_processor *dcn10_ipp_create(
@@ -771,13 +767,9 @@ static struct mem_input *dcn10_mem_input_create(if (!mem_inputn10)return NULL ; -if (dcn10_mem_input_construct (mem_inputn10, ctx, inst, - &mi_regs[inst], &mi_shift, &mi_mask)) -return &mem_inputn10->base; - -BREAK_TO_DEBUGGER (); -kfree (mem_inputn10); -return NULL ; +dcn10_mem_input_construct (mem_inputn10, ctx, inst, + &mi_regs[inst], &mi_shift, &mi_mask); +return &mem_inputn10->base; } static void get_pixel_clock_parameters(
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 7/9 amdgpu/dc: remove pointless return from build_pipe_hw_param
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
This never returned anything else.
--- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 10 ++-------- drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h | 2 +- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 6 +----- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 11 ++--------- 6 files changed, 8 insertions(+), 33 deletions(-)
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +1 -5
@@ -631,16 +631,12 @@ static enum dc_status build_mapped_resource(struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);if (!pipe_ctx)return DC_ERROR_UNEXPECTED ; - status =dce110_resource_build_pipe_hw_param (pipe_ctx); - -if (status !=DC_OK ) -return status; +dce110_resource_build_pipe_hw_param (pipe_ctx);resource_build_info_frame (pipe_ctx);
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +2 -8
@@ -724,7 +724,7 @@ static void get_pixel_clock_parameters( } } -enum dc_status dce110_resource_build_pipe_hw_param (struct pipe_ctx *pipe_ctx) +void dce110_resource_build_pipe_hw_param (struct pipe_ctx *pipe_ctx) {get_pixel_clock_parameters (pipe_ctx, &pipe_ctx->stream_res.pix_clk_params); pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
@@ -734,8 +734,6 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)resource_build_bit_depth_reduction_params (pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; - -return DC_OK ; }static bool is_surface_pixel_format_supported (struct pipe_ctx *pipe_ctx,unsigned int underlay_idx)
@@ -754,7 +752,6 @@ static enum dc_status build_mapped_resource(struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);if (!pipe_ctx)
@@ -764,10 +761,7 @@ static enum dc_status build_mapped_resource( dc->res_pool->underlay_pipe_index))return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED ; - status =dce110_resource_build_pipe_hw_param (pipe_ctx); - -if (status !=DC_OK ) -return status; +dce110_resource_build_pipe_hw_param (pipe_ctx);/* TODO: validate audio ASIC caps, encoder */
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.h +1 -1
@@ -38,7 +38,7 @@ struct dce110_resource_pool {struct resource_pool base; }; -enum dc_status dce110_resource_build_pipe_hw_param (struct pipe_ctx *pipe_ctx); +void dce110_resource_build_pipe_hw_param (struct pipe_ctx *pipe_ctx); struct resource_pool *dce110_create_resource_pool( uint8_t num_virtual_links,
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +1 -5
@@ -704,16 +704,12 @@ static enum dc_status build_mapped_resource(struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);if (!pipe_ctx)return DC_ERROR_UNEXPECTED ; - status =dce110_resource_build_pipe_hw_param (pipe_ctx); - -if (status !=DC_OK ) -return status; +dce110_resource_build_pipe_hw_param (pipe_ctx);resource_build_info_frame (pipe_ctx);
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +1 -5
@@ -665,16 +665,12 @@ static enum dc_status build_mapped_resource(struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);if (!pipe_ctx)return DC_ERROR_UNEXPECTED ; - status =dce110_resource_build_pipe_hw_param (pipe_ctx); - -if (status !=DC_OK ) -return status; +dce110_resource_build_pipe_hw_param (pipe_ctx);resource_build_info_frame (pipe_ctx);
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +2 -9
@@ -805,7 +805,7 @@ static void build_clamping_params(struct dc_stream_state *stream) stream->clamping.pixel_encoding = stream->timing.pixel_encoding; } -static enum dc_status build_pipe_hw_param (struct pipe_ctx *pipe_ctx) +static void build_pipe_hw_param (struct pipe_ctx *pipe_ctx) {get_pixel_clock_parameters (pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
@@ -820,8 +820,6 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)resource_build_bit_depth_reduction_params (pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params);build_clamping_params (pipe_ctx->stream); - -return DC_OK ; } static enum dc_status build_mapped_resource(
@@ -829,7 +827,6 @@ static enum dc_status build_mapped_resource(struct dc_state *context, struct dc_stream_state *stream) { - enum dc_status status = DC_OK; struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);/*TODO Seems unneeded anymore */
@@ -853,11 +850,7 @@ static enum dc_status build_mapped_resource(if (!pipe_ctx)return DC_ERROR_UNEXPECTED ; - status =build_pipe_hw_param (pipe_ctx); - -if (status !=DC_OK ) -return status; - +build_pipe_hw_param (pipe_ctx);return DC_OK ; }
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 8/9 amdgpu: fixup construct to void paths on some more dc objects.
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
--- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 10 +++------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 18 +++++------------- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 15 +++------------ 3 files changed, 11 insertions(+), 32 deletions(-)
drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +3 -7
@@ -245,7 +245,7 @@ void dal_ddc_aux_payloads_add( } } -static bool construct ( +static void construct (struct ddc_service *ddc_service,struct ddc_service_init_data *init_data) {
@@ -282,7 +282,6 @@ static bool construct( connector_id ==CONNECTOR_ID_LVDS ; ddc_service->wa.raw =0 ; -return true; } struct ddc_service *dal_ddc_service_create(
@@ -295,11 +294,8 @@ struct ddc_service *dal_ddc_service_create(if (!ddc_service)return NULL ; -if (construct (ddc_service, init_data)) -return ddc_service; - -kfree (ddc_service); -return NULL ; +construct (ddc_service, init_data); +return ddc_service; }static void destruct (struct ddc_service *ddc)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c +5 -13
@@ -56,7 +56,7 @@ static void update_stream_signal(struct dc_stream_state *stream) } } -static bool construct (struct dc_stream_state *stream, +static void construct (struct dc_stream_state *stream,struct dc_sink *dc_sink_data) {uint32_t i =0 ;
@@ -104,7 +104,6 @@ static bool construct(struct dc_stream_state *stream, stream->status.link = stream->sink->link;update_stream_signal (stream); -return true; }static void destruct (struct dc_stream_state *stream)
@@ -142,25 +141,18 @@ struct dc_stream_state *dc_create_stream_for_sink(struct dc_stream_state *stream;if (sink ==NULL ) - goto alloc_fail; +return NULL ; stream =kzalloc (sizeof (struct dc_stream_state ),GFP_KERNEL ); +if (stream ==NULL ) +return NULL ; -if (NULL == stream) - goto alloc_fail; - -if (false ==construct (stream, sink)) - goto construct_fail; +construct (stream, sink);atomic_inc (&stream->ref_count);return stream; -construct_fail: -kfree (stream); - -alloc_fail: -return NULL ; } struct dc_stream_status *dc_stream_get_status(
drivers/gpu/drm/amd/display/dc/core/dc_surface.c +3 -12
@@ -34,12 +34,11 @@/******************************************************************************* * Private functions ******************************************************************************/ -static bool construct (struct dc_context *ctx,struct dc_plane_state *plane_state) +static void construct (struct dc_context *ctx,struct dc_plane_state *plane_state) { plane_state->ctx = ctx;memset (&plane_state->hdr_static_ctx,0 ,sizeof (struct dc_hdr_static_metadata )); -return true; }static void destruct (struct dc_plane_state *plane_state)
@@ -72,20 +71,12 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) GFP_KERNEL);if (NULL == plane_state) - goto alloc_fail; - -if (false ==construct (core_dc->ctx, plane_state)) - goto construct_fail; +return NULL ; +construct (core_dc->ctx, plane_state);atomic_inc (&plane_state->ref_count);return plane_state; - -construct_fail: -kfree (plane_state); - -alloc_fail: -return NULL ; } const struct dc_plane_status *dc_plane_get_status(
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
PATCH 9/9 amdgpu/dc: fix construct return values on irq service.
In reply to a message not in the archiveFrom: Dave Airlie <[email protected]>
This just removes more unused return/errors paths.
--- .../gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c | 14 ++++---------- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 9 +++++---- drivers/gpu/drm/amd/display/dc/irq/irq_service.h | 2 +- 6 files changed, 22 insertions(+), 45 deletions(-)
drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +4 -10
@@ -406,17 +406,14 @@ static const struct irq_service_funcs irq_service_funcs_dce110 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce110; irq_service->funcs = &irq_service_funcs_dce110; - -return true; } struct irq_service *dal_irq_service_dce110_create(
@@ -428,9 +425,6 @@ struct irq_service *dal_irq_service_dce110_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }
drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +4 -10
@@ -265,17 +265,14 @@ static const struct irq_service_funcs irq_service_funcs_dce120 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce120; irq_service->funcs = &irq_service_funcs_dce120; - -return true; } struct irq_service *dal_irq_service_dce120_create(
@@ -287,9 +284,6 @@ struct irq_service *dal_irq_service_dce120_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }
drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +4 -10
@@ -277,17 +277,14 @@ static const struct irq_service_funcs irq_service_funcs_dce80 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce80; irq_service->funcs = &irq_service_funcs_dce80; - -return true; } struct irq_service *dal_irq_service_dce80_create(
@@ -299,11 +296,8 @@ struct irq_service *dal_irq_service_dce80_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }
drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +4 -10
@@ -332,17 +332,14 @@ static const struct irq_service_funcs irq_service_funcs_dcn10 = { .to_dal_irq_source = to_dal_irq_source_dcn10 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dcn10; irq_service->funcs = &irq_service_funcs_dcn10; - -return true; } struct irq_service *dal_irq_service_dcn10_create(
@@ -354,9 +351,6 @@ struct irq_service *dal_irq_service_dcn10_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }
drivers/gpu/drm/amd/display/dc/irq/irq_service.c +5 -4
@@ -48,15 +48,16 @@#define CTX \ irq_service->ctx -bool dal_irq_service_construct ( +void dal_irq_service_construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!init_data || !init_data->ctx) -return false; +if (!init_data || !init_data->ctx) { +BREAK_TO_DEBUGGER (); +return ; + } irq_service->ctx = init_data->ctx; -return true; }void dal_irq_service_destroy (struct irq_service **irq_service)
drivers/gpu/drm/amd/display/dc/irq/irq_service.h +1 -1
@@ -69,7 +69,7 @@ struct irq_service {const struct irq_service_funcs *funcs; }; -bool dal_irq_service_construct ( +void dal_irq_service_construct (struct irq_service *irq_service,struct irq_service_init_data *init_data);
Signature · 6 lines
2.9.4 _______________________________________________ amd-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Harry Wentland
Reviewed-byRe: [PATCH 9/9] amdgpu/dc: fix construct return values on irq service.
In reply to a message not in the archiveQuoted 5 lines · Dave Airlie
From: Dave Airlie <[email protected]>
This just removes more unused return/errors paths.
Signed-off-by Dave Airlie <[email protected]>
Series is
Harry
Quoted 186 lines
--- .../gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c | 14 ++++---------- .../gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c | 14 ++++---------- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 9 +++++---- drivers/gpu/drm/amd/display/dc/irq/irq_service.h | 2 +- 6 files changed, 22 insertions(+), 45 deletions(-)drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +4
-10@@ -406,17 +406,14 @@ static const struct irq_service_funcs irq_service_funcs_dce110 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce110; irq_service->funcs = &irq_service_funcs_dce110; - -return true; } struct irq_service *dal_irq_service_dce110_create(@@ -428,9 +425,6 @@ struct irq_service *dal_irq_service_dce110_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +4
-10@@ -265,17 +265,14 @@ static const struct irq_service_funcs irq_service_funcs_dce120 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce120; irq_service->funcs = &irq_service_funcs_dce120; - -return true; } struct irq_service *dal_irq_service_dce120_create(@@ -287,9 +284,6 @@ struct irq_service *dal_irq_service_dce120_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +4
-10@@ -277,17 +277,14 @@ static const struct irq_service_funcs irq_service_funcs_dce80 = { .to_dal_irq_source = to_dal_irq_source_dce110 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dce80; irq_service->funcs = &irq_service_funcs_dce80; - -return true; } struct irq_service *dal_irq_service_dce80_create(@@ -299,11 +296,8 @@ struct irq_service *dal_irq_service_dce80_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +4
-10@@ -332,17 +332,14 @@ static const struct irq_service_funcs irq_service_funcs_dcn10 = { .to_dal_irq_source = to_dal_irq_source_dcn10 }; -static bool construct ( +static void construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!dal_irq_service_construct (irq_service, init_data)) -return false; +dal_irq_service_construct (irq_service, init_data); irq_service->info = irq_source_info_dcn10; irq_service->funcs = &irq_service_funcs_dcn10; - -return true; } struct irq_service *dal_irq_service_dcn10_create(@@ -354,9 +351,6 @@ struct irq_service *dal_irq_service_dcn10_create(if (!irq_service)return NULL ; -if (construct (irq_service, init_data)) -return irq_service; - -kfree (irq_service); -return NULL ; +construct (irq_service, init_data); +return irq_service; }drivers/gpu/drm/amd/display/dc/irq/irq_service.c +5
-4@@ -48,15 +48,16 @@#define CTX \ irq_service->ctx -bool dal_irq_service_construct ( +void dal_irq_service_construct (struct irq_service *irq_service,struct irq_service_init_data *init_data) { -if (!init_data || !init_data->ctx) -return false; +if (!init_data || !init_data->ctx) { +BREAK_TO_DEBUGGER (); +return ; + } irq_service->ctx = init_data->ctx; -return true; }void dal_irq_service_destroy (struct irq_service **irq_service)drivers/gpu/drm/amd/display/dc/irq/irq_service.h +0
-0
drivers/gpu/drm/amd/display/dc/irq/irq_service.h struct irq_service { · line 75
Quoted 8 lines
drivers/gpu/drm/amd/display/dc/irq/irq_service.h +1
-1@@ -69,7 +69,7 @@ struct irq_service {const struct irq_service_funcs *funcs; }; -bool dal_irq_service_construct ( +void dal_irq_service_construct (struct irq_service *irq_service,struct irq_service_init_data *init_data);
_______________________________________________
amd-gfx mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/amd-gfx