perf/x86: Hide TSX events when no TSX
Subsystems (2)
PATCH 1/1 perf/x86: Hide TSX events when no TSX
From: Andi Kleen <[email protected]>
When TSX is not available don't show the TSX events in sysfs for Haswell/Broadwell/Skylake.
This fixes a perf test regression reported by 0day on Haswell systems without RTM. The earlier a5df70c35 patch hid the t/ct attributes in this case, so their attributes cannot be parsed anymore.
Fixes a5df70c354c2 (perf/x86: Only show format attributes when supported)
Tested-by Jin Yao <[email protected]>
Signed-off-by Andi Kleen <[email protected]>
--- arch/x86/events/intel/core.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-)
arch/x86/events/intel/core.c +23 -12
@@ -3734,6 +3734,19 @@ EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");EVENT_ATTR_STR (cycles-ct, cycles_ct,"event=0x3c,in_tx=1,in_tx_cp=1" );static struct attribute *hsw_events_attrs[] = { +EVENT_PTR (mem_ld_hsw), +EVENT_PTR (mem_st_hsw), +EVENT_PTR (td_slots_issued), +EVENT_PTR (td_slots_retired), +EVENT_PTR (td_fetch_bubbles), +EVENT_PTR (td_total_slots), +EVENT_PTR (td_total_slots_scale), +EVENT_PTR (td_recovery_bubbles), +EVENT_PTR (td_recovery_bubbles_scale), +NULL +}; + +static struct attribute *hsw_tsx_events_attrs[] = {EVENT_PTR (tx_start),EVENT_PTR (tx_commit),EVENT_PTR (tx_abort),
@@ -3746,18 +3759,16 @@ static struct attribute *hsw_events_attrs[] = {EVENT_PTR (el_conflict),EVENT_PTR (cycles_t),EVENT_PTR (cycles_ct), -EVENT_PTR (mem_ld_hsw), -EVENT_PTR (mem_st_hsw), -EVENT_PTR (td_slots_issued), -EVENT_PTR (td_slots_retired), -EVENT_PTR (td_fetch_bubbles), -EVENT_PTR (td_total_slots), -EVENT_PTR (td_total_slots_scale), -EVENT_PTR (td_recovery_bubbles), -EVENT_PTR (td_recovery_bubbles_scale), NULL }; +static __init struct attribute **get_hsw_events_attrs (void ) +{ +return boot_cpu_has (X86_FEATURE_RTM ) ? +merge_attr (hsw_events_attrs, hsw_tsx_events_attrs) : + hsw_events_attrs; +} +static ssize_t freeze_on_smi_show (struct device *cdev,struct device_attribute *attr,char *buf)
@@ -4186,7 +4197,7 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs (); x86_pmu.lbr_double_abort = true; extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr;
@@ -4225,7 +4236,7 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs (); x86_pmu.limit_period = bdw_limit_period; extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr;
@@ -4283,7 +4294,7 @@ __init int intel_pmu_init(void) extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr; extra_attr =merge_attr (extra_attr, skl_format_attr); - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs ();intel_pmu_pebs_data_source_skl ( boot_cpu_data.x86_model ==INTEL_FAM6_SKYLAKE_X );pr_cont ("Skylake events, " );
Signature · 1 line
2.13.6
tip-bot for Andi Kleen
merge bot[tip:perf/urgent] perf/x86/intel: Hide TSX events when RTM is not supported
perf/x86/intel: Hide TSX events when RTM is not supported
Commit-ID: 58ba4d5a25579e5c7e312bd359c95f3a9a0a242c Gitweb: https://git.kernel.org/tip/58ba4d5a25579e5c7e312bd359c95f3a9a0a242c Author: Andi Kleen <[email protected]> AuthorDate: Wed, 8 Nov 2017 16:07:18 -0800 Committer: Thomas Gleixner <[email protected]> CommitDate: Mon, 13 Nov 2017 17:03:38 +0100
perf/x86/intel: Hide TSX events when RTM is not supported
0day testing reported a perf test regression on Haswell systems without RTM. Commit a5df70c35 hides the in_tx/in_tx_cp attributes when RTM is not available, but the TSX events are still available in sysfs. Due to the missing attributes the event parser fails on those files.
Don't show the TSX events in sysfs when RTM is not available on Haswell/Broadwell/Skylake.
Fixes a5df70c354c2 (perf/x86: Only show format attributes when supported)
Reported-by kernel test robot <[email protected]>
Tested-by Jin Yao <[email protected]>
Signed-off-by Andi Kleen <[email protected]>
Signed-off-by Thomas Gleixner <[email protected]>
Acked-by Peter Zijlstra <[email protected]>
--- arch/x86/events/intel/core.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-)
arch/x86/events/intel/core.c +23 -12
@@ -3730,6 +3730,19 @@ EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");EVENT_ATTR_STR (cycles-ct, cycles_ct,"event=0x3c,in_tx=1,in_tx_cp=1" );static struct attribute *hsw_events_attrs[] = { +EVENT_PTR (mem_ld_hsw), +EVENT_PTR (mem_st_hsw), +EVENT_PTR (td_slots_issued), +EVENT_PTR (td_slots_retired), +EVENT_PTR (td_fetch_bubbles), +EVENT_PTR (td_total_slots), +EVENT_PTR (td_total_slots_scale), +EVENT_PTR (td_recovery_bubbles), +EVENT_PTR (td_recovery_bubbles_scale), +NULL +}; + +static struct attribute *hsw_tsx_events_attrs[] = {EVENT_PTR (tx_start),EVENT_PTR (tx_commit),EVENT_PTR (tx_abort),
@@ -3742,18 +3755,16 @@ static struct attribute *hsw_events_attrs[] = {EVENT_PTR (el_conflict),EVENT_PTR (cycles_t),EVENT_PTR (cycles_ct), -EVENT_PTR (mem_ld_hsw), -EVENT_PTR (mem_st_hsw), -EVENT_PTR (td_slots_issued), -EVENT_PTR (td_slots_retired), -EVENT_PTR (td_fetch_bubbles), -EVENT_PTR (td_total_slots), -EVENT_PTR (td_total_slots_scale), -EVENT_PTR (td_recovery_bubbles), -EVENT_PTR (td_recovery_bubbles_scale), NULL }; +static __init struct attribute **get_hsw_events_attrs (void ) +{ +return boot_cpu_has (X86_FEATURE_RTM ) ? +merge_attr (hsw_events_attrs, hsw_tsx_events_attrs) : + hsw_events_attrs; +} +static ssize_t freeze_on_smi_show (struct device *cdev,struct device_attribute *attr,char *buf)
@@ -4182,7 +4193,7 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs (); x86_pmu.lbr_double_abort = true; extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr;
@@ -4221,7 +4232,7 @@ __init int intel_pmu_init(void) x86_pmu.hw_config = hsw_hw_config; x86_pmu.get_event_constraints = hsw_get_event_constraints; - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs (); x86_pmu.limit_period = bdw_limit_period; extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr;
@@ -4279,7 +4290,7 @@ __init int intel_pmu_init(void) extra_attr =boot_cpu_has (X86_FEATURE_RTM ) ? hsw_format_attr : nhm_format_attr; extra_attr =merge_attr (extra_attr, skl_format_attr); - x86_pmu.cpu_events = hsw_events_attrs; + x86_pmu.cpu_events =get_hsw_events_attrs ();intel_pmu_pebs_data_source_skl ( boot_cpu_data.x86_model ==INTEL_FAM6_SKYLAKE_X );pr_cont ("Skylake events, " );