arm: mvebu: correct comments around cas_wl/cas_l

PATCH New Chris Packham 2 participants 3 messages Nov 28, 2017 – Nov 30, 2017

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Chris Packham

author

2017-11-28 21:38 UTC #0 lore raw

PATCH 1/1 arm: mvebu: correct comments around cas_wl/cas_l

The order of members in struct hws_topology_map is cas_wl, cas_l. The comments in the original db-88f6820-gp.c had this wrong and have been copied to other Armada-385 based boards. Practically this hasn't made a difference since all these boards set both cas_wl and cas_l to 0 (autodetect) but if there were ever a board that did need to set these explicitly they would run into unexpected issued.

Update the comments to reflect the correct order of structure members.

Reported-by Tobi Wulff <[email protected]>

Signed-off-by Chris Packham <[email protected]>

---

 board/CZ.NIC/turris_omnia/turris_omnia.c      | 4 ++--
 board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 2 +-
 board/Marvell/db-88f6820-gp/db-88f6820-gp.c   | 2 +-
 board/gdsys/a38x/controlcenterdc.c            | 2 +-
 board/solidrun/clearfog/clearfog.c            | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

board/CZ.NIC/turris_omnia/turris_omnia.c +2 -2

index af66837909de..b03c0a3714b1 100644
@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_NORMAL,		/* temperature */
 	    HWS_TIM_2T} },		/* timing (force 2t) */
 	5,				/* Num Of Bus Per Interface*/

@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_8G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_NORMAL,		/* temperature */
 	    HWS_TIM_2T} },		/* timing (force 2t) */
 	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +1 -1

index ac58f9085266..7db0095f75ef 100644
@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_8,		/* memory_width */
 	    MEM_2G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-gp/db-88f6820-gp.c +1 -1

index a1974cb4bd21..b95cd1d4aab5 100644
@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_8,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/gdsys/a38x/controlcenterdc.c +1 -1

index 32168d35768a..3d74a6dfb897 100644
@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_533,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

board/solidrun/clearfog/clearfog.c +1 -1

index 8906636f7646..1472e9793e5f 100644
@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
 	    BUS_WIDTH_16,		/* memory_width */
 	    MEM_4G,			/* mem_size */
 	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
 	    HWS_TEMP_LOW,		/* temperature */
 	    HWS_TIM_DEFAULT} },		/* timing */
 	5,				/* Num Of Bus Per Interface*/

Signature · 1 line

2.15.0

Stefan Roese

2017-11-29 10:32 UTC #1 lore raw

PATCH 1/1 arm: mvebu: correct comments around cas_wl/cas_l

Quoted 87 lines · Chris Packham

Update the comments to reflect the correct order of structure members.

Reported-by Tobi Wulff <[email protected]>

Signed-off-by Chris Packham <[email protected]>

---

  board/CZ.NIC/turris_omnia/turris_omnia.c      | 4 ++--
  board/Marvell/db-88f6820-amc/db-88f6820-amc.c | 2 +-
  board/Marvell/db-88f6820-gp/db-88f6820-gp.c   | 2 +-
  board/gdsys/a38x/controlcenterdc.c            | 2 +-
  board/solidrun/clearfog/clearfog.c            | 2 +-
  5 files changed, 6 insertions(+), 6 deletions(-)

board/CZ.NIC/turris_omnia/turris_omnia.c +2 -2

index af66837909de..b03c0a3714b1 100644
@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
  	    BUS_WIDTH_16,		/* memory_width */
  	    MEM_4G,			/* mem_size */
  	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_NORMAL,		/* temperature */
  	    HWS_TIM_2T} },		/* timing (force 2t) */
  	5,				/* Num Of Bus Per Interface*/

@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
  	    BUS_WIDTH_16,		/* memory_width */
  	    MEM_8G,			/* mem_size */
  	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_NORMAL,		/* temperature */
  	    HWS_TIM_2T} },		/* timing (force 2t) */
  	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-amc/db-88f6820-amc.c +1 -1

index ac58f9085266..7db0095f75ef 100644
@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
  	    BUS_WIDTH_8,		/* memory_width */
  	    MEM_2G,			/* mem_size */
  	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_LOW,		/* temperature */
  	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per Interface*/

board/Marvell/db-88f6820-gp/db-88f6820-gp.c +1 -1

index a1974cb4bd21..b95cd1d4aab5 100644
@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
  	    BUS_WIDTH_8,		/* memory_width */
  	    MEM_4G,			/* mem_size */
  	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_LOW,		/* temperature */
  	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per Interface*/

board/gdsys/a38x/controlcenterdc.c +1 -1

index 32168d35768a..3d74a6dfb897 100644
@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
  	    BUS_WIDTH_16,		/* memory_width */
  	    MEM_4G,			/* mem_size */
  	    DDR_FREQ_533,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_LOW,		/* temperature */
  	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per Interface*/

board/solidrun/clearfog/clearfog.c +0 -0

index 8906636f7646..1472e9793e5f 100644

board/solidrun/clearfog/clearfog.c static struct hws_topology_map board_topology_map = { · line 88

Quoted 8 lines

board/solidrun/clearfog/clearfog.c +1 -1

@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
  	    BUS_WIDTH_16,		/* memory_width */
  	    MEM_4G,			/* mem_size */
  	    DDR_FREQ_800,		/* frequency */
-	    0, 0,			/* cas_l cas_wl */
+	    0, 0,			/* cas_wl cas_l */
  	    HWS_TEMP_LOW,		/* temperature */
  	    HWS_TIM_DEFAULT} },		/* timing */
  	5,				/* Num Of Bus Per Interface*/

Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

Stefan Roese

2017-11-30 12:30 UTC #2 lore raw

PATCH 1/1 arm: mvebu: correct comments around cas_wl/cas_l

In reply to Chris Packham

Quoted 11 lines · Chris Packham

The order of members in struct hws_topology_map is cas_wl, cas_l. The comments in the original db-88f6820-gp.c had this wrong and have been copied to other Armada-385 based boards. Practically this hasn't made a difference since all these boards set both cas_wl and cas_l to 0 (autodetect) but if there were ever a board that did need to set these explicitly they would run into unexpected issued.
Update the comments to reflect the correct order of structure members.
Reported-by Tobi Wulff <[email protected]>
Signed-off-by Chris Packham <[email protected]>

Applied to u-boot-marvell/master.

Thanks,
Stefan