IR support for A83T - sunxi-ir driver update
Subsystems (4)
cover IR support for A83T - sunxi-ir driver update
This patch series adds support for the sunxi A83T ir module and enhances the sunxi-ir driver. Right now the base clock frequency for the ir driver is a hard coded define and is set to 8 MHz. This works for the most common ir receivers. On the Sinovoip Bananapi M3 the ir receiver needs, a 3 MHz base clock frequency to work without problems with this driver (like in the legacy kernel).
To fix this issue I reworked the driver that this value could be set over the devicetree.
About 37 devices would have a devicetree change if this patch series would be applied. Therfore I would like to ask you to give me some feedback about the patch series, before I finialize it.
Thanks in advance!
Philipp
Philipp Rossak (5):
[media] rc: update sunxi-ir driver to get base frequency from
devicetree
[media] dt: bindings: Update binding documentation for sunxi IR
controller
ARM: dts: sun8i: a83t: Add the ir pin for the A83T
ARM: dts: sun8i: a83t: Add support for the ir interface
ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 ++++++++------ arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++ arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ drivers/media/rc/sunxi-cir.c | 20 +++++++++++--------- 4 files changed, 41 insertions(+), 15 deletions(-)
Signature · 1 line
2.11.0
RFC 1/5 rc: update sunxi-ir driver to get base frequency from devicetree
This patch updates the sunxi-ir driver to set the ir base clock from devicetree.
This is neccessary since there are different ir recievers on the market, that operate with different frequencys. So this value needs to be set depending on the attached receiver.
--- drivers/media/rc/sunxi-cir.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)
drivers/media/rc/sunxi-cir.c +11 -9
@@ -72,12 +72,6 @@/* CIR_REG register idle threshold */ #define REG_CIR_ITHR (val) (((val) << 8) & (GENMASK(15, 8))) -/* Required frequency for IR0 or IR1 clock in CIR mode */ -#define SUNXI_IR_BASE_CLK 8000000 -/* Frequency after IR internal divider */ -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64) -/* Sample period in ns */ -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)/* Noise threshold in samples */ #define SUNXI_IR_RXNOISE 1/* Idle Threshold in samples */
@@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)/* for each bit in fifo */ dt =readb (ir->base +SUNXI_IR_RXFIFO_REG ); rawir.pulse = (dt &0x80 ) !=0 ; - rawir.duration = ((dt &0x7f ) +1 ) *SUNXI_IR_SAMPLE ; + rawir.duration = ((dt &0x7f ) +1 ) * ir->rc->rx_resolution;ir_raw_event_store_with_filter (ir->rc, &rawir); } }
@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)struct device_node *dn = dev->of_node;struct resource *res;struct sunxi_ir *ir; +u32 b_clk_freq; ir =devm_kzalloc (dev,sizeof (struct sunxi_ir ),GFP_KERNEL );if (!ir)
@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)return PTR_ERR (ir->clk); } +/* Required frequency for IR0 or IR1 clock in CIR mode */ +if (of_property_read_u32 (dn,"base-clk-frequency" , &b_clk_freq)) { +dev_err (dev,"failed to get ir base clock frequency.\n" ); +return -ENODATA ; + } +/* Reset (optional) */ ir->rst =devm_reset_control_get_optional_exclusive (dev,NULL );if (IS_ERR (ir->rst))
@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)if (ret)return ret; - ret =clk_set_rate (ir->clk,SUNXI_IR_BASE_CLK ); + ret =clk_set_rate (ir->clk, b_clk_freq);if (ret) {dev_err (dev,"set ir base clock failed!\n" ); goto exit_reset_assert;
@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rc->map_name = ir->map_name ?:RC_MAP_EMPTY ; ir->rc->dev.parent = dev; ir->rc->allowed_protocols =RC_PROTO_BIT_ALL_IR_DECODER ; - ir->rc->rx_resolution =SUNXI_IR_SAMPLE ; +/* Frequency after IR internal divider with sample period in ns */ + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq /64 )); ir->rc->timeout =MS_TO_NS (SUNXI_IR_TIMEOUT ); ir->rc->driver_name =SUNXI_IR_DEV ;
Signature · 1 line
2.11.0
RFC 2/5 dt: bindings: Update binding documentation for sunxi IR controller
In reply to Philipp RossakThis patch updates documentation for Device-Tree bindings for sunxi IR controller and adds the new requiered property for the base clock frequency.
--- Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)
Documentation/devicetree/bindings/media/sunxi-ir.txt +8 -6
@@ -1,12 +1,13 @@ Device-Tree bindings for SUNXI IR controller found in sunXi SoC family Required properties: -- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" -- clocks : list of clock specifiers, corresponding to - entries in clock-names property; -- clock-names : should contain "apb" and "ir" entries; -- interrupts : should contain IR IRQ number; -- reg : should contain IO map address for IR. +- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" +- clocks : list of clock specifiers, corresponding to + entries in clock-names property; +- clock-names : should contain "apb" and "ir" entries; +- interrupts : should contain IR IRQ number; +- reg : should contain IO map address for IR. +- base-clk-frequency : should contain the base clock frequency Optional properties: - linux,rc-map-name: see rc.txt file in the same directory.
@@ -21,5 +22,6 @@ ir0: ir at 1c21800 { resets = <&apb0_rst 1>; interrupts = <0 5 1>; reg = <0x01C21800 0x40>; + base-clk-frequency = <8000000>; linux,rc-map-name = "rc-rc6-mce"; };
Signature · 1 line
2.11.0
RFC 3/5 ARM: dts: sun8i: a83t: Add the ir pin for the A83T
In reply to Philipp RossakThe CIR Pin of the A83T is located at PL12
--- arch/arm/boot/dts/sun8i-a83t.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/sun8i-a83t.dtsi +5 -0
@@ -488,6 +488,11 @@ drive-strength = <20>; bias-pull-up; }; + + ir_pins_a: ir at 0 { + pins = "PL12"; + function = "s_cir_rx"; + }; }; r_rsb: rsb at 1f03400 {
Signature · 1 line
2.11.0
RFC 4/5 ARM: dts: sun8i: a83t: Add support for the ir interface
In reply to Philipp RossakThe ir interface is like the H3 at 0x01f02000 located and is exactly the same. This patch adds support for the ir interface on the A83T.
--- arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/sun8i-a83t.dtsi +10 -0
@@ -470,6 +470,16 @@ #reset-cells = <1>; }; + ir: ir at 01f02000 { + compatible = "allwinner,sun5i-a13-ir"; + clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; + clock-names = "apb", "ir"; + resets = <&r_ccu RST_APB0_IR>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x01f02000 0x40>; + status = "disabled"; + }; + r_pio: pinctrl at 1f02c00 { compatible = "allwinner,sun8i-a83t-r-pinctrl"; reg = <0x01f02c00 0x400>;
Signature · 1 line
2.11.0
RFC 5/5 ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller
In reply to Philipp RossakThe Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Other than the other IR receivers this one needs a base clock frequency of 3000000 Hz (3 MHz), to be able to work.
--- arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++ arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-)
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +7 -0
@@ -88,6 +88,13 @@ /* TODO GL830 USB-to-SATA bridge downstream w/ GPIO power controls */ }; +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + base-clk-frequency = <3000000>; + status = "okay"; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>;
arch/arm/boot/dts/sun8i-a83t.dtsi +1 -1
@@ -470,7 +470,7 @@ #reset-cells = <1>; }; - ir: ir at 01f02000 { + ir: ir at 1f02000 { compatible = "allwinner,sun5i-a13-ir"; clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; clock-names = "apb", "ir";
Signature · 1 line
2.11.0
Mauro Carvalho Chehab
maintainerRe: [RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
In reply to Philipp RossakEm Sat, 16 Dec 2017 03:49:10 +0100
Philipp Rossak <[email protected]> escreveu:
Hi Phillip,
This is not a full review of this patchset. I just want to point you that you should keep supporting existing DT files.
Quoted 6 lines
This patch updates the sunxi-ir driver to set the ir base clock from devicetree.
This is neccessary since there are different ir recievers on the market, that operate with different frequencys. So this value needs to be set depending on the attached receiver.
Please don't break backward compatibility with old DT files. In this specific case, it seems simple enough to be backward-compatible.
Quoted 11 lines
Signed-off-by Philipp Rossak <[email protected]>--- drivers/media/rc/sunxi-cir.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)drivers/media/rc/sunxi-cir.c +0
-0
drivers/media/rc/sunxi-cir.c line 78
Quoted 7 lines
drivers/media/rc/sunxi-cir.c +0
-4@@ -72,12 +72,6 @@/* CIR_REG register idle threshold */ #define REG_CIR_ITHR (val) (((val) << 8) & (GENMASK(15, 8))) -/* Required frequency for IR0 or IR1 clock in CIR mode */ -#define SUNXI_IR_BASE_CLK 8000000 -/* Frequency after IR internal divider */ -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)
Keep those to definitions...
Quoted 23 lines
drivers/media/rc/sunxi-cir.c +2
-3-/* Sample period in ns */ -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)/* Noise threshold in samples */ #define SUNXI_IR_RXNOISE 1/* Idle Threshold in samples */ @@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)/* for each bit in fifo */ dt =readb (ir->base +SUNXI_IR_RXFIFO_REG ); rawir.pulse = (dt &0x80 ) !=0 ; - rawir.duration = ((dt &0x7f ) +1 ) *SUNXI_IR_SAMPLE ; + rawir.duration = ((dt &0x7f ) +1 ) * ir->rc->rx_resolution;ir_raw_event_store_with_filter (ir->rc, &rawir); } }@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)struct device_node *dn = dev->of_node;struct resource *res;struct sunxi_ir *ir; +u32 b_clk_freq; ir =devm_kzalloc (dev,sizeof (struct sunxi_ir ),GFP_KERNEL );if (!ir)
drivers/media/rc/sunxi-cir.c static int sunxi_ir_probe(struct platform_device *pdev) · line 175
Quoted 9 lines
drivers/media/rc/sunxi-cir.c +6
-0@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)return PTR_ERR (ir->clk); } +/* Required frequency for IR0 or IR1 clock in CIR mode */ +if (of_property_read_u32 (dn,"base-clk-frequency" , &b_clk_freq)) { +dev_err (dev,"failed to get ir base clock frequency.\n" ); +return -ENODATA ; + } +
And here, instead of returning an error, if the property can't be read, it means it is an older DT file. Just default to SUNXI_IR_BASE_CLK. This will make it backward-compatible with old DT files that don't have such property.
Regards,
Mauro
Quoted 13 lines
drivers/media/rc/sunxi-cir.c +1
-1/* Reset (optional) */ ir->rst =devm_reset_control_get_optional_exclusive (dev,NULL );if (IS_ERR (ir->rst))@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)if (ret)return ret; - ret =clk_set_rate (ir->clk,SUNXI_IR_BASE_CLK ); + ret =clk_set_rate (ir->clk, b_clk_freq);if (ret) {dev_err (dev,"set ir base clock failed!\n" ); goto exit_reset_assert;
drivers/media/rc/sunxi-cir.c static int sunxi_ir_probe(struct platform_device *pdev) · line 233
Quoted 9 lines
drivers/media/rc/sunxi-cir.c +2
-1@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rc->map_name = ir->map_name ?:RC_MAP_EMPTY ; ir->rc->dev.parent = dev; ir->rc->allowed_protocols =RC_PROTO_BIT_ALL_IR_DECODER ; - ir->rc->rx_resolution =SUNXI_IR_SAMPLE ; +/* Frequency after IR internal divider with sample period in ns */ + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq /64 )); ir->rc->timeout =MS_TO_NS (SUNXI_IR_TIMEOUT ); ir->rc->driver_name =SUNXI_IR_DEV ;
Thanks,
Mauro
Re: [RFC 1/5] [media] rc: update sunxi-ir driver to get base frequency from devicetree
Hey Mauro,
Thanks for your fast feedback!
I will rework the driver like you suggested it.
Does somebody have any concerns about the Devicetree property (base-clk-frequency = < frequency >;)?
Regards,
Philipp
Quoted 107 lines · Mauro Carvalho Chehab
Em Sat, 16 Dec 2017 03:49:10 +0100
Philipp Rossak <[email protected]> escreveu:Hi Phillip,
This is not a full review of this patchset. I just want to point you that you should keep supporting existing DT files.
Quoted 6 lines
This patch updates the sunxi-ir driver to set the ir base clock from devicetree.
This is neccessary since there are different ir recievers on the market, that operate with different frequencys. So this value needs to be set depending on the attached receiver.
Please don't break backward compatibility with old DT files. In this specific case, it seems simple enough to be backward-compatible.
Quoted 11 lines
Signed-off-by Philipp Rossak <[email protected]>--- drivers/media/rc/sunxi-cir.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-)drivers/media/rc/sunxi-cir.c +0
-0drivers/media/rc/sunxi-cir.c line 78
Quoted 7 lines
drivers/media/rc/sunxi-cir.c +0
-4@@ -72,12 +72,6 @@/* CIR_REG register idle threshold */ #define REG_CIR_ITHR (val) (((val) << 8) & (GENMASK(15, 8))) -/* Required frequency for IR0 or IR1 clock in CIR mode */ -#define SUNXI_IR_BASE_CLK 8000000 -/* Frequency after IR internal divider */ -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64)Keep those to definitions...
Quoted 23 lines
drivers/media/rc/sunxi-cir.c +2
-3-/* Sample period in ns */ -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK)/* Noise threshold in samples */ #define SUNXI_IR_RXNOISE 1/* Idle Threshold in samples */ @@ -122,7 +116,7 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id)/* for each bit in fifo */ dt =readb (ir->base +SUNXI_IR_RXFIFO_REG ); rawir.pulse = (dt &0x80 ) !=0 ; - rawir.duration = ((dt &0x7f ) +1 ) *SUNXI_IR_SAMPLE ; + rawir.duration = ((dt &0x7f ) +1 ) * ir->rc->rx_resolution;ir_raw_event_store_with_filter (ir->rc, &rawir); } }@@ -148,6 +142,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)struct device_node *dn = dev->of_node;struct resource *res;struct sunxi_ir *ir; +u32 b_clk_freq; ir =devm_kzalloc (dev,sizeof (struct sunxi_ir ),GFP_KERNEL );if (!ir)drivers/media/rc/sunxi-cir.c static int sunxi_ir_probe(struct platform_device *pdev) · line 175
Quoted 9 lines
drivers/media/rc/sunxi-cir.c +6
-0@@ -172,6 +167,12 @@ static int sunxi_ir_probe(struct platform_device *pdev)return PTR_ERR (ir->clk); } +/* Required frequency for IR0 or IR1 clock in CIR mode */ +if (of_property_read_u32 (dn,"base-clk-frequency" , &b_clk_freq)) { +dev_err (dev,"failed to get ir base clock frequency.\n" ); +return -ENODATA ; + } +And here, instead of returning an error, if the property can't be read, it means it is an older DT file. Just default to
SUNXI_IR_BASE_CLK. This will make it backward-compatible with old DT files that don't have such property.Regards,
MauroQuoted 13 lines
drivers/media/rc/sunxi-cir.c +1
-1/* Reset (optional) */ ir->rst =devm_reset_control_get_optional_exclusive (dev,NULL );if (IS_ERR (ir->rst))@@ -180,7 +181,7 @@ static int sunxi_ir_probe(struct platform_device *pdev)if (ret)return ret; - ret =clk_set_rate (ir->clk,SUNXI_IR_BASE_CLK ); + ret =clk_set_rate (ir->clk, b_clk_freq);if (ret) {dev_err (dev,"set ir base clock failed!\n" ); goto exit_reset_assert;drivers/media/rc/sunxi-cir.c static int sunxi_ir_probe(struct platform_device *pdev) · line 233
Quoted 9 lines
drivers/media/rc/sunxi-cir.c +2
-1@@ -225,7 +226,8 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rc->map_name = ir->map_name ?:RC_MAP_EMPTY ; ir->rc->dev.parent = dev; ir->rc->allowed_protocols =RC_PROTO_BIT_ALL_IR_DECODER ; - ir->rc->rx_resolution =SUNXI_IR_SAMPLE ; +/* Frequency after IR internal divider with sample period in ns */ + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq /64 )); ir->rc->timeout =MS_TO_NS (SUNXI_IR_TIMEOUT ); ir->rc->driver_name =SUNXI_IR_DEV ;Thanks,
Mauro
Rob Herring
maintainerRe: [RFC 2/5] [media] dt: bindings: Update binding documentation for sunxi IR controller
In reply to Philipp RossakQuoted 19 lines · Philipp Rossak
This patch updates documentation for Device-Tree bindings for sunxi IR controller and adds the new requiered property for the base clock frequency.
Signed-off-by Philipp Rossak <[email protected]>--- Documentation/devicetree/bindings/media/sunxi-ir.txt | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-)Documentation/devicetree/bindings/media/sunxi-ir.txt +0
-3@@ -1,12 +1,13 @@ Device-Tree bindings for SUNXI IR controller found in sunXi SoC family Required properties: -- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" -- clocks : list of clock specifiers, corresponding to - entries in clock-names property;
Documentation/devicetree/bindings/media/sunxi-ir.txt line 10
Quoted 10 lines
Documentation/devicetree/bindings/media/sunxi-ir.txt +7
-3-- clock-names : should contain "apb" and "ir" entries; -- interrupts : should contain IR IRQ number; -- reg : should contain IO map address for IR. +- compatible : "allwinner,sun4i-a10-ir" or "allwinner,sun5i-a13-ir" +- clocks : list of clock specifiers, corresponding to + entries in clock-names property; +- clock-names : should contain "apb" and "ir" entries; +- interrupts : should contain IR IRQ number; +- reg : should contain IO map address for IR. +- base-clk-frequency : should contain the base clock frequency
Use clock-frequency or assigned-clocks.
Rob