drm/msm/dsi: SDM845 DSI host controller and DT updates
Subsystems (5)
cover drm/msm/dsi: SDM845 DSI host controller and DT updates
This series adds some of the host controller changes needed for SDM845.\
The DT patches in the series do some minor clean ups and add missing bindings for 14nm DSI PHY (8x96) and new bindings for 10nm PHY.
Archit Taneja (7):
drm/msm/dsi: Use msm_clk_get in dsi_get_config drm/msm/dsi: Add SDM845 in dsi_cfg
drm/msm/dsi: Add byte_intf_clk
dt-bindings: display: msm/dsi: Remove unused properties
dt-bindings: display: msm/dsi: Fix the PHY regulator supply props
dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
dt-bindings: display: msm/dsi: Add updates for SDM845
.../devicetree/bindings/display/msm/dsi.txt | 26 +++++++++++---- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 19 +++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 38 +++++++++++++++++++--- 4 files changed, 74 insertions(+), 10 deletions(-)
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PATCH 1/7 drm/msm/dsi: Use msm_clk_get in dsi_get_config
We try to get the interface clock in dsi_get_config early during DSI's component bind. Try getting both the "iface" and "iface_clk" clock name variants so that we are compatible with both new and legacy DT.
--- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
drivers/gpu/drm/msm/dsi/dsi_host.c +2 -4
@@ -214,7 +214,7 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( goto exit; } - ahb_clk =clk_get (dev,"iface_clk" ); + ahb_clk =msm_clk_get (msm_host->pdev,"iface" );if (IS_ERR (ahb_clk)) {pr_err ("%s: cannot get interface clock\n" , __func__); goto put_gdsc;
@@ -225,7 +225,7 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( ret =regulator_enable (gdsc_reg);if (ret) {pr_err ("%s: unable to enable gdsc\n" , __func__); - goto put_clk; + goto put_gdsc; } ret =clk_prepare_enable (ahb_clk);
@@ -249,8 +249,6 @@ static const struct msm_dsi_cfg_handler *dsi_get_config( disable_gdsc:regulator_disable (gdsc_reg);pm_runtime_put_sync (dev); -put_clk: -clk_put (ahb_clk); put_gdsc:regulator_put (gdsc_reg); exit:
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PATCH 2/7 drm/msm/dsi: Add SDM845 in dsi_cfg
In reply to Archit TanejaSDM845 contains 2 DSI6G v2.2.1 host controllers. Add them in dsi_cfg.
--- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 19 +++++++++++++++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 20 insertions(+)
drivers/gpu/drm/msm/dsi/dsi_cfg.c +19 -0
@@ -118,6 +118,24 @@ static const struct msm_dsi_config msm8996_dsi_cfg = { .num_dsi = 2, }; +static const char *const dsi_sdm845_bus_clk_names[] = { +"iface" ,"bus" , +}; + +static const struct msm_dsi_config sdm845_dsi_cfg = { + .io_offset =DSI_6G_REG_SHIFT , + .reg_cfg = { + .num =1 , + .regs = { + {"vdda" ,21800 ,4 },/* 1.2 V */ + }, + }, + .bus_clk_names = dsi_sdm845_bus_clk_names, + .num_bus_clks =ARRAY_SIZE (dsi_sdm845_bus_clk_names), + .io_start = {0xae94000 ,0xae96000 }, + .num_dsi =2 , +}; +static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_V2 ,MSM_DSI_V2_VER_MINOR_8064 , &apq8064_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G ,MSM_DSI_6G_VER_MINOR_V1_0 ,
@@ -131,6 +149,7 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, &msm8994_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, &msm8916_dsi_cfg}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, &msm8996_dsi_cfg}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, &sdm845_dsi_cfg}, };const struct msm_dsi_cfg_handler *msm_dsi_cfg_get (u32 major,u32 minor)
drivers/gpu/drm/msm/dsi/dsi_cfg.h +1 -0
@@ -25,6 +25,7 @@#define MSM_DSI_6G_VER_MINOR_V1_3 0x10030000#define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001#define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 +#define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001#define MSM_DSI_V2_VER_MINOR_8064 0x0
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PATCH 3/7 drm/msm/dsi: Add byte_intf_clk
In reply to Archit TanejaDSI6G v2.0+ blocks have a new clock input to them called byte_intf_clk. It's rate is to be set as byte_clk / 2.
Within the clock controller (CC) subsystem, this clock is a child/descendant of the byte_clk.
Set it up as an optional clock in the DSI host driver. Make sure that we enable/set its rate only after we configure byte_clk. This is required for the ancestor clocks in the CC to be configured correctly.
--- drivers/gpu/drm/msm/dsi/dsi_host.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
drivers/gpu/drm/msm/dsi/dsi_host.c +32 -0
@@ -115,6 +115,7 @@ struct msm_dsi_host {struct clk *pixel_clk;struct clk *byte_clk_src;struct clk *pixel_clk_src; +struct clk *byte_intf_clk;u32 byte_clk_rate;u32 esc_clk_rate;
@@ -377,6 +378,14 @@ static int dsi_clk_init(struct msm_dsi_host *msm_host) goto exit; } + msm_host->byte_intf_clk =msm_clk_get (pdev,"byte_intf" ); +if (IS_ERR (msm_host->byte_intf_clk)) { + ret =PTR_ERR (msm_host->byte_intf_clk); +pr_debug ("%s: can't find byte_intf clock. ret=%d\n" , + __func__, ret); + msm_host->byte_intf_clk =NULL ; + } + msm_host->byte_clk_src =clk_get_parent (msm_host->byte_clk);if (!msm_host->byte_clk_src) { ret = -ENODEV ;
@@ -502,6 +511,16 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto error; } +if (msm_host->byte_intf_clk) { + ret =clk_set_rate (msm_host->byte_intf_clk, + msm_host->byte_clk_rate /2 ); +if (ret) { +pr_err ("%s: Failed to set rate byte intf clk, %d\n" , + __func__, ret); + goto error; + } + } + ret =clk_prepare_enable (msm_host->esc_clk);if (ret) {pr_err ("%s: Failed to enable dsi esc clk\n" , __func__);
@@ -520,8 +539,19 @@ static int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) goto pixel_clk_err; } +if (msm_host->byte_intf_clk) { + ret =clk_prepare_enable (msm_host->byte_intf_clk); +if (ret) { +pr_err ("%s: Failed to enable byte intf clk\n" , + __func__); + goto byte_intf_clk_err; + } + } +return 0 ; +byte_intf_clk_err: +clk_disable_unprepare (msm_host->pixel_clk); pixel_clk_err:clk_disable_unprepare (msm_host->byte_clk); byte_clk_err:
@@ -615,6 +645,8 @@ static void dsi_link_clk_disable(struct msm_dsi_host *msm_host)if (cfg_hnd->major ==MSM_DSI_VER_MAJOR_6G ) {clk_disable_unprepare (msm_host->esc_clk);clk_disable_unprepare (msm_host->pixel_clk); +if (msm_host->byte_intf_clk) +clk_disable_unprepare (msm_host->byte_intf_clk);clk_disable_unprepare (msm_host->byte_clk); }else {clk_disable_unprepare (msm_host->pixel_clk);
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PATCH 4/7 dt-bindings: display: msm/dsi: Remove unused properties
In reply to Archit Taneja"qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't acceptable and have never been used in any DT files. Remove them.
--- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ---- 1 file changed, 4 deletions(-)
Documentation/devicetree/bindings/display/msm/dsi.txt +0 -4
@@ -7,8 +7,6 @@ Required properties: - reg: Physical base address and length of the registers of controller - reg-names: The names of register regions. The following regions are required: * "dsi_ctrl" -- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should - be 0 or 1, since we have 2 DSI controllers at most for now. - interrupts: The interrupt signal from the DSI block. - power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: Phandles to device clocks.
@@ -96,8 +94,6 @@ Required properties: * "dsi_phy_regulator" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). -- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should - be 0 or 1, since we have 2 DSI PHYs at most for now. - power-domains: Should be <&mmcc MDSS_GDSC>. - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required:
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Re: [PATCH 4/7] dt-bindings: display: msm/dsi: Remove unused properties
Quoted 9 lines · Archit Taneja
"qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't acceptable and have never been used in any DT files. Remove them.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ---- 1 file changed, 4 deletions(-)
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PATCH 5/7 dt-bindings: display: msm/dsi: Fix the PHY regulator supply props
In reply to Archit TanejaThe PHY regulator supply names vary across different PHY versions. Mention explicitly which PHYs require which supplies.
--- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ++++ 1 file changed, 4 insertions(+)
Documentation/devicetree/bindings/display/msm/dsi.txt +4 -0
@@ -98,7 +98,11 @@ Required properties: - clocks: Phandles to device clocks. See [1] for details on clock bindings. - clock-names: the following clocks are required: * "iface" + For 28nm HPM/LP, 28nm 8960 PHYs: - vddio-supply: phandle to vdd-io regulator device node + For 20nm PHY: +- vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
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Rob Herring
Reviewed-byRe: [PATCH 5/7] dt-bindings: display: msm/dsi: Fix the PHY regulator supply props
Quoted 9 lines · Archit Taneja
The PHY regulator supply names vary across different PHY versions. Mention explicitly which PHYs require which supplies.
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 4 ++++ 1 file changed, 4 insertions(+)
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PATCH 6/7 dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
In reply to Archit TanejaAdd the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.
--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)
Documentation/devicetree/bindings/display/msm/dsi.txt +11 -2
@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>.
@@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node + For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties:
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Rob Herring
maintainerRe: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Quoted 39 lines · Archit Taneja
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). From 14nm PHY onwards, the "
dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/msm/dsi.txt +9
-2@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1). - power-domains: Should be <&mmcc MDSS_GDSC>.
Documentation/devicetree/bindings/display/msm/dsi.txt Required properties: · line 112
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0@@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device node
Did you mean to add this?
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0+ For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties:Signature · 2 lines
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Re: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Quoted 38 lines · Rob Herring
Quoted 37 lines · Archit Taneja
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/msm/dsi.txt +9
-2@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY and PHY - regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY. Some + revisions require the PHY regulator base address, whereas others require the + PHY lane base address. See below for each PHY revision. - reg-names: The names of register regions. The following regions are required: + For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi.txt Required properties: · line 112
Quoted 6 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0- power-domains: Should be <&mmcc MDSS_GDSC>.@@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device nodeDid you mean to add this?
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the 20nm PHY. I'll move this to a separate patch.
Thanks,
Archit
Quoted 9 lines
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0+ For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties:Signature · 2 lines
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Signature · 2 lines
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Re: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Quoted 61 lines · Archit Taneja
Quoted 48 lines · Rob Herring
Quoted 46 lines · Archit Taneja
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/msm/dsi.txt +0
-1@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY andPHY
Documentation/devicetree/bindings/display/msm/dsi.txt +2
-1- regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY.Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are
required:Documentation/devicetree/bindings/display/msm/dsi.txt +5
-0+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider,creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmccMDSS_GDSC>.Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi.txt Required properties: · line 112
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0@@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device nodeDid you mean to add this?
Quoted 3 lines
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the
20nm PHY. I'll move this to a separate patch.
actually, this looks correct, just formatted counter-intuitively by git-format-patch..
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi:
Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.
So I don't think it needs to be split up.
BR,
-R
Quoted 17 lines
Thanks,
ArchitQuoted 9 lines
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-1+ For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties: --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation--
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Re: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Quoted 69 lines · Rob Clark
Quoted 61 lines · Archit Taneja
Quoted 48 lines · Rob Herring
Quoted 46 lines · Archit Taneja
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/msm/dsi.txt +0
-1@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHY andPHY
Documentation/devicetree/bindings/display/msm/dsi.txt +2
-1- regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY.Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions are
required:Documentation/devicetree/bindings/display/msm/dsi.txt +5
-0+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clock provider,creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmccMDSS_GDSC>.Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi.txt Required properties: · line 112
Quoted 5 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0@@ -102,6 +109,8 @@ Required properties: - vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device nodeDid you mean to add this?
Quoted 3 lines
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the
20nm PHY. I'll move this to a separate patch.actually, this looks correct, just formatted counter-intuitively by git-format-patch..
Quoted 6 lines
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi:
Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.So I don't think it needs to be split up.
Oh yeah, you're right. I guess this is okay as is, then.
Thanks,
Archit
Quoted 26 lines
BR,
-RQuoted 14 lines
Thanks,
ArchitQuoted 9 lines
Quoted 9 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-1+ For 14nm PHY: - vcca-supply: phandle to vcca regulator device node Optional properties: --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux FoundationQuoted 3 lines
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Re: [PATCH 6/7] dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHY
Quoted 89 lines · Archit Taneja
Quoted 86 lines · Rob Clark
Quoted 70 lines · Archit Taneja
Quoted 55 lines · Rob Herring
Quoted 52 lines · Archit Taneja
Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096).
From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not
required,
but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs.Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)Documentation/devicetree/bindings/display/msm/dsi.txt +0
-1@@ -86,12 +86,19 @@ Required properties: * "qcom,dsi-phy-28nm-lp" * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" -- reg: Physical base address and length of the registers of PLL, PHYand
PHYDocumentation/devicetree/bindings/display/msm/dsi.txt +2
-1- regulator + * "qcom,dsi-phy-14nm" +- reg: Physical base address and length of the registers of PLL, PHY.Some
+ revisions require the PHY regulator base address, whereas others require the
+ PHY lane base address. See below for each PHY revision.
- reg-names: The names of register regions. The following regions
are
required:Documentation/devicetree/bindings/display/msm/dsi.txt +5
-0+ For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" + For DSI 14nm PHY: + * "dsi_pll" + * "dsi_phy" + * "dsi_phy_lane" - clock-cells: Must be 1. The DSI PHY block acts as a clockprovider,
creating
2 clocks: A byte clock (index 0), and a pixel clock (index 1).
- power-domains: Should be <&mmccMDSS_GDSC>.Documentation/devicetree/bindings/display/msm/dsi.txt +0
-0@@ -102,6 +109,8 @@ Required properties:Quoted 8 lines
Documentation/devicetree/bindings/display/msm/dsi.txt Required properties: · line 112
Quoted 4 lines
Documentation/devicetree/bindings/display/msm/dsi.txt +1
-0- vddio-supply: phandle to vdd-io regulator device node For 20nm PHY: - vddio-supply: phandle to vdd-io regulator device node +- vcca-supply: phandle to vcca regulator device nodeDid you mean to add this?
Quoted 3 lines
Yes, I didn't intend it to be a part of this patch, but this supply is indeed needed for the
20nm PHY. I'll move this to a separate patch.actually, this looks correct, just formatted counter-intuitively by git-format-patch..
vcca-supply for 20nm was introduced by "dt-bindings: display: msm/dsi:
Fix the PHY regulator supply props", but when 14nm phy is added in this patch, it shows the addition of same line beneath 14nm PHY as an addition above the line.
Quoted 4 lines
Quoted 1 line
So I don't think it needs to be split up.
Oh yeah, you're right. I guess this is okay as is, then.
Doh!
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PATCH 7/7 dt-bindings: display: msm/dsi: Add updates for SDM845
In reply to Archit TanejaSDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding.
A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs.
--- Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/display/msm/dsi.txt +6 -1
@@ -20,6 +20,8 @@ Required properties: * "core" For DSIv2, we need an additional clock: * "src" + For DSI6G v2.0 onwards, we need also need the clock: + * "byte_intf" - assigned-clocks: Parents of "byte" and "pixel" for the given platform. - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided by a DSI PHY block. See [1] for details on clock bindings.
@@ -87,6 +89,7 @@ Required properties: * "qcom,dsi-phy-20nm" * "qcom,dsi-phy-28nm-8960" * "qcom,dsi-phy-14nm" + * "qcom,dsi-phy-10nm" - reg: Physical base address and length of the registers of PLL, PHY. Some revisions require the PHY regulator base address, whereas others require the PHY lane base address. See below for each PHY revision.
@@ -95,7 +98,7 @@ Required properties: * "dsi_pll" * "dsi_phy" * "dsi_phy_regulator" - For DSI 14nm PHY: + For DSI 14nm and 10nm PHYs: * "dsi_pll" * "dsi_phy" * "dsi_phy_lane"
@@ -112,6 +115,8 @@ Required properties: - vcca-supply: phandle to vcca regulator device node For 14nm PHY: - vcca-supply: phandle to vcca regulator device node + For 10nm PHY: +- vdds-supply: phandle to vdds regulator device node Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
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Re: [PATCH 7/7] dt-bindings: display: msm/dsi: Add updates for SDM845
Quoted 7 lines · Archit Taneja
SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding.
A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs.
Quoted 6 lines
Cc Rob Herring <[email protected]>Signed-off-by Archit Taneja <[email protected]>--- Documentation/devicetree/bindings/display/msm/dsi.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)