Add DTS for SDM845 SoC and MTP
v4 cover Add DTS for SDM845 SoC and MTP
These are basic device tree files needed to boot a SDM845 MTP board to a ramfs based serial console shell
Bindings are based on whats proposed for pinctrl/serial/clock drivers for SDM845 SoC
pinctrl: https://patchwork.kernel.org/patch/10157143/ (This is now pulled in by Linus Walleij for 4.17)
clocks: https://lkml.org/lkml/2018/1/31/209 (under review)
serial: https://patchwork.ozlabs.org/cover/860251/ (under review)
'PATCH 3/3' is based on v2 of serial patches, will need an update if v3 (still in the works) has further binding updates
Since 'PATCH 2/3' also adds an ITS node and keeps it disabled, we also depend on https://lkml.org/lkml/2018/1/29/383
changes in v4:
* pull config changes to uart pins
* License in device tree files is still GPL-2.0
changes in v3:
* split the pinmux/pinconf nodes across SoC/Board files
* Fixes for issues reported with 'make dtbs W=2'
* other minor fixes based on review
changes in v2:
* dropped cpu-map
* dropped GIC_CPU_MASK_SIMPLE()
* Added new cpu compatible for kryo385
* added ITS node, marked as disabled
Rajendra Nayak (4):
dt-bindings: arm: Document kryo385 cpu
dt-bindings: qcom: Add SDM845 bindings
arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
arm64: dts: sdm845: Add serial console support
Documentation/devicetree/bindings/arm/cpus.txt | 1 + Documentation/devicetree/bindings/arm/qcom.txt | 1 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 54 +++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 316 +++++++++++++++++++++++++ 5 files changed, 373 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 1/4 dt-bindings: arm: Document kryo385 cpu
Document the compatible string for the Kryo385 cpus found in qualcomm SoCs.
--- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/cpus.txt +1 -0
@@ -184,6 +184,7 @@ described below. "nvidia,tegra186-denver" "qcom,krait" "qcom,kryo" + "qcom,kryo385" "qcom,scorpion" - enable-method Value type: <stringlist>
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 2/4 dt-bindings: qcom: Add SDM845 bindings
In reply to Rajendra NayakAdd a SoC string 'sdm845' for the qualcomm SDM845 SoC
--- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/arm/qcom.txt +1 -0
@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845 The 'board' element must be one of the following strings:
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 3/4 arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Rajendra NayakAdd a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
--- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
arch/arm64/boot/dts/qcom/Makefile +1 -0
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
arch/arm64/boot/dts/qcom/sdm845-mtp.dts new file +15 -0
@@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 MTP board device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +/dts-v1/; + +#include "sdm845.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDM845 MTP"; + compatible = "qcom,sdm845-mtp"; +};
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +277 -0
277 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v4 4/4 arm64: dts: sdm845: Add serial console support
In reply to Rajendra NayakAdd the qup uart node and geni se instance needed to support the serial console on the MTP.
--- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+)
arch/arm64/boot/dts/qcom/sdm845-mtp.dts +39 -0
@@ -12,4 +12,43 @@ / { model = "Qualcomm Technologies, Inc. SDM845 MTP"; compatible = "qcom,sdm845-mtp"; + + aliases { + serial0 = &qup_uart2; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&soc { + geni-se at ac0000 { + serial at a84000 { + status = "okay"; + }; + }; + + pinctrl at 3400000 { + qup-uart2-default { + pinconf_tx { + pins = "gpio4"; + drive-strength = <2>; + bias-disable; + }; + + pinconf_rx { + pins = "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup-uart2-sleep { + pinconf { + pins = "gpio4", "gpio5"; + bias-pull-down; + }; + }; + }; };
arch/arm64/boot/dts/qcom/sdm845.dtsi +39 -0
@@ -6,6 +6,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,gcc-sdm845.h> / { interrupt-parent = <&intc>;
@@ -195,6 +196,20 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qup_uart2_default: qup-uart2-default { + pinmux { + function = "qup9"; + pins = "gpio4", "gpio5"; + }; + }; + + qup_uart2_sleep: qup-uart2-sleep { + pinmux { + function = "gpio"; + pins = "gpio4", "gpio5"; + }; + }; }; timer at 17c90000 {
@@ -273,5 +288,29 @@ #interrupt-cells = <4>; cell-index = <0>; }; + + geni-se at ac0000 { + compatible = "qcom,geni-se-qup"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0xac0000 0x6000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + + qup_uart2: serial at a84000 { + compatible = "qcom,geni-debug-uart"; + reg = <0xa84000 0x4000>; + reg-names = "se-phys"; + clock-names = "se-clk"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qup_uart2_default>; + pinctrl-1 = <&qup_uart2_sleep>; + interrupts = <GIC_SPI 354 IRQ_TYPE_NONE>; + status = "disabled"; + }; + }; }; };
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 1/4] dt-bindings: arm: Document kryo385 cpu
In reply to Rajendra NayakHi,
Quoted 8 lines · Rajendra Nayak
Document the compatible string for the Kryo385 cpus found in qualcomm SoCs.
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Rob Herring <[email protected]>--- Documentation/devicetree/bindings/arm/cpus.txt | 1 + 1 file changed, 1 insertion(+)
FWIW since my review doesn't add much atop Rob's:
Re: [PATCH v4 2/4] dt-bindings: qcom: Add SDM845 bindings
In reply to Rajendra NayakHi,
Quoted 6 lines · Rajendra Nayak
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by Rajendra Nayak <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+)
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Rajendra NayakHi,
Quoted 27 lines · Rajendra Nayak
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Doug Anderson <[email protected]>--- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsiarch/arm64/boot/dts/qcom/Makefile +1
-0@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtbarch/arm64/boot/dts/qcom/sdm845-mtp.dts new file +0
-0
arch/arm64/boot/dts/qcom/sdm845-mtp.dts line 1
Quoted 1 line
arch/arm64/boot/dts/qcom/sdm845-mtp.dts new file +1
-0@@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0
This already has my Reviewed-by tag (and that's great), but just making it clear that I am in favor of this landing with just the GPL-2.0 license and not block waiting on the QC lawyers to hash out whether the device tree can really be dual-licensed.
If lawyers come back soon then it will be easy to have a followup patch that changes this. Since (I don't think) any hobbyists have an SDM845 in their hands right now it seems unlikely to be hard to track down any authors in the meantime and make sure they're OK.
If lawyers don't come back soon then it will be a good thing that we didn't block.
Having this skeleton DTS file land sooner rather than later will unblock other patches to be sent out enabling other peripherals, which seems like a nice thing. :)
-Doug
Re: [PATCH v4 4/4] arm64: dts: sdm845: Add serial console support
In reply to Rajendra NayakHi,
Quoted 8 lines · Rajendra Nayak
Add the qup uart node and geni se instance needed to support the serial console on the MTP.
Signed-off-by Rajendra Nayak <[email protected]>--- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 39 +++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+)
Looks nice to me. Thanks!
As in your cover letter, this patch will almost certainly need to be spun again because it's based on bindings that have review feedback. For those of you playing along at home, see
<https://patchwork.kernel.org/patch/10162063/>. Thus, I'm not providing a Reviewed-by tag at the moemnt.
I will still say thanks for posting this (even though it was based on old bindings) since it allowed us to make some good progress ahead of time so we'll be very close to landing when the serial patch is spun next.
In my ideal world the first 3 patches of this series would land sooner rather than later and then this 4th patch would simply be re-posted on its own when the bindings get more finalized (or, even better, if the first 3 patches have landed then Karthikeyan could just glom this on to the end of his next spin of the serial driver. ;-)
-Doug
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Rajendra NayakQuoted 12 lines · On Fri, 16 Feb 2018 11:35:02 +0530 Rajendra Nayak <[email protected]> wrote:
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Doug Anderson <[email protected]>--- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
[...]
Quoted 189 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +183
-0@@ -0,0 +1,277 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * SDM845 SoC device tree source + * + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + memory at 80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0x80000000 0 0>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu at 0 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu at 100 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_100>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu at 200 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_200>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu at 300 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_300>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu at 400 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_400>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu at 500 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_500>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu at 600 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_600>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu at 700 { + device_type = "cpu"; + compatible = "qcom,kryo385"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_700>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; + }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32764>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller at 17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic-its at 17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17a40000 0x20000>; + status = "disabled"; + }; + }; + + gcc: clock-controller at 100000 {
arch/arm64/boot/dts/qcom/sdm845.dtsi line 193
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +10
-0+ compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + tlmm: pinctrl at 3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;
Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC binding. Set it to the actual trigger value.
Quoted 64 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +64
-0+ gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + timer at 17c90000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17c90000 0x1000>; + + frame at 17ca0000 { + frame-number = <0>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17ca0000 0x1000>, + <0x17cb0000 0x1000>; + }; + + frame at 17cc0000 { + frame-number = <1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cc0000 0x1000>; + status = "disabled"; + }; + + frame at 17cd0000 { + frame-number = <2>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cd0000 0x1000>; + status = "disabled"; + }; + + frame at 17ce0000 { + frame-number = <3>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17ce0000 0x1000>; + status = "disabled"; + }; + + frame at 17cf0000 { + frame-number = <4>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17cf0000 0x1000>; + status = "disabled"; + }; + + frame at 17d00000 { + frame-number = <5>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d00000 0x1000>; + status = "disabled"; + }; + + frame at 17d10000 { + frame-number = <6>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x17d10000 0x1000>; + status = "disabled"; + }; + }; +
arch/arm64/boot/dts/qcom/sdm845.dtsi line 267
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +10
-0+ spmi_bus: spmi at c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0xc440000 0x1100>, + <0xc600000 0x2000000>, + <0xe600000 0x100000>, + <0xe700000 0xa0000>, + <0xc40a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = <GIC_SPI 481 IRQ_TYPE_NONE>;
Same here.
arch/arm64/boot/dts/qcom/sdm845.dtsi line 277
Quoted 10 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +10
-0+ qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + }; +};
Thanks,
M.
Signature · 1 line
Without deviation from the norm, progress is not possible.
Re: [PATCH v4 2/4] dt-bindings: qcom: Add SDM845 bindings
In reply to Rajendra NayakQuoted 12 lines · Rajendra Nayak
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by Rajendra Nayak <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/arm/qcom.txt +0
-0
Documentation/devicetree/bindings/arm/qcom.txt The 'SoC' element must be one of the following strings: · line 29
Quoted 4 lines
Documentation/devicetree/bindings/arm/qcom.txt +1
-0@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845
These should really be the full string with 'qcom,', but you don't have to fix that now.
Re: [PATCH v4 2/4] dt-bindings: qcom: Add SDM845 bindings
Rob,
Quoted 21 lines · Rob Herring
Quoted 12 lines · Rajendra Nayak
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by Rajendra Nayak <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/arm/qcom.txt +0
-0Documentation/devicetree/bindings/arm/qcom.txt The 'SoC' element must be one of the following strings: · line 29
Quoted 4 lines
Documentation/devicetree/bindings/arm/qcom.txt +1
-0@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845These should really be the full string with 'qcom,', but you don't have to fix that now.
Quoted 1 line
Reviewed-by Rob Herring <[email protected]>
Thanks for the review! I agree that we should land this and then make further progress in additional patches.
Are you suggesting to rewriting this whole bindings doc to not specify things in an "M x N" type of way? AKA the top of this doc says:
Quoted 4 lines
Each board must specify a top-level board compatible string with the following format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"The 'SoC' and 'board' elements are required. All other elements are optional.
...and then the doc goes on to give lists of known SoC and board values.
Presumably if someone were to fix this then they'd need to try to track down existing boards so they could enumerate every known combination?
-Doug
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Marc ZyngierHi,
Quoted 9 lines · Marc Zyngier
Quoted 1 line
+ interrupts = <
GIC_SPI208IRQ_TYPE_NONE>;Please do not use
IRQ_TYPE_NONE, ever. It doesn't exist in the GIC binding. Set it to the actual trigger value.Quoted 1 line
+ interrupts = <
GIC_SPI481IRQ_TYPE_NONE>;Same here.
Thanks for the review Marc!
Andy: If I'm reading everything correctly you're the one who would collect these patches and apply them. Is that right? Do they look OK to you in general? Would you prefer that Rajendra send out a v5 with the fixes pointed out by Marc, or would you prefer to fix them up yourself when applying? Is now a good time or would you prefer to wait?
Thanks! :)
-Doug
Rob Herring
maintainerRe: [PATCH v4 2/4] dt-bindings: qcom: Add SDM845 bindings
In reply to Doug AndersonQuoted 38 lines · Doug Anderson
Rob,
Quoted 21 lines · Rob Herring
Quoted 12 lines · Rajendra Nayak
Add a SoC string 'sdm845' for the qualcomm SDM845 SoC
Signed-off-by Rajendra Nayak <[email protected]>--- Documentation/devicetree/bindings/arm/qcom.txt | 1 + 1 file changed, 1 insertion(+)Documentation/devicetree/bindings/arm/qcom.txt +0
-0Documentation/devicetree/bindings/arm/qcom.txt The 'SoC' element must be one of the following strings: · line 29
Quoted 4 lines
Documentation/devicetree/bindings/arm/qcom.txt +1
-0@@ -26,6 +26,7 @@ The 'SoC' element must be one of the following strings: msm8996 mdm9615 ipq8074 + sdm845These should really be the full string with 'qcom,', but you don't have to fix that now.
Quoted 1 line
Reviewed-by Rob Herring <[email protected]>Thanks for the review! I agree that we should land this and then make further progress in additional patches.
Are you suggesting to rewriting this whole bindings doc to not specify things in an "M x N" type of way? AKA the top of this doc says:
Quoted 4 lines
Each board must specify a top-level board compatible string with the following format:
compatible = "qcom,<SoC>[-<soc_version>][-<foundry_id>]-<board>[/<subtype>][-<board_version>]"The 'SoC' and 'board' elements are required. All other elements are optional.
Quoted 6 lines
...and then the doc goes on to give lists of known SoC and board values.
Presumably if someone were to fix this then they'd need to try to track down existing boards so they could enumerate every known combination?
Ah, I forgot about all this QCom craziness. NM.
Though I'm not sure any of these optional suffixes ever got implemented. AFAIK, downstream still uses those separate board-id properties (though the bootloaders can finally deal with them being absent).
Rob
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Marc ZyngierQuoted 14 lines · Marc Zyngier
Quoted 11 lines · On Fri, 16 Feb 2018 11:35:02 +0530 Rajendra Nayak <[email protected]> wrote:
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by Rajendra Nayak <[email protected]>Reviewed-by Doug Anderson <[email protected]>--- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ arch/arm64/boot/dts/qcom/sdm845.dtsi | 277 ++++++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
[...]
Quoted 35 lines
Quoted 35 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +35
-0+ + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller at 17a00000 { + compatible = "arm,gic-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17a00000 0x10000>, /* GICD */ + <0x17a60000 0x100000>; /* GICR * 8 */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + + gic-its at 17a40000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x17a40000 0x20000>; + status = "disabled"; + }; + }; + + gcc: clock-controller at 100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + };
Quoted 8 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi line 193
Quoted 5 lines
arch/arm64/boot/dts/qcom/sdm845.dtsi new file +5
-0+ + tlmm: pinctrl at 3400000 { + compatible = "qcom,sdm845-pinctrl"; + reg = <0x03400000 0xc00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_NONE>;Please do not use
IRQ_TYPE_NONE, ever. It doesn't exist in the GIC binding. Set it to the actual trigger value.
Thanks Marc for the review. I fixed these up and did a respin.
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Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
In reply to Doug AndersonQuoted 16 lines · Doug Anderson
Hi,
Quoted 9 lines · Marc Zyngier
Quoted 1 line
+ interrupts = <
GIC_SPI208IRQ_TYPE_NONE>;Please do not use
IRQ_TYPE_NONE, ever. It doesn't exist in the GIC binding. Set it to the actual trigger value.Quoted 1 line
+ interrupts = <
GIC_SPI481IRQ_TYPE_NONE>;Same here.
Thanks for the review Marc!
Quoted 6 lines
Andy: If I'm reading everything correctly you're the one who would collect these patches and apply them. Is that right? Do they look OK to you in general? Would you prefer that Rajendra send out a v5 with the fixes pointed out by Marc, or would you prefer to fix them up yourself when applying? Is now a good time or would you prefer to wait?
I just fixed up to remove all instances of IRQ_TYPE_NONE and sent a v5 out.
Quoted 10 lines
Thanks! :)
-Doug
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