ppc4xx: Add device models found in PPC440 core SoCs

PATCH New BALATON Zoltan 1 participant 1 message Mar 2, 2018

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BALATON Zoltan

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2018-03-02 17:53 UTC #0 lore raw

PATCH v3 1/1 ppc4xx: Add device models found in PPC440 core SoCs

These devices are found in newer SoCs based on 440 core e.g. the 460EX
(http://www.embeddeddeveloper.com/assets/processors/amcc/datasheets/
PP460EX_DS2063.pdf)

Signed-off-by BALATON Zoltan <[email protected]>

Signed-off-by David Gibson <[email protected]>

---
v3: Fixed warning from older gcc about variable used uninitialised

 hw/ppc/ppc440.h            |   26 +
 hw/ppc/ppc440_uc.c         | 1162 ++++++++++++++++++++++++++++++++++++++++++++
 include/hw/pci/pcie_host.h |    2 +-
 3 files changed, 1189 insertions(+), 1 deletion(-)
 create mode 100644 hw/ppc/ppc440.h
 create mode 100644 hw/ppc/ppc440_uc.c

hw/ppc/ppc440.h new file +26 -0

new file mode 100644
index 0000000..ad27db1
@@ -0,0 +1,26 @@
+/*
+ * QEMU PowerPC 440 shared definitions
+ *
+ * Copyright (c) 2012 François Revol
+ * Copyright (c) 2016-2018 BALATON Zoltan
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#ifndef PPC440_H
+#define PPC440_H
+
+#include "hw/ppc/ppc.h"
+
+void ppc4xx_l2sram_init(CPUPPCState *env);
+void ppc4xx_cpr_init(CPUPPCState *env);
+void ppc4xx_sdr_init(CPUPPCState *env);
+void ppc440_sdram_init(CPUPPCState *env, int nbanks,
+                       MemoryRegion *ram_memories,
+                       hwaddr *ram_bases, hwaddr *ram_sizes,
+                       int do_init);
+void ppc4xx_ahb_init(CPUPPCState *env);
+void ppc460ex_pcie_init(CPUPPCState *env);
+
+#endif /* PPC440_H */

hw/ppc/ppc440_uc.c new file +1162 -0

1,162 lines not on this page · raw message

include/hw/pci/pcie_host.h +1 -1

index 4d23c80..3f7b988 100644
@@ -65,7 +65,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
  * bit 12 - 14: function number
  * bit  0 - 11: offset in configuration space of a given device
  */
-#define PCIE_MMCFG_SIZE_MAX             (1ULL << 28)
+#define PCIE_MMCFG_SIZE_MAX             (1ULL << 29)
 #define PCIE_MMCFG_SIZE_MIN             (1ULL << 20)
 #define PCIE_MMCFG_BUS_BIT              20
 #define PCIE_MMCFG_BUS_MASK             0x1ff

Signature · 1 line

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