ARM: i.MX6: Add proper CONFIG names

ARCH_MX6 -> ARCH_IMX6
MX6 -> SOC_IMX6
MX6D -> SOC_IMX6D
MX6DL -> SOC_IMX6DL
MX6Q -> SOC_IMX6Q
MX6S -> SOC_IMX6S

MX6SL -> SOC_IMX6SL
MX6Sx -> SOC_IMX6SX
MX6SLL -> SOC_IMX6SLL
MX6UL -> SOC_IMX6UL
MX6UL_LITESOM -> SOC_IMX6UL_LITESOM
MX6UL_OPOS6UL -> SOC_IMX6UL_OPOS6UL

MX6ULL -> SOC_IMX6ULL
"MX6" -> "i.MX6"

Signed-off-by Jagan Teki <[email protected]>

---
 Makefile                                          |   2 +-
 arch/arm/Kconfig                                  |   6 +-
 arch/arm/dts/Makefile                             |   2 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h          |  46 +++++-----
 arch/arm/include/asm/arch-mx6/imx-rdc.h           |   4 +-
 arch/arm/include/asm/arch-mx6/imx-regs.h          |  69 ++++++++-------
 arch/arm/include/asm/arch-mx6/mx6-ddr.h           |  20 ++---
 arch/arm/include/asm/arch-mx6/mx6-pins.h          |  18 ++--
 arch/arm/include/asm/arch-mx6/mx6_plugin.S        |   6 +-
 arch/arm/include/asm/arch-mx6/mx6dl-ddr.h         |   4 +-
 arch/arm/include/asm/arch-mx6/mx6q-ddr.h          |   2 +-
 arch/arm/include/asm/arch-mx6/mx6sl-ddr.h         |   2 +-
 arch/arm/include/asm/arch-mx6/mx6sx-ddr.h         |   2 +-
 arch/arm/include/asm/arch-mx6/mx6ul-ddr.h         |   2 +-
 arch/arm/include/asm/mach-imx/dma.h               |   2 +-
 arch/arm/include/asm/mach-imx/iomux-v3.h          |  11 +--
 arch/arm/include/asm/mach-imx/mxc_i2c.h           |   2 +-
 arch/arm/include/asm/mach-imx/regs-apbh.h         |   6 +-
 arch/arm/include/asm/mach-imx/regs-bch.h          |   4 +-
 arch/arm/include/asm/mach-imx/regs-lcdif.h        |  21 +++--
 arch/arm/include/asm/mach-imx/sys_proto.h         |   6 +-
 arch/arm/mach-imx/Kconfig                         |  12 +--
 arch/arm/mach-imx/Makefile                        |   2 +-
 arch/arm/mach-imx/cache.c                         |   2 +-
 arch/arm/mach-imx/cpu.c                           |   6 +-
 arch/arm/mach-imx/init.c                          |   2 +-
 arch/arm/mach-imx/iomux-v3.c                      |   6 +-
 arch/arm/mach-imx/mx6/Kconfig                     | 100 +++++++++++-----------
 arch/arm/mach-imx/mx6/Makefile                    |   4 +-
 arch/arm/mach-imx/mx6/clock.c                     |  14 +--
 arch/arm/mach-imx/mx6/ddr.c                       |  20 +++--
 arch/arm/mach-imx/mx6/soc.c                       |   6 +-
 arch/arm/mach-imx/spl.c                           |   8 +-
 arch/arm/mach-imx/timer.c                         |   2 +-
 board/bachmann/ot1200/ot1200_spl.c                |   4 +-
 board/barco/platinum/spl_picon.c                  |   4 +-
 board/barco/platinum/spl_titanium.c               |   4 +-
 board/boundary/nitrogen6x/ddr-setup.cfg           |   8 +-
 board/compulab/cm_fx6/cm_fx6.c                    |   6 +-
 board/congatec/cgtqmx6eval/cgtqmx6eval.c          |   4 +-
 board/dhelectronics/dh_imx6/dh_imx6.c             |   4 +-
 board/engicam/common/spl.c                        |  24 +++---
 board/freescale/mx6memcal/spl.c                   |   6 +-
 board/freescale/mx6qarm2/mx6qarm2.c               |   8 +-
 board/freescale/mx6sabreauto/mx6sabreauto.c       |   8 +-
 board/freescale/mx6sabresd/mx6sabresd.c           |   8 +-
 board/freescale/mx6sllevk/mx6sllevk.c             |   2 +-
 board/freescale/mx6sxsabreauto/mx6sxsabreauto.c   |   2 +-
 board/freescale/mx6sxsabresd/mx6sxsabresd.c       |   2 +-
 board/freescale/mx6ul_14x14_evk/README            |   6 +-
 board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c |   4 +-
 board/freescale/mx6ullevk/README                  |   6 +-
 board/freescale/mx6ullevk/mx6ullevk.c             |   2 +-
 board/gateworks/gw_ventana/gw_ventana_spl.c       |   4 +-
 board/kosagi/novena/novena_spl.c                  |   4 +-
 board/liebherr/mccmon6/spl.c                      |   4 +-
 board/logicpd/imx6/imx6logic.c                    |   2 +-
 board/seco/Kconfig                                |   6 +-
 board/solidrun/mx6cuboxi/mx6cuboxi.c              |  10 +--
 board/tbs/tbs2910/Kconfig                         |   2 +-
 board/toradex/apalis_imx6/ddr-setup.cfg           |   8 +-
 board/toradex/colibri_imx6/ddr-setup.cfg          |   8 +-
 board/tqc/tqma6/Kconfig                           |   6 +-
 board/udoo/README                                 |   4 +-
 board/udoo/udoo.c                                 |   4 +-
 board/udoo/udoo_spl.c                             |   4 +-
 board/wandboard/spl.c                             |   8 +-
 board/wandboard/wandboard.c                       |   6 +-
 cmd/fastboot/Kconfig                              |   3 +-
 common/spl/Kconfig                                |   6 +-
 common/spl/spl.c                                  |   2 +-
 configs/apalis_imx6_defconfig                     |   4 +-
 configs/apalis_imx6_nospl_com_defconfig           |   4 +-
 configs/apalis_imx6_nospl_it_defconfig            |   4 +-
 configs/aristainetos2_defconfig                   |   4 +-
 configs/aristainetos2b_defconfig                  |   4 +-
 configs/aristainetos_defconfig                    |   4 +-
 configs/cgtqmx6eval_defconfig                     |   2 +-
 configs/cm_fx6_defconfig                          |   2 +-
 configs/colibri_imx6_defconfig                    |   4 +-
 configs/colibri_imx6_nospl_defconfig              |   4 +-
 configs/dh_imx6_defconfig                         |   2 +-
 configs/display5_defconfig                        |   4 +-
 configs/display5_factory_defconfig                |   4 +-
 configs/dms-ba16-1g_defconfig                     |   2 +-
 configs/dms-ba16_defconfig                        |   2 +-
 configs/ge_b450v3_defconfig                       |   2 +-
 configs/ge_b650v3_defconfig                       |   2 +-
 configs/ge_b850v3_defconfig                       |   2 +-
 configs/gwventana_emmc_defconfig                  |   2 +-
 configs/gwventana_gw5904_defconfig                |   2 +-
 configs/gwventana_nand_defconfig                  |   2 +-
 configs/imx6dl_icore_nand_defconfig               |   2 +-
 configs/imx6q_icore_nand_defconfig                |   2 +-
 configs/imx6q_logic_defconfig                     |   4 +-
 configs/imx6qdl_icore_mipi_defconfig              |   2 +-
 configs/imx6qdl_icore_mmc_defconfig               |   2 +-
 configs/imx6qdl_icore_nand_defconfig              |   2 +-
 configs/imx6qdl_icore_rqs_defconfig               |   2 +-
 configs/imx6ul_geam_mmc_defconfig                 |   2 +-
 configs/imx6ul_geam_nand_defconfig                |   2 +-
 configs/imx6ul_isiot_emmc_defconfig               |   2 +-
 configs/imx6ul_isiot_nand_defconfig               |   2 +-
 configs/liteboard_defconfig                       |   2 +-
 configs/marsboard_defconfig                       |   4 +-
 configs/mccmon6_nor_defconfig                     |   2 +-
 configs/mccmon6_sd_defconfig                      |   2 +-
 configs/mx6cuboxi_defconfig                       |   2 +-
 configs/mx6dlarm2_defconfig                       |   4 +-
 configs/mx6dlarm2_lpddr2_defconfig                |   4 +-
 configs/mx6memcal_defconfig                       |   4 +-
 configs/mx6qarm2_defconfig                        |   4 +-
 configs/mx6qarm2_lpddr2_defconfig                 |   4 +-
 configs/mx6qsabrelite_defconfig                   |   4 +-
 configs/mx6sabreauto_defconfig                    |   2 +-
 configs/mx6sabresd_defconfig                      |   2 +-
 configs/mx6slevk_defconfig                        |   2 +-
 configs/mx6slevk_spinor_defconfig                 |   2 +-
 configs/mx6slevk_spl_defconfig                    |   2 +-
 configs/mx6sllevk_defconfig                       |   2 +-
 configs/mx6sllevk_plugin_defconfig                |   2 +-
 configs/mx6sxsabreauto_defconfig                  |   2 +-
 configs/mx6sxsabresd_defconfig                    |   2 +-
 configs/mx6sxsabresd_spl_defconfig                |   2 +-
 configs/mx6ul_14x14_evk_defconfig                 |   2 +-
 configs/mx6ul_9x9_evk_defconfig                   |   2 +-
 configs/mx6ull_14x14_evk_defconfig                |   2 +-
 configs/mx6ull_14x14_evk_plugin_defconfig         |   2 +-
 configs/nitrogen6dl2g_defconfig                   |   4 +-
 configs/nitrogen6dl_defconfig                     |   4 +-
 configs/nitrogen6q2g_defconfig                    |   4 +-
 configs/nitrogen6q_defconfig                      |   4 +-
 configs/nitrogen6s1g_defconfig                    |   4 +-
 configs/nitrogen6s_defconfig                      |   4 +-
 configs/novena_defconfig                          |   4 +-
 configs/opos6uldev_defconfig                      |   2 +-
 configs/ot1200_defconfig                          |   4 +-
 configs/ot1200_spl_defconfig                      |   4 +-
 configs/pcm058_defconfig                          |   4 +-
 configs/pfla02_defconfig                          |   2 +-
 configs/pico-imx6ul_defconfig                     |   2 +-
 configs/platinum_picon_defconfig                  |   4 +-
 configs/platinum_titanium_defconfig               |   4 +-
 configs/riotboard_defconfig                       |   4 +-
 configs/secomx6quq7_defconfig                     |   4 +-
 configs/sksimx6_defconfig                         |   4 +-
 configs/tbs2910_defconfig                         |   2 +-
 configs/titanium_defconfig                        |   2 +-
 configs/tqma6dl_mba6_mmc_defconfig                |   2 +-
 configs/tqma6dl_mba6_spi_defconfig                |   2 +-
 configs/tqma6q_mba6_mmc_defconfig                 |   2 +-
 configs/tqma6q_mba6_spi_defconfig                 |   2 +-
 configs/tqma6s_mba6_mmc_defconfig                 |   2 +-
 configs/tqma6s_mba6_spi_defconfig                 |   2 +-
 configs/tqma6s_wru4_mmc_defconfig                 |   2 +-
 configs/udoo_defconfig                            |   2 +-
 configs/udoo_neo_defconfig                        |   2 +-
 configs/vining_2000_defconfig                     |   2 +-
 configs/wandboard_defconfig                       |   2 +-
 configs/warp_defconfig                            |   2 +-
 configs/xpress_defconfig                          |   2 +-
 configs/xpress_spl_defconfig                      |   2 +-
 configs/zc5202_defconfig                          |   4 +-
 configs/zc5601_defconfig                          |   4 +-
 doc/README.imx6                                   |   2 +-
 doc/README.imximage                               |   4 +-
 drivers/ata/dwc_ahsata.c                          |   2 +-
 drivers/crypto/fsl/jobdesc.c                      |   2 +-
 drivers/dma/Kconfig                               |   2 +-
 drivers/dma/apbh_dma.c                            |   2 +-
 drivers/gpio/mxc_gpio.c                           |  23 ++---
 drivers/i2c/Kconfig                               |   2 +-
 drivers/misc/mxc_ocotp.c                          |   8 +-
 drivers/mmc/Kconfig                               |   6 +-
 drivers/mtd/nand/Kconfig                          |   6 +-
 drivers/mtd/nand/mxs_nand.c                       |   2 +-
 drivers/net/Kconfig                               |   2 +-
 drivers/net/fec_mxc.c                             |   2 +-
 drivers/net/fec_mxc.h                             |   4 +-
 drivers/pci/pcie_imx.c                            |  14 +--
 drivers/pinctrl/nxp/Kconfig                       |   2 +-
 drivers/pwm/pwm-imx-util.c                        |   4 +-
 drivers/serial/Kconfig                            |   2 +-
 drivers/spi/fsl_qspi.c                            |  18 ++--
 drivers/thermal/Kconfig                           |   2 +-
 drivers/thermal/imx_thermal.c                     |   2 +-
 drivers/usb/host/Kconfig                          |   4 +-
 drivers/usb/host/ehci-mx6.c                       |   8 +-
 drivers/video/Kconfig                             |   2 +-
 drivers/video/ipu_regs.h                          |   2 +-
 env/Kconfig                                       |   2 +-
 include/configs/cgtqmx6eval.h                     |   4 +-
 include/configs/cm_fx6.h                          |   2 +-
 include/configs/ge_bx50v3.h                       |   2 +-
 include/configs/imx6-engicam.h                    |   4 +-
 include/configs/imx6_spl.h                        |   4 +-
 include/configs/mx6_common.h                      |  12 +--
 include/configs/mx6cuboxi.h                       |  12 +--
 include/configs/mx6memcal.h                       |   2 +-
 include/configs/mx6sabre_common.h                 |  12 +--
 include/configs/titanium.h                        |   2 +-
 include/configs/udoo.h                            |   4 +-
 include/configs/wandboard.h                       |  14 +--
 include/fsl_sec.h                                 |   8 +-
 lib/rsa/Kconfig                                   |   4 +-
 205 files changed, 552 insertions(+), 545 deletions(-)

Makefile +1 -1

index 5fa14789d9..a969fef1dd 100644
@@ -778,7 +778,7 @@ ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
 endif
 endif
 ALL-$(CONFIG_SPL) += spl/u-boot-spl.bin
-ifeq ($(CONFIG_MX6)$(CONFIG_SECURE_BOOT), yy)
+ifeq ($(CONFIG_SOC_IMX6)$(CONFIG_SECURE_BOOT), yy)
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot-ivt.img
 else
 ALL-$(CONFIG_SPL_FRAMEWORK) += u-boot.img

arch/arm/Kconfig +3 -3

index b8f7a982d9..ad7f0c1f7d 100644
@@ -641,8 +641,8 @@ config ARCH_MX7
 	select ARCH_MISC_INIT
 	imply MXC_GPIO
 
-config ARCH_MX6
-	bool "Freescale MX6"
+config ARCH_IMX6
+	bool "Freescale i.MX6"
 	select CPU_V7
 	select SYS_FSL_HAS_SEC if SECURE_BOOT
 	select SYS_FSL_SEC_COMPAT_4

@@ -650,7 +650,7 @@ config ARCH_MX6
 	select SYS_THUMB_BUILD if SPL
 	imply MXC_GPIO
 
-if ARCH_MX6
+if ARCH_IMX6
 config SPL_LDSCRIPT
         default "arch/arm/mach-omap2/u-boot-spl.lds"
 endif

arch/arm/dts/Makefile +1 -1

index 7dd1dffae5..7a5f0a36a3 100644
@@ -385,7 +385,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
 
 dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
 
-dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
+dtb-$(CONFIG_SOC_IMX6) += imx6ull-14x14-evk.dtb \
 	imx6sl-evk.dtb \
 	imx6sll-evk.dtb \
 	imx6dl-icore.dtb \

arch/arm/include/asm/arch-mx6/crm_regs.h +23 -23

index 74ed91230f..e5f699f691 100644
@@ -205,7 +205,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK			0x7
 #define MXC_CCM_CCR_WB_COUNT_OFFSET			(1 << 16)
 #define MXC_CCM_CCR_COSC_EN				(1 << 12)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCR_OSCNT_MASK				0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK				0xFF

@@ -275,7 +275,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK		(0x3 << 18)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET		18
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK		(0x3 << 16)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET		16
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK		(0x3 << 14)

@@ -283,7 +283,7 @@ struct mxc_ccm_reg {
 #endif
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK		(0x3 << 12)
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET		12
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL			(1 << 11)
 #endif
 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL			(1 << 10)

@@ -336,7 +336,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK			0x3F
 
 /* Define the bits in register CSCMR2 */
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK			(0x7 << 21)
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET		21
 #endif

@@ -352,7 +352,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET		2
 
 /* Define the bits in register CSCDR1 */
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK		(0x7 << 25)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET		25
 #endif

@@ -370,7 +370,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET		16
 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK			(0x7 << 11)
 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET		11
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET		8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK		(0x7 << 8)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET		6

@@ -382,7 +382,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_UART_CLK_SEL			(1 << 6)
 
 /* Define the bits in register CS1CDR */
-/* MX6UL, !MX6ULL */
+/* i.MX6UL, !i.MX6ULL */
 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_MASK		(0x7 << 22)
 #define MXC_CCM_CS1CDR_SAI3_CLK_PRED_OFFSET		22
 #define MXC_CCM_CS1CDR_SAI3_CLK_PODF_MASK		(0x3F << 16)

@@ -454,7 +454,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET		0
 
 /* Define the bits in register CDCDR */
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK			(0x7 << 29)
 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET		29
 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL			(1 << 28)

@@ -572,7 +572,7 @@ struct mxc_ccm_reg {
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY		(1 << 4)
 #endif
 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY		(1 << 3)

@@ -583,14 +583,14 @@ struct mxc_ccm_reg {
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE			(1 << 27)
 #define MXC_CCM_CLPCR_MASK_SCU_IDLE			(1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CLPCR_MASK_CORE3_WFI			(1 << 25)
 #define MXC_CCM_CLPCR_MASK_CORE2_WFI			(1 << 24)
 #define MXC_CCM_CLPCR_MASK_CORE1_WFI			(1 << 23)
 #endif
 #define MXC_CCM_CLPCR_MASK_CORE0_WFI			(1 << 22)
 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS		(1 << 21)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS		(1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM			(1 << 17)
 #endif

@@ -602,7 +602,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CLPCR_DIS_REF_OSC			(1 << 7)
 #define MXC_CCM_CLPCR_SBYOS				(1 << 6)
 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM		(1 << 5)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK			(0x3 << 3)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET		3
 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY		(1 << 2)

@@ -612,7 +612,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CISR */
 #define MXC_CCM_CISR_ARM_PODF_LOADED			(1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED		(1 << 23)
 #endif
 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED		(1 << 22)

@@ -625,7 +625,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CIMR */
 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED		(1 << 26)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED		(1 << 23)
 #endif
 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED		(1 << 22)

@@ -692,7 +692,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR0_DCIC1_MASK			(3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET			26
 #define MXC_CCM_CCGR0_DCIC2_MASK			(3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET			30
 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK			(3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 #else

@@ -719,7 +719,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_EPIT2S_MASK			(3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET			16
 #define MXC_CCM_CCGR1_ESAIS_MASK			(3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR1_WAKEUP_OFFSET			18
 #define MXC_CCM_CCGR1_WAKEUP_MASK			(3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 #endif

@@ -727,13 +727,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_GPT_BUS_MASK			(3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET			22
 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK			(3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR1_GPU2D_OFFSET			24
 #define MXC_CCM_CCGR1_GPU2D_MASK			(3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_GPU3D_OFFSET			26
 #define MXC_CCM_CCGR1_GPU3D_MASK			(3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET			28
 #define MXC_CCM_CCGR1_OCRAM_S_MASK			(3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 #define MXC_CCM_CCGR1_CANFD_OFFSET			30

@@ -746,7 +746,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_CSI_OFFSET			2
 #define MXC_CCM_CCGR2_CSI_MASK				(3 << MXC_CCM_CCGR2_CSI_OFFSET)
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET		4
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK		(3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #endif

@@ -839,7 +839,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MLB_MASK					(3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET	20
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET	22
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK		(3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #endif

@@ -864,7 +864,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET				30
 #define MXC_CCM_CCGR3_GPIO4_CLK_MASK				(3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET)
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET			30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK				(3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif

@@ -903,7 +903,7 @@ struct mxc_ccm_reg {
 
 #define MXC_CCM_CCGR5_ROM_OFFSET			0
 #define MXC_CCM_CCGR5_ROM_MASK				(3 << MXC_CCM_CCGR5_ROM_OFFSET)
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR5_SATA_OFFSET			4
 #define MXC_CCM_CCGR5_SATA_MASK				(3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #endif

@@ -923,7 +923,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_UART_MASK				(3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET		26
 #define MXC_CCM_CCGR5_UART_SERIAL_MASK			(3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define MXC_CCM_CCGR5_SAI1_OFFSET			20
 #define MXC_CCM_CCGR5_SAI1_MASK				(3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 #define MXC_CCM_CCGR5_SAI2_OFFSET			30

arch/arm/include/asm/arch-mx6/imx-rdc.h +2 -2

index c4d3bb44b4..d69a92b562 100644
@@ -7,10 +7,10 @@
 #ifndef __IMX_RDC_H__
 #define __IMX_RDC_H__
 
-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_SOC_IMX6SX)
 #include "mx6sx_rdc.h"
 #else
 #error "Please select cpu"
-#endif /* CONFIG_MX6SX */
+#endif /* CONFIG_SOC_IMX6SX */
 
 #endif	/* __IMX_RDC_H__*/

arch/arm/include/asm/arch-mx6/imx-regs.h +36 -33

index 8513406a8e..1605032a6e 100644
@@ -12,12 +12,13 @@
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_IMX6SL
 #define GPU_2D_ARB_BASE_ADDR            0x02200000
 #define GPU_2D_ARB_END_ADDR             0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000
 #define OPENVG_ARB_END_ADDR             0x02207FFF
-#elif (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#elif (defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+		defined(CONFIG_SOC_IMX6ULL))
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00107FFF
 #define GPU_ARB_BASE_ADDR               0x01800000

@@ -26,7 +27,7 @@
 #define APBH_DMA_ARB_END_ADDR           0x0180BFFF
 #define M4_BOOTROM_BASE_ADDR			0x007F8000
 
-#elif !defined(CONFIG_MX6SLL)
+#elif !defined(CONFIG_SOC_IMX6SLL)
 #define CAAM_ARB_BASE_ADDR              0x00100000
 #define CAAM_ARB_END_ADDR               0x00103FFF
 #define APBH_DMA_ARB_BASE_ADDR          0x00110000

@@ -39,16 +40,16 @@
 #define GPU_2D_ARB_END_ADDR             0x00137FFF
 #define DTCP_ARB_BASE_ADDR              0x00138000
 #define DTCP_ARB_END_ADDR               0x0013BFFF
-#endif	/* CONFIG_MX6SL */
+#endif	/* CONFIG_SOC_IMX6SL */
 
 #define MXS_APBH_BASE			APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE			(APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
-#if (defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL))
+#if (defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL) || defined(CONFIG_SOC_IMX6SL) || \
+	defined(CONFIG_SOC_IMX6SLL))
 #define GPV2_BASE_ADDR                  0x00D00000
 #define GPV3_BASE_ADDR			0x00E00000
 #define GPV4_BASE_ADDR			0x00F00000

@@ -82,19 +83,19 @@
 /* AIPS3 only on i.MX6SX */
 #define AIPS3_ARB_BASE_ADDR             0x02200000
 #define AIPS3_ARB_END_ADDR              0x022FFFFF
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                0x60000000
 #define QSPI0_AMBA_END                 0x6FFFFFFF
 #define QSPI1_AMBA_BASE                0x70000000
 #define QSPI1_AMBA_END                 0x7FFFFFFF
-#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#elif (defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
 #define QSPI0_AMBA_BASE                 0x60000000
 #define QSPI0_AMBA_END                  0x6FFFFFFF
-#elif !defined(CONFIG_MX6SLL)
+#elif !defined(CONFIG_SOC_IMX6SLL)
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
 #define OPENVG_ARB_BASE_ADDR            0x02204000

@@ -109,9 +110,9 @@
 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
 #endif
 
-#if (defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if (defined(CONFIG_SOC_IMX6SLL) || defined(CONFIG_SOC_IMX6SL) || \
+	defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL))
 #define MMDC0_ARB_BASE_ADDR             0x80000000
 #define MMDC0_ARB_END_ADDR              0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR             0xC0000000

@@ -123,7 +124,7 @@
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 #endif
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define IPU_SOC_BASE_ADDR		IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET			0x00200000
 #endif

@@ -152,7 +153,7 @@
 #define MX6SLL_UART3_BASE_ADDR      (ATZ1_BASE_ADDR + 0x34000)
 #define MX6SL_UART4_BASE_ADDR       (ATZ1_BASE_ADDR + 0x38000)
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
 #endif
 #define UART1_IPS_BASE_ADDR         (ATZ1_BASE_ADDR + 0x20000)

@@ -164,7 +165,7 @@
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 #endif

@@ -202,17 +203,17 @@
 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
 #define IOMUXC_GPR_BASE_ADDR        (AIPS1_OFF_BASE_ADDR + 0x64000)
-#ifdef CONFIG_MX6SLL
+#ifdef CONFIG_SOC_IMX6SLL
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define PXP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x70000)
 #define EPDC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x74000)
 #define DCP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x7C000)
-#elif defined(CONFIG_MX6SL)
+#elif defined(CONFIG_SOC_IMX6SL)
 #define CSI_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_IMX6SX)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)

@@ -247,7 +248,7 @@
 #define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_IMX6SL
 #define MSHC_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)

@@ -264,7 +265,7 @@
 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 /* i.MX6SL/SLL */
 #define RNGB_IPS_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
-#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if (defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 #define ENET2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 #else
 /* i.MX6SX */

@@ -276,7 +277,7 @@
 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SLL
+#ifdef CONFIG_SOC_IMX6SLL
 #define IOMUXC_GPR_SNVS_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IOMUXC_SNVS_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x48000)
 #endif

@@ -284,17 +285,17 @@
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6UL_LCDIF1_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define MX6ULL_LCDIF1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x48000)
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
-#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if (defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 #define SCTR_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define UART6_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x7C000)
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_IMX6SX)
 #define SAI1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x54000)
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)

@@ -317,7 +318,7 @@
 /* i.MX6SLL */
 #define MTR_MASTER_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #define GIS_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x04000)
 #define DCIC1_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x0C000)
 #define DCIC2_BASE_ADDR             (AIPS3_ARB_BASE_ADDR + 0x10000)

@@ -340,7 +341,7 @@
 #define PWM6_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xA8000)
 #define PWM7_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xAC000)
 #define PWM8_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0xB0000)
-#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#elif (defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 #define AIPS3_CONFIG_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x7C000)
 #define DCP_BASE_ADDR               (AIPS3_ARB_BASE_ADDR + 0x80000)
 #define RNGB_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x84000)

@@ -357,9 +358,9 @@
 #define MX6SX_LCDIF1_BASE_ADDR      (AIPS3_ARB_BASE_ADDR + 0x20000)
 #define MX6SX_WDOG3_BASE_ADDR       (AIPS3_ARB_BASE_ADDR + 0x88000)
 
-#if !(defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL))
+#if !(defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL) || defined(CONFIG_SOC_IMX6SLL) || \
+	defined(CONFIG_SOC_IMX6SL))
 #define IRAM_SIZE                    0x00040000
 #else
 #define IRAM_SIZE                    0x00020000

@@ -578,7 +579,8 @@ struct src {
 #define IOMUXC_GPR12_LOS_LEVEL			(0x1f << 4)
 
 struct iomuxc {
-#if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if (defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+		defined(CONFIG_SOC_IMX6ULL))
 	u8 reserved[0x4000];
 #endif
 	u32 gpr[14];

@@ -704,8 +706,9 @@ struct cspi_regs {
 #define MXC_CSPICON_POL		4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL	12 /* SS polarity */
 #define MXC_CSPICON_CTL		20 /* inactive state of SCLK */
-#if defined(CONFIG_MX6SLL) || defined(CONFIG_MX6SL) || \
-	defined(CONFIG_MX6DL) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6SLL) || defined(CONFIG_SOC_IMX6SL) || \
+	defined(CONFIG_SOC_IMX6DL) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL)
 #define MXC_SPI_BASE_ADDRESSES \
 	ECSPI1_BASE_ADDR, \
 	ECSPI2_BASE_ADDR, \

arch/arm/include/asm/arch-mx6/mx6-ddr.h +10 -10

index 19d2f1d9c5..c0aa870b62 100644
@@ -7,27 +7,27 @@
 #define __ASM_ARCH_MX6_DDR_H__
 
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_IMX6Q
 #include "mx6q-ddr.h"
 #else
-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_IMX6DL) || defined(CONFIG_SOC_IMX6S)
 #include "mx6dl-ddr.h"
 #else
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 #include "mx6sx-ddr.h"
 #else
-#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL)
 #include "mx6ul-ddr.h"
 #else
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_IMX6SL
 #include "mx6sl-ddr.h"
 #else
 #error "Please select cpu"
-#endif	/* CONFIG_MX6SL */
-#endif	/* CONFIG_MX6UL */
-#endif	/* CONFIG_MX6SX */
-#endif	/* CONFIG_MX6DL or CONFIG_MX6S */
-#endif	/* CONFIG_MX6Q */
+#endif	/* CONFIG_SOC_IMX6SL */
+#endif	/* CONFIG_SOC_IMX6UL */
+#endif	/* CONFIG_SOC_IMX6SX */
+#endif	/* CONFIG_SOC_IMX6DL or CONFIG_SOC_IMX6S */
+#endif	/* CONFIG_SOC_IMX6Q */
 #else
 
 enum {

arch/arm/include/asm/arch-mx6/mx6-pins.h +9 -9

index c2ce953206..5426fdb7a5 100644
@@ -11,7 +11,7 @@
 #define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
 	prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
 
-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_IMX6QDL
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
 	MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),

@@ -21,30 +21,30 @@ enum {
 	MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_SOC_IMX6Q)
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
 	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6q_pins.h"
 };
-#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_IMX6DL) || defined(CONFIG_SOC_IMX6S)
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
 	MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
-#elif defined(CONFIG_MX6SLL)
+#elif defined(CONFIG_SOC_IMX6SLL)
 #include "mx6sll_pins.h"
-#elif defined(CONFIG_MX6SL)
+#elif defined(CONFIG_SOC_IMX6SL)
 #include "mx6sl_pins.h"
-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_IMX6SX)
 #include "mx6sx_pins.h"
-#elif defined(CONFIG_MX6ULL)
+#elif defined(CONFIG_SOC_IMX6ULL)
 #include "mx6ull_pins.h"
-#elif defined(CONFIG_MX6UL)
+#elif defined(CONFIG_SOC_IMX6UL)
 #include "mx6ul_pins.h"
 #else
 #error "Please select cpu"
-#endif	/* CONFIG_MX6Q */
+#endif	/* CONFIG_SOC_IMX6Q */
 
 #endif	/*__ASM_ARCH_MX6_PINS_H__ */

arch/arm/include/asm/arch-mx6/mx6_plugin.S +3 -3

index b7d1b20315..10a30678fa 100644
@@ -43,7 +43,7 @@ plugin_start:
 	adr r2, boot_data2
 
 #ifdef CONFIG_NOR_BOOT
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 	ldr r3, =ROM_VERSION_OFFSET
 	ldr r4, [r3]
 	cmp r4, #ROM_VERSION_TO10

@@ -64,12 +64,12 @@ plugin_start:
 before_calling_rom___pu_irom_hwcnfg_setup:
 	ldr r3, =ROM_VERSION_OFFSET
 	ldr r4, [r3]
-#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_MX6SOLO) || defined(CONFIG_SOC_IMX6DL)
 	ldr r3, =ROM_VERSION_TO12
 	cmp r4, r3
 	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12
 	ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY
-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_SOC_IMX6Q)
 	ldr r3, =ROM_VERSION_TO15
 	cmp r4, r3
 	ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15

arch/arm/include/asm/arch-mx6/mx6dl-ddr.h +2 -2

index 1eb4b3c8b3..f82dc45f90 100644
@@ -6,8 +6,8 @@
 #ifndef __ASM_ARCH_MX6DLS_DDR_H__
 #define __ASM_ARCH_MX6DLS_DDR_H__
 
-#ifndef CONFIG_MX6DL
-#ifndef CONFIG_MX6S
+#ifndef CONFIG_SOC_IMX6DL
+#ifndef CONFIG_SOC_IMX6S
 #error "wrong CPU"
 #endif
 #endif

arch/arm/include/asm/arch-mx6/mx6q-ddr.h +1 -1

index 0aa94cffe5..a87c6b9ff8 100644
@@ -6,7 +6,7 @@
 #ifndef __ASM_ARCH_MX6Q_DDR_H__
 #define __ASM_ARCH_MX6Q_DDR_H__
 
-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_IMX6Q
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/arch-mx6/mx6sl-ddr.h +1 -1

index c3c4d69818..9f3b41a3e8 100644
@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6SL_DDR_H__
 #define __ASM_ARCH_MX6SL_DDR_H__
 
-#ifndef CONFIG_MX6SL
+#ifndef CONFIG_SOC_IMX6SL
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/arch-mx6/mx6sx-ddr.h +1 -1

index 2cc94aa4c7..8aa82db6a9 100644
@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6SX_DDR_H__
 #define __ASM_ARCH_MX6SX_DDR_H__
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/arch-mx6/mx6ul-ddr.h +1 -1

index 518b81208a..c07f1a9078 100644
@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6UL_DDR_H__
 #define __ASM_ARCH_MX6UL_DDR_H__
 
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if !(defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 #error "wrong CPU"
 #endif
 

arch/arm/include/asm/mach-imx/dma.h +1 -1

index 0244947b6e..ec1d23d6c1 100644
@@ -54,7 +54,7 @@ enum {
 	MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
 	MXS_MAX_DMA_CHANNELS,
 };
-#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#elif defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7)
 enum {
 	MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
 	MXS_DMA_CHANNEL_AHB_APBH_GPMI1,

arch/arm/include/asm/mach-imx/iomux-v3.h +6 -5

index 0c0ccf4403..9931553f38 100644
@@ -134,7 +134,7 @@ typedef u64 iomux_v3_cfg_t;
 
 #else
 
-#ifdef CONFIG_MX6
+#ifdef CONFIG_SOC_IMX6
 
 #define PAD_CTL_HYS		(1 << 16)
 

@@ -147,7 +147,8 @@ typedef u64 iomux_v3_cfg_t;
 
 #define PAD_CTL_ODE		(1 << 11)
 
-#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL)
 #define PAD_CTL_SPEED_LOW	(0 << 6)
 #else
 #define PAD_CTL_SPEED_LOW	(1 << 6)

@@ -257,7 +258,7 @@ void imx_iomux_gpio_get_function(unsigned int gpio,
 #endif
 
 /* macros for declaring and using pinmux array */
-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_IMX6QDL)
 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 #define SETUP_IOMUX_PAD(def)					\
 if (is_mx6dq() || is_mx6dqp()) {				\

@@ -267,13 +268,13 @@ if (is_mx6dq() || is_mx6dqp()) {				\
 }
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#elif defined(CONFIG_SOC_IMX6Q) || defined(CONFIG_SOC_IMX6D)
 #define IOMUX_PADS(x) MX6Q_##x
 #define SETUP_IOMUX_PAD(def)					\
 	imx_iomux_v3_setup_pad(MX6Q_##def);
 #define SETUP_IOMUX_PADS(x)					\
 	imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
-#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#elif defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL)
 #define IOMUX_PADS(x) MX6_##x
 #define SETUP_IOMUX_PAD(def)					\
 	imx_iomux_v3_setup_pad(MX6_##def);

arch/arm/include/asm/mach-imx/mxc_i2c.h +1 -1

index 80018e4a14..bce661c6d3 100644
@@ -59,7 +59,7 @@ struct mxc_i2c_bus {
 #endif
 };
 
-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_IMX6QDL)
 #define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
 	struct i2c_pads_info mx6q_##name = {		\
 		.scl = {				\

arch/arm/include/asm/mach-imx/regs-apbh.h +3 -3

index 4cc4abaf85..9283f0cc26 100644
@@ -96,7 +96,7 @@ struct mxs_apbh_regs {
 	mxs_reg_32(hw_apbh_version)
 };
 
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 struct mxs_apbh_regs {
 	mxs_reg_32(hw_apbh_ctrl0)
 	mxs_reg_32(hw_apbh_ctrl1)

@@ -275,7 +275,7 @@ struct mxs_apbh_regs {
 #define	APBH_CTRL0_CLKGATE_CHANNEL_NAND7		0x0800
 #define	APBH_CTRL0_CLKGATE_CHANNEL_HSADC		0x1000
 #define	APBH_CTRL0_CLKGATE_CHANNEL_LCDIF		0x2000
-#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 #define	APBH_CTRL0_CLKGATE_CHANNEL_OFFSET		0
 #define	APBH_CTRL0_CLKGATE_CHANNEL_NAND0		0x0001
 #define	APBH_CTRL0_CLKGATE_CHANNEL_NAND1		0x0002

@@ -391,7 +391,7 @@ struct mxs_apbh_regs {
 #define	APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF		0x2000
 #endif
 
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 #define	APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET		16
 #endif
 

arch/arm/include/asm/mach-imx/regs-bch.h +2 -2

index c0f673cc33..9a0aaf8878 100644
@@ -123,7 +123,7 @@ struct mxs_bch_regs {
 #define	BCH_FLASHLAYOUT0_NBLOCKS_OFFSET			24
 #define	BCH_FLASHLAYOUT0_META_SIZE_MASK			(0xff << 16)
 #define	BCH_FLASHLAYOUT0_META_SIZE_OFFSET		16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 #define	BCH_FLASHLAYOUT0_ECC0_MASK			(0x1f << 11)
 #define	BCH_FLASHLAYOUT0_ECC0_OFFSET			11
 #else

@@ -154,7 +154,7 @@ struct mxs_bch_regs {
 
 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_MASK			(0xffff << 16)
 #define	BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET		16
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 #define	BCH_FLASHLAYOUT1_ECCN_MASK			(0x1f << 11)
 #define	BCH_FLASHLAYOUT1_ECCN_OFFSET			11
 #else

arch/arm/include/asm/mach-imx/regs-lcdif.h +10 -11

index 38a2c6d4ee..e671e1f356 100644
@@ -19,9 +19,9 @@
 struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_ctrl)		/* 0x00 */
 	mxs_reg_32(hw_lcdif_ctrl1)		/* 0x10 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+#if defined(CONFIG_MX28) || defined(CONFIG_SOC_IMX6SX) || \
+	defined(CONFIG_SOC_IMX6SL) || defined(CONFIG_SOC_IMX6SLL) || \
+	defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
 	defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_ctrl2)		/* 0x20 */

@@ -58,9 +58,9 @@ struct mxs_lcdif_regs {
 #endif
 	mxs_reg_32(hw_lcdif_data)		/* 0x1b0/0x180 */
 	mxs_reg_32(hw_lcdif_bm_error_stat)	/* 0x1c0/0x190 */
-#if defined(CONFIG_MX28) || defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
+#if defined(CONFIG_MX28) || defined(CONFIG_SOC_IMX6SX) || \
+	defined(CONFIG_SOC_IMX6SL) || defined(CONFIG_SOC_IMX6SLL) || \
+	defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL) || \
 	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
 	defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_crc_stat)		/* 0x1a0 */

@@ -70,11 +70,10 @@ struct mxs_lcdif_regs {
 	mxs_reg_32(hw_lcdif_debug0)		/* 0x1f0/0x1d0 */
 	mxs_reg_32(hw_lcdif_debug1)		/* 0x200/0x1e0 */
 	mxs_reg_32(hw_lcdif_debug2)		/* 0x1f0 */
-#if defined(CONFIG_MX6SX) || \
-	defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \
-	defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \
-	defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
-	defined(CONFIG_MX8M)
+#if defined(CONFIG_SOC_IMX6SX) || defined(CONFIG_SOC_IMX6SL) || \
+	defined(CONFIG_SOC_IMX6SLL) || defined(CONFIG_SOC_IMX6UL) || \
+	defined(CONFIG_SOC_IMX6ULL) || defined(CONFIG_MX7) || \
+	defined(CONFIG_MX7ULP) || defined(CONFIG_MX8M)
 	mxs_reg_32(hw_lcdif_thres)
 	mxs_reg_32(hw_lcdif_as_ctrl)
 	mxs_reg_32(hw_lcdif_as_buf)

arch/arm/include/asm/mach-imx/sys_proto.h +3 -3

index 96795e1814..361e383f5b 100644
@@ -42,7 +42,7 @@
 
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
-#ifdef CONFIG_MX6
+#ifdef CONFIG_SOC_IMX6
 #define IMX6_SRC_GPR10_BMODE		BIT(28)
 
 #define IMX6_BMODE_MASK			GENMASK(7, 0)

@@ -70,7 +70,7 @@ enum imx6_bmode_emi {
 
 enum imx6_bmode {
 	IMX6_BMODE_EMI,
-#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL)
 	IMX6_BMODE_QSPI,
 	IMX6_BMODE_RESERVED,
 #else

@@ -94,7 +94,7 @@ static inline u8 imx6_is_bmode_from_gpr9(void)
 u32 imx6_src_get_boot_mode(void);
 void gpr_init(void);
 
-#endif /* CONFIG_MX6 */
+#endif /* CONFIG_SOC_IMX6 */
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);

arch/arm/mach-imx/Kconfig +6 -6

index 3aec89d440..ff4f692ae7 100644
@@ -15,7 +15,7 @@ config GPT_TIMER
 
 config IMX_RDC
 	bool "i.MX Resource domain controller driver"
-	depends on ARCH_MX6 || ARCH_MX7
+	depends on ARCH_IMX6 || ARCH_MX7
 	help
 	  i.MX Resource domain controller is used to assign masters
 	  and peripherals to differet domains. This can be used to

@@ -23,20 +23,20 @@ config IMX_RDC
 
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6
+	depends on ARCH_MX7 || ARCH_IMX6
 	help
 	  bootaux [addr] to boot auxiliary core.
 
 config USE_IMXIMG_PLUGIN
 	bool "Use imximage plugin code"
-	depends on ARCH_MX7 || ARCH_MX6
+	depends on ARCH_MX7 || ARCH_IMX6
 	help
 	  i.MX6/7 supports DCD and Plugin. Enable this configuration
 	  to use Plugin, otherwise DCD will be used.
 
 config SECURE_BOOT
 	bool "Support i.MX HAB features"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+	depends on ARCH_MX7 || ARCH_IMX6 || ARCH_MX5
 	select FSL_CAAM if HAS_CAAM
 	imply CMD_DEKBLOB
 	help

@@ -46,7 +46,7 @@ config SECURE_BOOT
 config CMD_BMODE
 	bool "Support the 'bmode' command"
 	default y
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5
+	depends on ARCH_MX7 || ARCH_IMX6 || ARCH_MX5
 	help
 	  This enables the 'bmode' (bootmode) command for forcing
 	  a boot from specific media.

@@ -73,7 +73,7 @@ config CMD_HDMIDETECT
 
 config NXP_BOARD_REVISION
 	bool "Read NXP board revision from fuses"
-	depends on ARCH_MX6 || ARCH_MX7
+	depends on ARCH_IMX6 || ARCH_MX7
 	help
 	  NXP boards based on i.MX6/7 contain the board revision information
 	  stored in the fuses. Select this option if you want to be able to

arch/arm/mach-imx/Makefile +1 -1

index 95a542fa01..494534fa25 100644
@@ -138,7 +138,7 @@ targets += $(addprefix ../../../,$(IMX_CONFIG) SPL u-boot.uim spl/u-boot-nand-sp
 obj-$(CONFIG_ARM64) += sip.o
 
 obj-$(CONFIG_MX5) += mx5/
-obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_SOC_IMX6) += mx6/
 obj-$(CONFIG_MX7) += mx7/
 obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
 obj-$(CONFIG_MX8M) += mx8m/

arch/arm/mach-imx/cache.c +1 -1

index c5279a7c8a..c74421b0d8 100644
@@ -84,7 +84,7 @@ void v7_outer_cache_enable(void)
 	 * double linefill feature. This is the default behavior.
 	 */
 
-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_IMX6Q
 	val |= 0x40800000;
 #endif
 	writel(val, &pl310->pl310_prefetch_ctrl);

arch/arm/mach-imx/cpu.c +3 -3

index 4d4d434906..2ab3db019b 100644
@@ -85,7 +85,7 @@ u32 get_imx_reset_cause(void)
 }
 #endif
 
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6)
 #if defined(CONFIG_MX53)
 #define MEMCTL_BASE	ESDCTL_BASE_ADDR
 #else

@@ -130,7 +130,7 @@ unsigned imx_ddr_size(void)
 	bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
 	bits += ESD_MMDC_CTL_GET_CS1(ctl);
 
-	/* The MX6 can do only 3840 MiB of DRAM */
+	/* The i.MX6 can do only 3840 MiB of DRAM */
 	if (bits == 32)
 		return 0xf0000000;
 

@@ -288,7 +288,7 @@ void arch_preboot_os(void)
 #endif
 #if defined(CONFIG_SATA)
 	sata_remove(0);
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 	disable_sata_clock();
 #endif
 #endif

arch/arm/mach-imx/init.c +1 -1

index 0aa8295751..9e3aaed3ee 100644
@@ -116,7 +116,7 @@ void boot_mode_apply(unsigned cfg_val)
 }
 #endif
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 u32 imx6_src_get_boot_mode(void)
 {
 	if (imx6_is_bmode_from_gpr9())

arch/arm/mach-imx/iomux-v3.c +3 -3

index 94d660015d..2bfeb1fe7e 100644
@@ -31,7 +31,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 		(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
 	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL)
+#if defined(CONFIG_SOC_IMX6SL) || defined(CONFIG_SOC_IMX6SLL)
 	/* Check whether LVE bit needs to be set */
 	if (pad_ctrl & PAD_CTL_LVE) {
 		pad_ctrl &= ~PAD_CTL_LVE;

@@ -73,7 +73,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
 #else
 	if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
 		__raw_writel(pad_ctrl, base + pad_ctrl_ofs);
-#if defined(CONFIG_MX6SLL)
+#if defined(CONFIG_SOC_IMX6SLL)
 	else if ((pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
 		clrbits_le32(base + pad_ctrl_ofs, PAD_CTL_IPD_BIT);
 #endif

@@ -94,7 +94,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 	int stride;
 	int i;
 
-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_IMX6QDL)
 	stride = 2;
 	if (!is_mx6dq() && !is_mx6dqp())
 		p += 1;

arch/arm/mach-imx/mx6/Kconfig +50 -50

index d4ce38db8d..f78ac2eaec 100644
@@ -1,4 +1,4 @@
-if ARCH_MX6
+if ARCH_IMX6
 
 config MX6_SMP
 	select ARM_ERRATA_751472

@@ -7,66 +7,66 @@ config MX6_SMP
 	select ARM_ERRATA_845369
 	bool
 
-config MX6
-	select ARM_ERRATA_743622 if !MX6UL && !MX6ULL
-	select GPT_TIMER if !MX6UL && !MX6ULL
+config SOC_IMX6
+	select ARM_ERRATA_743622 if !SOC_IMX6UL && !SOC_IMX6ULL
+	select GPT_TIMER if !SOC_IMX6UL && !SOC_IMX6ULL
 	bool
 	default y
 	imply CMD_FUSE
 
-config MX6D
+config SOC_IMX6D
 	select HAS_CAAM
 	select MX6_SMP
 	bool
 
-config MX6DL
+config SOC_IMX6DL
 	select HAS_CAAM
 	select MX6_SMP
 	bool
 
-config MX6Q
+config SOC_IMX6Q
 	select HAS_CAAM
 	select MX6_SMP
 	bool
 
-config MX6QDL
+config SOC_IMX6QDL
 	select HAS_CAAM
 	select MX6_SMP
 	bool
 
-config MX6S
+config SOC_IMX6S
 	select HAS_CAAM
 	bool
 
-config MX6SL
+config SOC_IMX6SL
 	bool
 
-config MX6SX
+config SOC_IMX6SX
 	select HAS_CAAM
 	select ROM_UNIFIED_SECTIONS
 	bool
 
-config MX6SLL
+config SOC_IMX6SLL
 	select ROM_UNIFIED_SECTIONS
 	bool
 
-config MX6UL
+config SOC_IMX6UL
 	select HAS_CAAM
 	select SYS_L2CACHE_OFF
 	select ROM_UNIFIED_SECTIONS
 	select SYSCOUNTER_TIMER
 	bool
 
-config MX6UL_LITESOM
+config SOC_IMX6UL_LITESOM
 	bool
-	select MX6UL
+	select SOC_IMX6UL
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL
 
-config MX6UL_OPOS6UL
+config SOC_IMX6UL_OPOS6UL
 	bool
-	select MX6UL
+	select SOC_IMX6UL
 	select BOARD_LATE_INIT
 	select DM
 	select DM_GPIO

@@ -74,7 +74,7 @@ config MX6UL_OPOS6UL
 	select DM_THERMAL
 	select SUPPORT_SPL
 
-config MX6ULL
+config SOC_IMX6ULL
 	select SYS_L2CACHE_OFF
 	select ROM_UNIFIED_SECTIONS
 	select SYSCOUNTER_TIMER

@@ -89,13 +89,13 @@ config MX6_DDRCAL
 	  If unsure, say N.
 
 choice
-	prompt "MX6 board select"
+	prompt "i.MX6 board select"
 	optional
 
 config TARGET_ADVANTECH_DMS_BA16
 	bool "Advantech dms-ba16"
 	select BOARD_LATE_INIT
-	select MX6Q
+	select SOC_IMX6Q
 	imply CMD_SATA
 
 config TARGET_APALIS_IMX6

@@ -120,7 +120,7 @@ config TARGET_ARISTAINETOS2B
 
 config TARGET_CGTQMX6EVAL
 	bool "cgtqmx6eval"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 	select DM

@@ -129,7 +129,7 @@ config TARGET_CGTQMX6EVAL
 config TARGET_CM_FX6
 	bool "CM-FX6"
 	select SUPPORT_SPL
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select DM
 	select DM_SERIAL

@@ -145,7 +145,7 @@ config TARGET_COLIBRI_IMX6
 
 config TARGET_DHCOMIMX6
 	bool "dh_imx6"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select BOARD_EARLY_INIT_F
 	select SUPPORT_SPL

@@ -166,21 +166,21 @@ config TARGET_EMBESTMX6BOARDS
 config TARGET_GE_B450V3
 	bool "General Electric B450v3"
 	select BOARD_LATE_INIT
-	select MX6Q
+	select SOC_IMX6Q
 
 config TARGET_GE_B650V3
 	bool "General Electric B650v3"
 	select BOARD_LATE_INIT
-	select MX6Q
+	select SOC_IMX6Q
 
 config TARGET_GE_B850V3
 	bool "General Electric B850v3"
 	select BOARD_LATE_INIT
-	select MX6Q
+	select SOC_IMX6Q
 
 config TARGET_GW_VENTANA
 	bool "gw_ventana"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select SUPPORT_SPL
 	imply CMD_SATA
 	imply CMD_SPL

@@ -192,12 +192,12 @@ config TARGET_KOSAGI_NOVENA
 
 config TARGET_MCCMON6
 	bool "mccmon6"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select SUPPORT_SPL
 
 config TARGET_MX6CUBOXI
 	bool "Solid-run mx6 boards"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 

@@ -228,7 +228,7 @@ config TARGET_MX6QARM2
 config TARGET_MX6Q_ENGICAM
 	bool "Support Engicam i.Core(RQS)"
 	select BOARD_LATE_INIT
-	select MX6QDL
+	select SOC_IMX6QDL
 	select OF_CONTROL
 	select SPL_OF_LIBFDT
 	select DM

@@ -245,7 +245,7 @@ config TARGET_MX6Q_ENGICAM
 
 config TARGET_MX6SABREAUTO
 	bool "mx6sabreauto"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 	select DM

@@ -254,7 +254,7 @@ config TARGET_MX6SABREAUTO
 
 config TARGET_MX6SABRESD
 	bool "mx6sabresd"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 	select DM

@@ -263,20 +263,20 @@ config TARGET_MX6SABRESD
 
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
-	select MX6SL
+	select SOC_IMX6SL
 	select SUPPORT_SPL
 
 config TARGET_MX6SLLEVK
         bool "mx6sll evk"
 	select BOARD_LATE_INIT
-        select MX6SLL
+        select SOC_IMX6SLL
         select DM
         select DM_THERMAL
 
 config TARGET_MX6SXSABRESD
 	bool "mx6sxsabresd"
 	select BOARD_LATE_INIT
-	select MX6SX
+	select SOC_IMX6SX
 	select SUPPORT_SPL
 	select DM
 	select DM_THERMAL

@@ -285,7 +285,7 @@ config TARGET_MX6SXSABRESD
 config TARGET_MX6SXSABREAUTO
         bool "mx6sxsabreauto"
 	select BOARD_LATE_INIT
-	select MX6SX
+	select SOC_IMX6SX
         select DM
         select DM_THERMAL
 	select BOARD_EARLY_INIT_F

@@ -293,7 +293,7 @@ config TARGET_MX6SXSABREAUTO
 config TARGET_MX6UL_9X9_EVK
 	bool "mx6ul_9x9_evk"
 	select BOARD_LATE_INIT
-	select MX6UL
+	select SOC_IMX6UL
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL

@@ -301,7 +301,7 @@ config TARGET_MX6UL_9X9_EVK
 config TARGET_MX6UL_14X14_EVK
 	select BOARD_LATE_INIT
 	bool "mx6ul_14x14_evk"
-	select MX6UL
+	select SOC_IMX6UL
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL

@@ -309,7 +309,7 @@ config TARGET_MX6UL_14X14_EVK
 config TARGET_MX6UL_ENGICAM
 	bool "Support Engicam GEAM6UL/Is.IoT"
 	select BOARD_LATE_INIT
-	select MX6UL
+	select SOC_IMX6UL
 	select OF_CONTROL
 	select DM
 	select DM_ETH

@@ -326,7 +326,7 @@ config TARGET_MX6UL_ENGICAM
 config TARGET_MX6ULL_14X14_EVK
 	bool "Support mx6ull_14x14_evk"
 	select BOARD_LATE_INIT
-	select MX6ULL
+	select SOC_IMX6ULL
 	select DM
 	select DM_THERMAL
 

@@ -339,7 +339,7 @@ config TARGET_NITROGEN6X
 
 config TARGET_OPOS6ULDEV
 	bool "Armadeus OPOS6ULDev board"
-	select MX6UL_OPOS6UL
+	select SOC_IMX6UL_OPOS6UL
 
 config TARGET_OT1200
 	bool "Bachmann OT1200"

@@ -348,12 +348,12 @@ config TARGET_OT1200
 
 config TARGET_PICO_IMX6UL
 	bool "PICO-IMX6UL-EMMC"
-	select MX6UL
+	select SOC_IMX6UL
 
 config TARGET_LITEBOARD
 	bool "Grinn liteBoard (i.MX6UL)"
 	select BOARD_LATE_INIT
-	select MX6UL_LITESOM
+	select SOC_IMX6UL_LITESOM
 
 config TARGET_PLATINUM_PICON
 	bool "platinum-picon"

@@ -370,7 +370,7 @@ config TARGET_PCM058
 
 config TARGET_PFLA02
 	bool "Phytec PFLA02 (PhyFlex) i.MX6 Quad"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 

@@ -393,7 +393,7 @@ config TARGET_TQMA6
 
 config TARGET_UDOO
 	bool "udoo"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 

@@ -401,32 +401,32 @@ config TARGET_UDOO_NEO
 	bool "UDOO Neo"
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
-	select MX6SX
+	select SOC_IMX6SX
 	select DM
 	select DM_THERMAL
 
 config TARGET_SAMTEC_VINING_2000
 	bool "samtec VIN|ING 2000"
 	select BOARD_LATE_INIT
-	select MX6SX
+	select SOC_IMX6SX
 	select DM
 	select DM_THERMAL
 
 config TARGET_WANDBOARD
 	bool "wandboard"
-	select MX6QDL
+	select SOC_IMX6QDL
 	select BOARD_LATE_INIT
 	select SUPPORT_SPL
 
 config TARGET_WARP
 	bool "WaRP"
-	select MX6SL
+	select SOC_IMX6SL
 	select BOARD_LATE_INIT
 
 config TARGET_XPRESS
 	bool "CCV xPress"
 	select BOARD_LATE_INIT
-	select MX6UL
+	select SOC_IMX6UL
 	select DM
 	select DM_THERMAL
 	select SUPPORT_SPL

arch/arm/mach-imx/mx6/Makefile +2 -2

index c183eb4a2f..37a5d5d422 100644
@@ -10,5 +10,5 @@
 obj-y	:= soc.o clock.o
 obj-$(CONFIG_SPL_BUILD)	     += ddr.o
 obj-$(CONFIG_MP)             += mp.o
-obj-$(CONFIG_MX6UL_LITESOM)  += litesom.o
-obj-$(CONFIG_MX6UL_OPOS6UL)  += opos6ul.o
+obj-$(CONFIG_SOC_IMX6UL_LITESOM)  += litesom.o
+obj-$(CONFIG_SOC_IMX6UL_OPOS6UL)  += opos6ul.o

arch/arm/mach-imx/mx6/clock.c +7 -7

index 71a9e6bca0..1a14d95822 100644
@@ -41,7 +41,7 @@ void enable_ocotp_clk(unsigned char enable)
 #ifdef CONFIG_NAND_MXS
 void setup_gpmi_io_clk(u32 cfg)
 {
-	/* Disable clocks per ERR007177 from MX6 errata */
+	/* Disable clocks per ERR007177 from i.MX6 errata */
 	clrbits_le32(&imx_ccm->CCGR4,
 		     MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |

@@ -49,7 +49,7 @@ void setup_gpmi_io_clk(u32 cfg)
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 
-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_SOC_IMX6SX)
 	clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
 
 	clrsetbits_le32(&imx_ccm->cs2cdr,

@@ -92,7 +92,7 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
-#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
+#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_IMX6SX)
 void enable_enet_clk(unsigned char enable)
 {
 	u32 mask, *addr;

@@ -949,7 +949,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 	reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
 	writel(reg, &anatop->pll_enet);
 
-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_IMX6SX
 	/* Disable enet system clcok before switching clock parent */
 	reg = readl(&imx_ccm->CCGR3);
 	reg &= ~MXC_CCM_CCGR3_ENET_MASK;

@@ -1312,7 +1312,7 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_IMX6SX
 void enable_ipu_clock(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

@@ -1328,8 +1328,8 @@ void enable_ipu_clock(void)
 }
 #endif
 
-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \
-	defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_IMX6Q) || defined(CONFIG_SOC_IMX6D) || \
+	defined(CONFIG_SOC_IMX6DL) || defined(CONFIG_SOC_IMX6S)
 static void disable_ldb_di_clock_sources(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

arch/arm/mach-imx/mx6/ddr.c +11 -9

index 43b77cfa41..f8f50b2bf9 100644
@@ -572,8 +572,8 @@ int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 }
 #endif
 
-#if defined(CONFIG_MX6SX)
-/* Configure MX6SX mmdc iomux */
+#if defined(CONFIG_SOC_IMX6SX)
+/* Configure i.MX6SX mmdc iomux */
 void mx6sx_dram_iocfg(unsigned width,
 		      const struct mx6sx_iomux_ddr_regs *ddr,
 		      const struct mx6sx_iomux_grp_regs *grp)

@@ -631,7 +631,7 @@ void mx6sx_dram_iocfg(unsigned width,
 }
 #endif
 
-#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL)
 void mx6ul_dram_iocfg(unsigned width,
 		      const struct mx6ul_iomux_ddr_regs *ddr,
 		      const struct mx6ul_iomux_grp_regs *grp)

@@ -675,7 +675,7 @@ void mx6ul_dram_iocfg(unsigned width,
 }
 #endif
 
-#if defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_IMX6SL)
 void mx6sl_dram_iocfg(unsigned width,
 		      const struct mx6sl_iomux_ddr_regs *ddr,
 		      const struct mx6sl_iomux_grp_regs *grp)

@@ -730,7 +730,8 @@ void mx6sl_dram_iocfg(unsigned width,
 }
 #endif
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_SOC_IMX6QDL) || defined(CONFIG_SOC_IMX6Q) || \
+	defined(CONFIG_SOC_IMX6D)
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
 		      const struct mx6dq_iomux_ddr_regs *ddr,

@@ -808,7 +809,8 @@ void mx6dq_dram_iocfg(unsigned width,
 }
 #endif
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_IMX6QDL) || defined(CONFIG_SOC_IMX6DL) || \
+	defined(CONFIG_SOC_IMX6S)
 /* Configure MX6SDL mmdc iomux */
 void mx6sdl_dram_iocfg(unsigned width,
 		       const struct mx6sdl_iomux_ddr_regs *ddr,

@@ -1218,14 +1220,14 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
-	/* Limit mem_speed for MX6D/MX6Q */
+	/* Limit mem_speed for i.MX6D/i.MX6Q */
 	if (is_mx6dq() || is_mx6dqp()) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
 		tcwl = 4;
 	}
-	/* Limit mem_speed for MX6S/MX6DL */
+	/* Limit mem_speed for i.MX6S/i.MX6DL */
 	else {
 		if (mem_speed > 800)
 			mem_speed = 800;  /* 800 MT/s */

@@ -1235,7 +1237,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 
 	clock = mem_speed / 2;
 	/*
-	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
+	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but i.MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
 	if (is_mx6dq() || is_mx6dqp()) {

arch/arm/mach-imx/mx6/soc.c +3 -3

index 9b3d8f69b2..1b9f26270f 100644
@@ -528,7 +528,7 @@ int board_postclk_init(void)
 const struct boot_mode soc_boot_modes[] = {
 	{"normal",	MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
 	/* reserved value should start rom usb */
-#if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)
+#if defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL)
 	{"usb",		MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
 #else
 	{"usb",		MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},

@@ -565,9 +565,9 @@ void s_init(void)
 	if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll())
 		return;
 
-	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
+	/* Due to hardware limitation, on i.MX6Q we need to gate/ungate all PFDs
 	 * to make sure PFD is working right, otherwise, PFDs may
-	 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
+	 * not output clock after reset, i.MX6DL and i.MX6SL have added 396M pfd
 	 * workaround in ROM code, as bus clock need it
 	 */
 

arch/arm/mach-imx/spl.c +4 -4

index b2521b2101..c084acb1ca 100644
@@ -19,7 +19,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
 {

@@ -61,7 +61,7 @@ u32 spl_boot_device(void)
 	case IMX6_BMODE_RESERVED:
 		return BOOT_DEVICE_BOARD;
 	/* SATA: See 8.5.4, Table 8-20 */
-#if !defined(CONFIG_MX6UL) && !defined(CONFIG_MX6ULL)
+#if !defined(CONFIG_SOC_IMX6UL) && !defined(CONFIG_SOC_IMX6ULL)
 	case IMX6_BMODE_SATA:
 		return BOOT_DEVICE_SATA;
 #endif

@@ -121,7 +121,7 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
-#endif /* CONFIG_MX6 || CONFIG_MX7 || CONFIG_MX8M */
+#endif /* CONFIG_SOC_IMX6 || CONFIG_MX7 || CONFIG_MX8M */
 
 #ifdef CONFIG_SPL_USB_GADGET_SUPPORT
 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)

@@ -213,7 +213,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
 
 #endif
 
-#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
+#if defined(CONFIG_SOC_IMX6) && defined(CONFIG_SPL_OS_BOOT)
 int dram_init_banksize(void)
 {
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;

arch/arm/mach-imx/timer.c +1 -1

index 69dbf3c2ce..ced5c9e961 100644
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static inline int gpt_has_clk_source_osc(void)
 {
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
 	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
 	    is_mx6ull() || is_mx6sll())

board/bachmann/ot1200/ot1200_spl.c +2 -2

index f3dff95710..62c5e3fa5d 100644
@@ -10,7 +10,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Configure MX6Q/DUAL mmdc DDR io registers */
+/* Configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
 	.dram_sdclk_0   = 0x00000028,

@@ -46,7 +46,7 @@ static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = {
 	.dram_dqm7      = 0x00000028,
 };
 
-/* Configure MX6Q/DUAL mmdc GRP io registers */
+/* Configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type    = 0x000c0000,

board/barco/platinum/spl_picon.c +2 -2

index f49adf0329..182e5db708 100644
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef RTT_NOM_120OHM	/* use 120ohm Rtt_nom vs 60ohm (lower power) */
 
-/* Configure MX6Q/DUAL mmdc DDR io registers */
+/* Configure i.MX6Q/DUAL mmdc DDR io registers */
 struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 	.dram_sdclk_0 = 0x00020030,

@@ -61,7 +61,7 @@ struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
 	.dram_dqm7 = 0x00020030,
 };
 
-/* Configure MX6Q/DUAL mmdc GRP io registers */
+/* Configure i.MX6Q/DUAL mmdc GRP io registers */
 struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type = 0x000c0000,

board/barco/platinum/spl_titanium.c +2 -2

index c27fb4836a..77117abd7a 100644
@@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #undef RTT_NOM_120OHM	/* use 120ohm Rtt_nom vs 60ohm (lower power) */
 
-/* Configure MX6Q/DUAL mmdc DDR io registers */
+/* Configure i.MX6Q/DUAL mmdc DDR io registers */
 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 	.dram_sdclk_0 = 0x00020030,

@@ -61,7 +61,7 @@ struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = 0x00020030,
 };
 
-/* Configure MX6Q/DUAL mmdc GRP io registers */
+/* Configure i.MX6Q/DUAL mmdc GRP io registers */
 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type = 0x000c0000,

board/boundary/nitrogen6x/ddr-setup.cfg +4 -4

index 2748d40084..a018bbacb4 100644
@@ -16,10 +16,10 @@
 
 /*
  * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	        memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	        memory bus width: 64 bits	x16/x32/x64
  * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
  *	   memory bus width: 32 bits	x16/x32
  */

board/compulab/cm_fx6/cm_fx6.c +3 -3

index 673de03071..9dc6bd4785 100644
@@ -607,7 +607,7 @@ int board_init(void)
 
 	cm_fx6_setup_display();
 
-	/* This should be done in the MMC driver when MX6 has a clock driver */
+	/* This should be done in the MMC driver when i.MX6 has a clock driver */
 #ifdef CONFIG_FSL_ESDHC
 	if (IS_ENABLED(CONFIG_BLK)) {
 		int i;

@@ -628,9 +628,9 @@ int board_late_init(void)
 	int err;
 
 	if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else if (is_mx6dl())
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 
 	err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 	if (err)

board/congatec/cgtqmx6eval/cgtqmx6eval.c +2 -2

index 1647b61100..47900e85c1 100644
@@ -756,9 +756,9 @@ int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 #endif
 
 	return 0;

board/dhelectronics/dh_imx6/dh_imx6.c +2 -2

index b00d0e4b6d..19e8ed7223 100644
@@ -245,8 +245,8 @@ int board_mmc_init(bd_t *bis)
 static void setup_usb(void)
 {
 	/*
-	 * Set daisy chain for otg_pin_id on MX6Q.
-	 * For MX6DL, this bit is reserved.
+	 * Set daisy chain for otg_pin_id on i.MX6Q.
+	 * For i.MX6DL, this bit is reserved.
 	 */
 	imx_iomux_set_gpr_register(1, 13, 1, 0);
 }

board/engicam/common/spl.c +12 -12

index 6e2389dd4b..1f50348c36 100644
@@ -30,10 +30,10 @@ DECLARE_GLOBAL_DATA_PTR;
         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
 static iomux_v3_cfg_t const uart_pads[] = {
-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_IMX6QDL
         IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
         IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
-#elif CONFIG_MX6UL
+#elif CONFIG_SOC_IMX6UL
 	IOMUX_PADS(PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL)),
 	IOMUX_PADS(PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL)),
 #endif

@@ -92,7 +92,7 @@ int spl_start_uboot(void)
 }
 #endif
 
-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_IMX6QDL
 /*
  * Driving strength:
  *   0x30 == 40 Ohm

@@ -101,7 +101,7 @@ int spl_start_uboot(void)
 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH		0x28
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,

@@ -131,7 +131,7 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
 	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,

@@ -293,9 +293,9 @@ static struct mx6_ddr_sysinfo mem_s = {
 	.rst_to_cke	= 0x23,
 	.sde_to_rst	= 0x10,
 };
-#endif /* CONFIG_MX6QDL */
+#endif /* CONFIG_SOC_IMX6QDL */
 
-#ifdef CONFIG_MX6UL
+#ifdef CONFIG_SOC_IMX6UL
 static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
 	.grp_addds = 0x00000030,
 	.grp_ddrmode_ctl = 0x00020000,

@@ -360,13 +360,13 @@ static struct mx6_ddr3_cfg mem_ddr = {
 	.trcmin = 4875,
 	.trasmin = 3500,
 };
-#endif /* CONFIG_MX6UL */
+#endif /* CONFIG_SOC_IMX6UL */
 
 static void ccgr_init(void)
 {
 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_IMX6QDL
 	writel(0x00003F3F, &ccm->CCGR0);
 	writel(0x0030FC00, &ccm->CCGR1);
 	writel(0x000FC000, &ccm->CCGR2);

@@ -374,7 +374,7 @@ static void ccgr_init(void)
 	writel(0xFF00F300, &ccm->CCGR4);
 	writel(0x0F0000C3, &ccm->CCGR5);
 	writel(0x000003CC, &ccm->CCGR6);
-#elif CONFIG_MX6UL
+#elif CONFIG_SOC_IMX6UL
 	writel(0x00c03f3f, &ccm->CCGR0);
 	writel(0xfcffff00, &ccm->CCGR1);
 	writel(0x0cffffcc, &ccm->CCGR2);

@@ -387,7 +387,7 @@ static void ccgr_init(void)
 
 static void spl_dram_init(void)
 {
-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_IMX6QDL
 	if (is_mx6solo()) {
 		mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
 		mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256);

@@ -398,7 +398,7 @@ static void spl_dram_init(void)
 		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 		mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256);
 	}
-#elif CONFIG_MX6UL
+#elif CONFIG_SOC_IMX6UL
 	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 #endif

board/freescale/mx6memcal/spl.c +3 -3

index b4b50db772..b08def69aa 100644
@@ -54,7 +54,7 @@ static iomux_v3_cfg_t const uart_pads[] = {
 #define DRAM_DRIVE_STRENGTH \
 	(CONFIG_DRAM_DRIVE_STRENGTH << 3)
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 	.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,

@@ -91,7 +91,7 @@ static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
 	.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type = GRP_DDRTYPE,

@@ -426,7 +426,7 @@ void board_init_f(ulong dummy)
 			reset_cpu(0);
 		}
 	}
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_IMX6SL
 	mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
 			 &mx6sl_grp_ioregs);
 #else

board/freescale/mx6qarm2/mx6qarm2.c +4 -4

index 8cb5ac5940..22aaa5ebac 100644
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
-#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
+#if defined(CONFIG_SOC_IMX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
 	defined(CONFIG_DDR_32BIT)
 	gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
 #else

@@ -278,10 +278,10 @@ int board_init(void)
 
 int checkboard(void)
 {
-#ifdef CONFIG_MX6DL
-	puts("Board: MX6DL-Armadillo2\n");
+#ifdef CONFIG_SOC_IMX6DL
+	puts("Board: i.MX6DL-Armadillo2\n");
 #else
-	puts("Board: MX6Q-Armadillo2\n");
+	puts("Board: i.MX6Q-Armadillo2\n");
 #endif
 
 	return 0;

board/freescale/mx6sabreauto/mx6sabreauto.c +4 -4

index 52b016b91d..d168c8348a 100644
@@ -661,11 +661,11 @@ int board_late_init(void)
 	env_set("board_name", "SABREAUTO");
 
 	if (is_mx6dqp())
-		env_set("board_rev", "MX6QP");
+		env_set("board_rev", "i.MX6QP");
 	else if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else if (is_mx6sdl())
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 #endif
 
 	return 0;

@@ -673,7 +673,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
+	printf("Board: i.MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
 
 	return 0;
 }

board/freescale/mx6sabresd/mx6sabresd.c +4 -4

index d75dd88dbc..d98ce42497 100644
@@ -706,11 +706,11 @@ int board_late_init(void)
 	env_set("board_name", "SABRESD");
 
 	if (is_mx6dqp())
-		env_set("board_rev", "MX6QP");
+		env_set("board_rev", "i.MX6QP");
 	else if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else if (is_mx6sdl())
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 #endif
 
 	return 0;

@@ -718,7 +718,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6-SabreSD\n");
+	puts("Board: i.MX6-SabreSD\n");
 	return 0;
 }
 

board/freescale/mx6sllevk/mx6sllevk.c +1 -1

index 33aada179f..8873413739 100644
@@ -115,7 +115,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6SLL EVK\n");
+	puts("Board: i.MX6SLL EVK\n");
 
 	return 0;
 }

board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +1 -1

index 83473d80b0..b60892a730 100644
@@ -356,7 +356,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6SX SABRE AUTO\n");
+	puts("Board: i.MX6SX SABRE AUTO\n");
 
 	return 0;
 }

board/freescale/mx6sxsabresd/mx6sxsabresd.c +1 -1

index 6c135130c9..9d82d68a43 100644
@@ -341,7 +341,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
+	printf("Board: i.MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
 
 	return 0;
 }

board/freescale/mx6ul_14x14_evk/README +3 -3

index 1edccf688c..902d048dbc 100644
@@ -1,7 +1,7 @@
-How to use U-Boot on Freescale MX6UL 14x14 EVK
------------------------------------------------
+How to use U-Boot on Freescale i.MX6UL 14x14 EVK
+------------------------------------------------
 
-- Build U-Boot for MX6UL 14x14 EVK:
+- Build U-Boot for i.MX6UL 14x14 EVK:
 
 $ make mrproper
 $ make mx6ul_14x14_evk_defconfig

board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +2 -2

index a7b0fa86e0..071e60c6df 100644
@@ -688,9 +688,9 @@ int board_late_init(void)
 int checkboard(void)
 {
 	if (is_mx6ul_9x9_evk())
-		puts("Board: MX6UL 9x9 EVK\n");
+		puts("Board: i.MX6UL 9x9 EVK\n");
 	else
-		puts("Board: MX6UL 14x14 EVK\n");
+		puts("Board: i.MX6UL 14x14 EVK\n");
 
 	return 0;
 }

board/freescale/mx6ullevk/README +3 -3

index d5c8770863..786adbb8b5 100644
@@ -1,11 +1,11 @@
-How to use U-Boot on Freescale MX6ULL 14x14 EVK
-----------------------------------------------
+How to use U-Boot on Freescale i.MX6ULL 14x14 EVK
+-------------------------------------------------
 
 - First make sure you have installed the dtc package (device tree compiler):
 
 $ sudo apt-get install device-tree-compiler
 
-- Build U-Boot for MX6ULL 14x14 EVK:
+- Build U-Boot for i.MX6ULL 14x14 EVK:
 
 $ make mrproper
 $ make mx6ull_14x14_evk_defconfig

board/freescale/mx6ullevk/mx6ullevk.c +1 -1

index cebcec738f..dc9e30bb3e 100644
@@ -93,7 +93,7 @@ int board_late_init(void)
 
 int checkboard(void)
 {
-	puts("Board: MX6ULL 14x14 EVK\n");
+	puts("Board: i.MX6ULL 14x14 EVK\n");
 
 	return 0;
 }

board/gateworks/gw_ventana/gw_ventana_spl.c +2 -2

index bdbe5e7027..724466c9f0 100644
@@ -27,7 +27,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GSC_EEPROM_DDR_SIZE	0x2B	/* enum (512,1024,2048) MB */
 #define GSC_EEPROM_DDR_WIDTH	0x2D	/* enum (32,64) bit */
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 	.dram_sdclk_0 = 0x00020030,

@@ -64,7 +64,7 @@ struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = 0x00020030,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type = 0x000c0000,

board/kosagi/novena/novena_spl.c +2 -2

index b4a68da88f..a99d794f69 100644
@@ -425,7 +425,7 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-/* Configure MX6Q/DUAL mmdc DDR io registers */
+/* Configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
 	/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
 	.dram_sdclk_0		= 0x00020038,

@@ -462,7 +462,7 @@ static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
 	.dram_dqm7		= 0x00000038,
 };
 
-/* Configure MX6Q/DUAL mmdc GRP io registers */
+/* Configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
 	/* DDR3 */
 	.grp_ddr_type		= 0x000c0000,

board/liebherr/mccmon6/spl.c +2 -2

index 196da46df9..d975be64c5 100644
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH		0x28
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,

@@ -63,7 +63,7 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,

board/logicpd/imx6/imx6logic.c +1 -1

index 1f3e378ffc..5e5f1674b8 100644
@@ -177,7 +177,7 @@ int board_late_init(void)
 	env_set("board_name", "imx6logic");
 
 	if (is_mx6dq()) {
-		env_set("board_rev", "MX6DQ");
+		env_set("board_rev", "i.MX6DQ");
 		env_set("fdt_file", "imx6q-logicpd.dtb");
 	}
 

board/seco/Kconfig +3 -3

index af1669733f..0a37f5d5bb 100644
@@ -21,15 +21,15 @@ choice
 
 config SECOMX6Q
 	bool "i.MX6Q"
-	select MX6Q
+	select SOC_IMX6Q
 
 config SECOMX6DL
 	bool "i.MX6DL"
-	select MX6DL
+	select SOC_IMX6DL
 
 config SECOMX6S
 	bool "i.MX6S"
-	select MX6S
+	select SOC_IMX6S
 
 endchoice
 

board/solidrun/mx6cuboxi/mx6cuboxi.c +5 -5

index ee9e4f7c01..d2cccd3935 100644
@@ -393,11 +393,11 @@ static bool is_hummingboard2(void)
 int checkboard(void)
 {
 	if (is_hummingboard2())
-		puts("Board: MX6 Hummingboard2\n");
+		puts("Board: i.MX6 Hummingboard2\n");
 	else if (is_hummingboard())
-		puts("Board: MX6 Hummingboard\n");
+		puts("Board: i.MX6 Hummingboard\n");
 	else
-		puts("Board: MX6 Cubox-i\n");
+		puts("Board: i.MX6 Cubox-i\n");
 
 	return 0;
 }

@@ -413,9 +413,9 @@ int board_late_init(void)
 		env_set("board_name", "CUBOXI");
 
 	if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 #endif
 
 	return 0;

board/tbs/tbs2910/Kconfig +1 -1

index 2e5e1d492a..09e14e1b59 100644
@@ -9,7 +9,7 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "tbs2910"
 
-config MX6Q
+config SOC_IMX6Q
 	default y
 
 config IMX_CONFIG

board/toradex/apalis_imx6/ddr-setup.cfg +4 -4

index de7cdd6d63..301138645a 100644
@@ -17,10 +17,10 @@
 
 /*
  * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	        memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6DL   ddr is limited to 800 MHz(400 MHz clock)
+ *	        memory bus width: 64 bits	x16/x32/x64
  * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
  *	   memory bus width: 32 bits	x16/x32
  */

board/toradex/colibri_imx6/ddr-setup.cfg +4 -4

index f46ae55ced..5ad87588bd 100644
@@ -17,10 +17,10 @@
 
 /*
  * DDR3 settings
- * MX6Q    ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
- *	   memory bus width: 64 bits	x16/x32/x64
- * MX6DL   ddr is limited to 800 MHz(400 MHz clock)
- *	   memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6Q  ddr is limited to 1066 Mhz	currently 1056 MHz(528 MHz clock),
+ *	      memory bus width: 64 bits	x16/x32/x64
+ * SOC_IMX6DL ddr is limited to 800 MHz(400 MHz clock)
+ *	      memory bus width: 64 bits	x16/x32/x64
  * MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
  *	   memory bus width: 32 bits	x16/x32
  */

board/tqc/tqma6/Kconfig +3 -3

index 6df4134286..f140ad6908 100644
@@ -18,19 +18,19 @@ choice
 
 config TQMA6Q
 	bool "TQMa6Q / TQMa6D"
-	select MX6Q
+	select SOC_IMX6Q
 	help
 	  select TQMa6Q / TQMa6D with i.MX6Q/D and 1GiB DRAM
 
 config TQMA6DL
 	bool "TQMa6DL"
-	select MX6DL
+	select SOC_IMX6DL
 	help
 	  select TQMa6DL with i.MX6DL and 1GiB DRAM
 
 config TQMA6S
 	bool "TQMa6S"
-	select MX6S
+	select SOC_IMX6S
 	help
 	  select TQMa6S with i.MX6S and 512 MiB DRAM
 

board/udoo/README +2 -2

index 6fbcc598f7..3d47e1348e 100644
@@ -1,7 +1,7 @@
-How to use U-Boot on MX6Q/DL Udoo boards
+How to use U-Boot on i.MX6Q/DL Udoo boards
 ----------------------------------------
 
-- Build U-Boot for MX6Q/DL Udoo boards:
+- Build U-Boot for i.MX6Q/DL Udoo boards:
 
 $ make mrproper
 $ make udoo_defconfig

board/udoo/udoo.c +2 -2

index 562f0d863e..ad1877fa79 100644
@@ -254,9 +254,9 @@ int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	if (is_cpu_type(MXC_CPU_MX6Q))
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 #endif
 	return 0;
 }

board/udoo/udoo_spl.c +2 -2

index 694055bd2e..daf453ff43 100644
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IMX6DQ_DRIVE_STRENGTH		0x30
 #define IMX6SDL_DRIVE_STRENGTH	0x28
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,

@@ -64,7 +64,7 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,

board/wandboard/spl.c +4 -4

index 5b9622e75e..5f4f00ae03 100644
@@ -34,7 +34,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define IMX6SDL_DRIVE_STRENGTH		0x28
 #define IMX6QP_DRIVE_STRENGTH		0x28
 
-/* configure MX6Q/DUAL mmdc DDR io registers */
+/* configure i.MX6Q/DUAL mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,

@@ -64,7 +64,7 @@ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
 	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
 };
 
-/* configure MX6QP mmdc DDR io registers */
+/* configure i.MX6QP mmdc DDR io registers */
 static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
 	.dram_sdclk_0 = IMX6QP_DRIVE_STRENGTH,
 	.dram_sdclk_1 = IMX6QP_DRIVE_STRENGTH,

@@ -94,7 +94,7 @@ static struct mx6dq_iomux_ddr_regs mx6qp_ddr_ioregs = {
 	.dram_dqm7 = IMX6QP_DRIVE_STRENGTH,
 };
 
-/* configure MX6Q/DUAL mmdc GRP io registers */
+/* configure i.MX6Q/DUAL mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,

@@ -112,7 +112,7 @@ static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
 	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
 };
 
-/* configure MX6QP mmdc GRP io registers */
+/* configure i.MX6QP mmdc GRP io registers */
 static struct mx6dq_iomux_grp_regs mx6qp_grp_ioregs = {
 	.grp_ddr_type = 0x000c0000,
 	.grp_ddrmode_ctl = 0x00020000,

board/wandboard/wandboard.c +3 -3

index 1e7c11e670..b9972d44a7 100644
@@ -511,11 +511,11 @@ int board_late_init(void)
 
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	if (is_mx6dqp())
-		env_set("board_rev", "MX6QP");
+		env_set("board_rev", "i.MX6QP");
 	else if (is_mx6dq())
-		env_set("board_rev", "MX6Q");
+		env_set("board_rev", "i.MX6Q");
 	else
-		env_set("board_rev", "MX6DL");
+		env_set("board_rev", "i.MX6DL");
 
 	if (is_revd1())
 		env_set("board_name", "D1");

cmd/fastboot/Kconfig +2 -1

index 0d2c2f131e..bba199b3ef 100644
@@ -30,7 +30,8 @@ if USB_FUNCTION_FASTBOOT
 
 config FASTBOOT_BUF_ADDR
 	hex "Define FASTBOOT buffer address"
-	default 0x82000000 if MX6SX || MX6SL || MX6UL || MX6SLL
+	default 0x82000000 if SOC_IMX6SX || SOC_IMX6SL || SOC_IMX6UL || \
+				SOC_IMX6SLL
 	default 0x81000000 if ARCH_OMAP2PLUS
 	default 0x42000000 if ARCH_SUNXI && !MACH_SUN9I
 	default 0x22000000 if ARCH_SUNXI && MACH_SUN9I

common/spl/Kconfig +3 -3

index b9b9e0f3a0..af27f2d7b7 100644
@@ -56,7 +56,7 @@ config SPL_BOOTROM_SUPPORT
 
 config SPL_RAW_IMAGE_SUPPORT
 	bool "Support SPL loading and booting of RAW images"
-	default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
+	default n if (ARCH_IMX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT))
 	default y if !TI_SECURE_DEVICE
 	help
 	  SPL will support loading and booting a RAW image when this option

@@ -143,7 +143,7 @@ config SPL_DISPLAY_PRINT
 
 config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 	bool "MMC raw mode: by sector"
-	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_MX6 || \
+	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER ||ARCH_IMX6 || \
 		     ARCH_ROCKCHIP || ARCH_MVEBU ||  ARCH_SOCFPGA || \
 		     ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
 		     OMAP44XX || OMAP54XX || AM33XX || AM43XX

@@ -156,7 +156,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 	default 0x50 if ARCH_SUNXI
 	default 0x75 if ARCH_DAVINCI
-	default 0x8a if ARCH_MX6
+	default 0x8a if ARCH_IMX6
 	default 0x100 if ARCH_UNIPHIER
 	default 0x140 if ARCH_MVEBU
 	default 0x200 if ARCH_SOCFPGA || ARCH_AT91

common/spl/spl.c +1 -1

index b1ce56d0d0..c6fcaac15a 100644
@@ -399,7 +399,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
 		if (spl_init())
 			hang();
 	}
-#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_MX6)
+#if !defined(CONFIG_PPC) && !defined(CONFIG_ARCH_IMX6)
 	/*
 	 * timer_init() does not exist on PPC systems. The timer is initialized
 	 * and enabled (decrementer) in interrupt_init() here.

configs/apalis_imx6_defconfig +2 -2

index 7b6adadc14..b27648b460 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -9,7 +9,7 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SUPPORT_RAW_INITRD=y

configs/apalis_imx6_nospl_com_defconfig +2 -2

index d6e3787221..eee36a21c5 100644
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_APALIS_IMX6=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,SOC_IMX6Q,DDR_MB=1024"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SUPPORT_RAW_INITRD=y

configs/apalis_imx6_nospl_it_defconfig +2 -2

index 306f96763b..2d45b9107d 100644
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_APALIS_IMX6=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,MX6Q,DDR_MB=2048"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis_imx6/apalis_imx6q.cfg,SOC_IMX6Q,DDR_MB=2048"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SUPPORT_RAW_INITRD=y

configs/aristainetos2_defconfig +2 -2

index 8343846e19..040f8613be 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_ARISTAINETOS2=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,SOC_IMX6DL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/aristainetos2b_defconfig +2 -2

index b49b1f24d0..f23b24596f 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_ARISTAINETOS2B=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,SOC_IMX6DL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/aristainetos_defconfig +2 -2

index cc713e29bd..80d22a5f17 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_ARISTAINETOS=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,SOC_IMX6DL"
 CONFIG_BOOTDELAY=3
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/cgtqmx6eval_defconfig +1 -1

index 2ac0bac0b6..04644c3eaf 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/cm_fx6_defconfig +1 -1

index 183ad4282b..79b3529525 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/colibri_imx6_defconfig +2 -2

index b982a5eae8..e908b543f9 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -9,7 +9,7 @@ CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6DL"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SUPPORT_RAW_INITRD=y

configs/colibri_imx6_nospl_defconfig +2 -2

index c5088215e8..2f747c2e97 100644
@@ -1,11 +1,11 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_COLIBRI_IMX6=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,MX6DL,DDR_MB=256"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx6/colibri_imx6.cfg,SOC_IMX6DL,DDR_MB=256"
 CONFIG_BOOTDELAY=1
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SUPPORT_RAW_INITRD=y

configs/dh_imx6_defconfig +1 -1

index 2b4fe9c2c5..838fb7a1fe 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/display5_defconfig +2 -2

index a0d9eaee97..7080849fa1 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx6q-display5"
 CONFIG_FIT=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_SPL=y
 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set

configs/display5_factory_defconfig +2 -2

index 632b32ac61..a0eca39956 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -10,7 +10,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_FIT=y
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run factory"

configs/dms-ba16-1g_defconfig +1 -1

index 40b317093f..ee365989b5 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_ADVANTECH_DMS_BA16=y
 CONFIG_SYS_DDR_1G=y

configs/dms-ba16_defconfig +1 -1

index 3519c5275c..1d2663e6e6 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_ADVANTECH_DMS_BA16=y
 CONFIG_BOOTDELAY=1

configs/ge_b450v3_defconfig +1 -1

index 045380b6de..e6c6f86ce4 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_GE_B450V3=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

configs/ge_b650v3_defconfig +1 -1

index 9d4b8aeebe..720ac2ab1e 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_GE_B650V3=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

configs/ge_b850v3_defconfig +1 -1

index 94785681be..febce1481f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_GE_B850V3=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set

configs/gwventana_emmc_defconfig +1 -1

index a6db1040b6..cf745dd62f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/gwventana_gw5904_defconfig +1 -1

index 41b93c8a07..2633a72473 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/gwventana_nand_defconfig +1 -1

index e513289583..e58aeb459f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6dl_icore_nand_defconfig +1 -1

index d17f9cfed9..282a23d090 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6q_icore_nand_defconfig +1 -1

index 2a86059226..937b5e5236 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6q_logic_defconfig +2 -2

index e6b3264e94..f349554723 100644
@@ -1,10 +1,10 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_MX6LOGICPD=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/logicpd/imx6/mx6q_2x_MT41K512M16HA.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/imx6qdl_icore_mipi_defconfig +1 -1

index 6dc8d2fe13..4d8c07af0b 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6qdl_icore_mmc_defconfig +1 -1

index a3f5e8fc34..4eb68b21de 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6qdl_icore_nand_defconfig +1 -1

index 2a86059226..937b5e5236 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6qdl_icore_rqs_defconfig +1 -1

index 6c8fb85ca2..f5d2067435 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6ul_geam_mmc_defconfig +1 -1

index b6d8680b08..f4d71d28dc 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6ul_geam_nand_defconfig +1 -1

index a8eb08bf5d..9f60e9fb8c 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6ul_isiot_emmc_defconfig +1 -1

index a9bfbfd254..774cf4ebbf 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/imx6ul_isiot_nand_defconfig +1 -1

index ba898e6e16..d5b12e3709 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/liteboard_defconfig +1 -1

index 22872b3ece..98b2e02bef 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/marsboard_defconfig +2 -2

index 76b55df0c2..309b92a50d 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,SOC_IMX6Q,DDR_MB=1024"
 CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/mccmon6_nor_defconfig +1 -1

index da1d502959..38200e7a76 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y

configs/mccmon6_sd_defconfig +1 -1

index cbfd125fb0..defbf82ec7 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y

configs/mx6cuboxi_defconfig +1 -1

index 14f128a96b..4b5b2d5bd8 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6dlarm2_defconfig +2 -2

index 1dc4e975ff..a7c3fa8c79 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_MX6QARM2=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,SOC_IMX6DL,DDR_MB=2048"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/mx6dlarm2_lpddr2_defconfig +2 -2

index 8f07f8feea..b6f2be823b 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_MX6QARM2=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,SOC_IMX6DL,MX6DL_LPDDR2,DDR_MB=512"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/mx6memcal_defconfig +2 -2

index fdcef6b65b..ee5bca2963 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y

@@ -7,7 +7,7 @@ CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_MX6MEMCAL=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SPL,SOC_IMX6QDL"
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_SPL=y
 CONFIG_SPL_USB_HOST_SUPPORT=y

configs/mx6qarm2_defconfig +2 -2

index 925fc16d6c..db2a771b0d 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_MX6QARM2=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,DDR_MB=2048"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,SOC_IMX6Q,DDR_MB=2048"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/mx6qarm2_lpddr2_defconfig +2 -2

index b907cb4225..d61bc73d4f 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_MX6QARM2=y
 # CONFIG_CMD_BMODE is not set
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,SOC_IMX6Q,MX6DQ_LPDDR2,DDR_MB=512"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/mx6qsabrelite_defconfig +2 -2

index 2b45dc17fd..f6f1a60f11 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,SOC_IMX6Q,DDR_MB=1024,SABRELITE"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/mx6sabreauto_defconfig +1 -1

index ee6ca57b00..114830c29f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6sabresd_defconfig +1 -1

index 83b8bed52b..41c8984cad 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6slevk_defconfig +1 -1

index a49e9cd72a..eeb98d63b0 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SLEVK=y
 # CONFIG_CMD_BMODE is not set

configs/mx6slevk_spinor_defconfig +1 -1

index 76fc584055..6d3bb56ab8 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SLEVK=y
 # CONFIG_CMD_BMODE is not set

configs/mx6slevk_spl_defconfig +1 -1

index c021b39ba0..3101c393b3 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6sllevk_defconfig +1 -1

index 39c1cef3ce..f6dad44279 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SLLEVK=y
 # CONFIG_CMD_BMODE is not set

configs/mx6sllevk_plugin_defconfig +1 -1

index 86f5195805..2395dc5971 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SLLEVK=y
 CONFIG_USE_IMXIMG_PLUGIN=y

configs/mx6sxsabreauto_defconfig +1 -1

index 2ea2877b5c..aa1d66ef0c 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SXSABREAUTO=y
 # CONFIG_CMD_BMODE is not set

configs/mx6sxsabresd_defconfig +1 -1

index 2856a7fd8a..e24a69c2dc 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6SXSABRESD=y
 # CONFIG_CMD_BMODE is not set

configs/mx6sxsabresd_spl_defconfig +1 -1

index 146c801404..ea8023d115 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6ul_14x14_evk_defconfig +1 -1

index a9926859b7..78e570fecf 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6ul_9x9_evk_defconfig +1 -1

index a36a872bac..f484710118 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/mx6ull_14x14_evk_defconfig +1 -1

index 375db54a75..711a436145 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk"

configs/mx6ull_14x14_evk_plugin_defconfig +1 -1

index ce2271549e..b37b39cc58 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_MX6ULL_14X14_EVK=y
 CONFIG_USE_IMXIMG_PLUGIN=y

configs/nitrogen6dl2g_defconfig +2 -2

index c109aa3b97..40db9a7127 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,SOC_IMX6DL,DDR_MB=2048"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/nitrogen6dl_defconfig +2 -2

index 462229e159..d060ae3ffe 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,SOC_IMX6DL,DDR_MB=1024"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/nitrogen6q2g_defconfig +2 -2

index 79c8de3d8e..277f3211ea 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,SOC_IMX6Q,DDR_MB=2048"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/nitrogen6q_defconfig +2 -2

index 2895b6e958..70c3a9eb60 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,SOC_IMX6Q,DDR_MB=1024"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/nitrogen6s1g_defconfig +2 -2

index e7348af733..664ab44a04 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SOC_IMX6S,DDR_MB=1024"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/nitrogen6s_defconfig +2 -2

index e9e9f73176..81f97086c7 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_NITROGEN6X=y
 CONFIG_CMD_HDMIDETECT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,SOC_IMX6S,DDR_MB=512"
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
 CONFIG_SUPPORT_RAW_INITRD=y

configs/novena_defconfig +2 -2

index 75cc57b7e1..99055a4b96 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -14,7 +14,7 @@ CONFIG_SPL_FAT_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_USE_BOOTARGS=y
 CONFIG_BOOTARGS="console=ttymxc1,115200 "
 CONFIG_BOOTCOMMAND="run distro_bootcmd ; run net_nfs"

configs/opos6uldev_defconfig +1 -1

index d4c8db23fd..448c6876f2 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y

configs/ot1200_defconfig +2 -2

index e5baed1ada..6851db14d6 100644
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_OT1200=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/bachmann/ot1200/mx6q_4x_mt41j128.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/ot1200_spl_defconfig +2 -2

index 29bbb9d012..52affefbc6 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -9,7 +9,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/pcm058_defconfig +2 -2

index b52499d161..aae4ea6ec5 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -14,7 +14,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_CMD_HDMIDETECT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_BOARD_EARLY_INIT_F=y

configs/pfla02_defconfig +1 -1

index c1ced48d9b..1af404cab1 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/pico-imx6ul_defconfig +1 -1

index c6fa11a9b4..67020dbfb4 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_PICO_IMX6UL=y
 # CONFIG_CMD_BMODE is not set

configs/platinum_picon_defconfig +2 -2

index c466d14db7..6cba40eb62 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -10,7 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6DL"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/platinum_titanium_defconfig +2 -2

index 298261d26a..3866e031da 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -10,7 +10,7 @@ CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_NAND_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y

configs/riotboard_defconfig +2 -2

index dd7df83959..69701359f9 100644
@@ -1,9 +1,9 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_EMBESTMX6BOARDS=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SOC_IMX6S,DDR_MB=1024"
 CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
 # CONFIG_CONSOLE_MUX is not set
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y

configs/secomx6quq7_defconfig +2 -2

index f1136609c3..657a8fb7b0 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_SECOMX6=y
 CONFIG_SECOMX6_UQ7=y

@@ -9,7 +9,7 @@ CONFIG_BOOTDELAY=3
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="SECO MX6Q uQ7 U-Boot > "
+CONFIG_SYS_PROMPT="SECO i.MX6Q uQ7 U-Boot > "
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y

configs/sksimx6_defconfig +2 -2

index c5cb7134f5..c32813cd16 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -14,7 +14,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6QDL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6QDL"
 CONFIG_BOOTDELAY=1
 # CONFIG_USE_BOOTCOMMAND is not set
 CONFIG_SILENT_CONSOLE=y

configs/tbs2910_defconfig +1 -1

index 567f80be84..e52e8ab8d8 100644
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_SYS_THUMB_BUILD=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_TBS2910=y
 CONFIG_CMD_HDMIDETECT=y

configs/titanium_defconfig +1 -1

index 2267039363..360c04d6dd 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_TARGET_TITANIUM=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"

configs/tqma6dl_mba6_mmc_defconfig +1 -1

index 3a6a9f04c6..9ff81c690b 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x4fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6DL=y

configs/tqma6dl_mba6_spi_defconfig +1 -1

index 35f58a2642..9b14458563 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x4fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6DL=y

configs/tqma6q_mba6_mmc_defconfig +1 -1

index 4a4803d969..ea492ba27f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x4fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_FIT=y

configs/tqma6q_mba6_spi_defconfig +1 -1

index a37ab54511..2e5f8dc5d0 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x4fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6X_SPI_BOOT=y

configs/tqma6s_mba6_mmc_defconfig +1 -1

index dec79e044f..e307c8631f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x2fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y

configs/tqma6s_mba6_spi_defconfig +1 -1

index ba257b81d2..cac256b0c4 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x2fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y

configs/tqma6s_wru4_mmc_defconfig +1 -1

index 995a1ced0f..d0600f53b9 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x2fc00000
 CONFIG_TARGET_TQMA6=y
 CONFIG_TQMA6S=y

configs/udoo_defconfig +1 -1

index 0e88f2b470..a88a2f788f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/udoo_neo_defconfig +1 -1

index dff2896749..d3623c2150 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/vining_2000_defconfig +1 -1

index 844809d8e6..b0784b5669 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_SAMTEC_VINING_2000=y
 # CONFIG_CMD_BMODE is not set

configs/wandboard_defconfig +1 -1

index 2c739fae1c..bdd53f747a 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/warp_defconfig +1 -1

index bddf4bcf1d..9996c4363a 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_WARP=y
 # CONFIG_CMD_BMODE is not set

configs/xpress_defconfig +1 -1

index 4a3ddccd3c..05d9e3ee6f 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_TARGET_XPRESS=y
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ccv/xpress/imximage.cfg"

configs/xpress_spl_defconfig +1 -1

index 3425d5325f..478ab27a13 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x87800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

configs/zc5202_defconfig +2 -2

index 82e8fc33a8..ae489ad161 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -12,7 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx6q-zc5202.dtb"

configs/zc5601_defconfig +2 -2

index cd2f5216c9..b643e2abfa 100644
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
-CONFIG_ARCH_MX6=y
+CONFIG_ARCH_IMX6=y
 CONFIG_SYS_TEXT_BASE=0x17800000
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y

@@ -12,7 +12,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DISTRO_DEFAULTS=y
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6Q"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,SOC_IMX6Q"
 CONFIG_BOOTDELAY=3
 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx6q-zc5601.dtb"

doc/README.imx6 +1 -1

index b0644f8491..63a73f1bbf 100644
@@ -14,7 +14,7 @@ SoC.
 
 Example:
 
-For reading the MAC address fuses on a MX6Q:
+For reading the MAC address fuses on a i.MX6Q:
 
 - The MAC address is stored in two fuse addresses (the fuse addresses are
 described in the Fusemap Descriptions table from the mx6q Reference Manual):

doc/README.imximage +2 -2

index 803682f558..9ae88bc337 100644
@@ -3,11 +3,11 @@ Imximage Boot Image generation using mkimage
 ---------------------------------------------
 
 This document describes how to set up a U-Boot image that can be booted
-by Freescale MX25, MX35, MX51, MX53 and MX6 processors via internal boot
+by Freescale MX25, MX35, MX51, MX53 and i.MX6 processors via internal boot
 mode.
 
 These processors can boot directly from NAND, SPI flash and SD card flash
-using its internal boot ROM support. MX6 processors additionally support
+using its internal boot ROM support. i.MX6 processors additionally support
 boot from NOR flash and SATA disks. All processors can boot from an internal
 UART, if booting from device media fails.
 Booting from NOR flash does not require to use this image type.

drivers/ata/dwc_ahsata.c +1 -1

index 480ae115af..2c7714ab53 100644
@@ -885,7 +885,7 @@ int init_sata(int dev)
 {
 	struct ahci_uc_priv *uc_priv = NULL;
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 #endif

drivers/crypto/fsl/jobdesc.c +1 -1

index aadf851101..8ed1b4ea4a 100644
@@ -14,7 +14,7 @@
 #include "jobdesc.h"
 #include "rsa_caam.h"
 
-#if defined(CONFIG_MX6) || defined(CONFIG_MX7)
+#if defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7)
 /*!
  * Secure memory run command
  *

drivers/dma/Kconfig +1 -1

index 4ee6afad35..e904e98cd3 100644
@@ -21,7 +21,7 @@ config TI_EDMA3
 
 config APBH_DMA
 	bool "Support APBH DMA"
-	depends on MX23 || MX28 || MX6 || MX7
+	depends on MX23 || MX28 || SOC_IMX6 || MX7
 	help
 	  Enable APBH DMA driver.
 

drivers/dma/apbh_dma.c +1 -1

index fea8767d7b..6365fb779d 100644
@@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
 #if defined(CONFIG_MX23)
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
 	uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#elif (defined(CONFIG_MX28) || defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 	uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
 	uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif

drivers/gpio/mxc_gpio.c +12 -11

index d0e365a54b..3ad08bf767 100644
@@ -40,19 +40,20 @@ static unsigned long gpio_ports[] = {
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+		defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 	[3] = GPIO4_BASE_ADDR,
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_MX8M)
 	[4] = GPIO5_BASE_ADDR,
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M))
+#if !(defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL) || \
+		defined(CONFIG_MX8M))
 	[5] = GPIO6_BASE_ADDR,
 #endif
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7)
-#if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL))
+#if defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7)
+#if !(defined(CONFIG_SOC_IMX6UL) || defined(CONFIG_SOC_IMX6ULL))
 	[6] = GPIO7_BASE_ADDR,
 #endif
 #endif

@@ -349,18 +350,18 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+		defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX8M)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX8M)
 	{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
 #ifndef CONFIG_MX8M
 	{ 5, (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6)
 	{ 6, (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
 };

@@ -370,18 +371,18 @@ U_BOOT_DEVICES(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[1] },
 	{ "gpio_mxc", &mxc_plat[2] },
 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+		defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX8M)
 	{ "gpio_mxc", &mxc_plat[3] },
 #endif
-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6) || \
 		defined(CONFIG_MX8M)
 	{ "gpio_mxc", &mxc_plat[4] },
 #ifndef CONFIG_MX8M
 	{ "gpio_mxc", &mxc_plat[5] },
 #endif
 #endif
-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6)
 	{ "gpio_mxc", &mxc_plat[6] },
 #endif
 };

drivers/i2c/Kconfig +1 -1

index 3299ef0fea..cd3ba8c7a4 100644
@@ -150,7 +150,7 @@ config SYS_I2C_MESON
 
 config SYS_I2C_MXC
 	bool "NXP i.MX I2C driver"
-	depends on MX6
+	depends on SOC_IMX6
 	help
 	  Add support for the NXP i.MX I2C driver. This supports upto for bus
 	  channels and operating on standard mode upto 100 kbits/s and fast

drivers/misc/mxc_ocotp.c +4 -4

index 8662e82cfa..667e82bb21 100644
@@ -66,11 +66,11 @@
 
 #define WRITE_POSTAMBLE_US		2
 
-#if defined(CONFIG_MX6) || defined(CONFIG_VF610)
+#if defined(CONFIG_SOC_IMX6) || defined(CONFIG_VF610)
 #define FUSE_BANK_SIZE	0x80
-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_IMX6SL
 #define FUSE_BANKS	8
-#elif defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL)
+#elif defined(CONFIG_SOC_IMX6ULL) || defined(CONFIG_SOC_IMX6SLL)
 #define FUSE_BANKS	9
 #else
 #define FUSE_BANKS	16

@@ -88,7 +88,7 @@
 #error "Unsupported architecture\n"
 #endif
 
-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_IMX6)
 
 /*
  * There is a hole in shadow registers address map of size 0x100

drivers/mmc/Kconfig +3 -3

index 5f67e336db..d92759bd26 100644
@@ -210,10 +210,10 @@ config MMC_MXC
 
 config MMC_MXS
 	bool "Freescale MXS Multimedia Card Interface support"
-	depends on MX23 || MX28 || MX6 || MX7
+	depends on MX23 || MX28 || SOC_IMX6 || MX7
 	select APBH_DMA
-	select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
-	select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
+	select APBH_DMA_BURST if ARCH_IMX6 || ARCH_MX7
+	select APBH_DMA_BURST8 if ARCH_IMX6 || ARCH_MX7
 	help
 	  This selects the Freescale SSP MMC controller found on MXS based
 	  platforms like mx23/28.

drivers/mtd/nand/Kconfig +3 -3

index a820af61ce..19edb98f29 100644
@@ -140,11 +140,11 @@ config NAND_MXC
 
 config NAND_MXS
 	bool "MXS NAND support"
-	depends on MX23 || MX28 || MX6 || MX7
+	depends on MX23 || MX28 || SOC_IMX6 || MX7
 	imply CMD_NAND
 	select APBH_DMA
-	select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
-	select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
+	select APBH_DMA_BURST if ARCH_IMX6 || ARCH_MX7
+	select APBH_DMA_BURST8 if ARCH_IMX6 || ARCH_MX7
 	help
 	  This enables NAND driver for the NAND flash controller on the
 	  MXS processors.

drivers/mtd/nand/mxs_nand.c +1 -1

index bed9b65ef4..20cd2f4056 100644
@@ -30,7 +30,7 @@
 #define	MXS_NAND_DMA_DESCRIPTOR_COUNT		4
 
 #define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE		512
-#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
+#if (defined(CONFIG_SOC_IMX6) || defined(CONFIG_MX7))
 #define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	2
 #else
 #define	MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT	0

drivers/net/Kconfig +1 -1

index de1947ccc1..7c6e0a5cb3 100644
@@ -149,7 +149,7 @@ config ETHOC
 
 config FEC_MXC
 	bool "FEC Ethernet controller"
-	depends on MX5 || MX6
+	depends on MX5 || SOC_IMX6
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.

drivers/net/fec_mxc.c +1 -1

index ff7ad91116..8ab656d388 100644
@@ -454,7 +454,7 @@ static int fec_open(struct eth_device *edev)
 	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
 	       &fec->eth->ecntrl);
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6SL)
 	udelay(100);
 
 	/* setup the MII gasket for RMII mode */

drivers/net/fec_mxc.h +2 -2

index 43a7d7bed8..d0ef86d46d 100644
@@ -127,7 +127,7 @@ struct ethernet_regs {
 
 	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_SOC_IMX6SL)
 	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
 	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
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drivers/pci/pcie_imx.c +7 -7

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drivers/pinctrl/nxp/Kconfig +1 -1

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drivers/pwm/pwm-imx-util.c +2 -2

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drivers/serial/Kconfig +1 -1

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drivers/spi/fsl_qspi.c +9 -9

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drivers/thermal/imx_thermal.c +1 -1

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drivers/usb/host/Kconfig +2 -2

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drivers/usb/host/ehci-mx6.c +4 -4

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drivers/video/Kconfig +1 -1

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drivers/video/ipu_regs.h +1 -1

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env/Kconfig +1 -1

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include/configs/cgtqmx6eval.h +2 -2

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include/configs/cm_fx6.h +1 -1

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include/configs/ge_bx50v3.h +1 -1

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include/configs/imx6-engicam.h +2 -2

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include/configs/imx6_spl.h +2 -2

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include/configs/mx6_common.h +6 -6

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include/configs/mx6cuboxi.h +6 -6

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include/configs/mx6memcal.h +1 -1

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include/configs/mx6sabre_common.h +6 -6

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include/configs/titanium.h +1 -1

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include/configs/wandboard.h +7 -7

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include/fsl_sec.h +4 -4

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