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timer: Add High Precision Event Timers (HPET) support

PATCH New Ivan Gorinov 4 participants 6 messages Mar 29, 2018 – Mar 31, 2018 x86

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Ivan Gorinov

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#0 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

Adding HPET as an alternative timer for x86 (default is TSC). HPET main counter has constant clock frequency, calibration is not required. This change also makes TSC timer driver optional on x86 platforms. If X86_TSC is disabled, early timer functions are provided by HPET.

HPET can be selected as the tick timer in the Device Tree "chosen" node:

/include/ "hpet.dtsi"

  chosen {
    tick-timer = "/hpet0";
  };
Signed-off-by Ivan Gorinov <[email protected]>
---
 arch/Kconfig               |   2 +-
 arch/x86/dts/hpet.dtsi     |   7 ++
 drivers/timer/Kconfig      |   6 ++
 drivers/timer/Makefile     |   1 +
 drivers/timer/hpet_timer.c | 197 +++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 212 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/dts/hpet.dtsi
 create mode 100644 drivers/timer/hpet_timer.c
arch/Kconfig +1 -1
index e599e7a..37dabae 100644
@@ -104,7 +104,7 @@ config X86
 	select DM_PCI
 	select PCI
 	select TIMER
-	select X86_TSC_TIMER
+	imply X86_TSC_TIMER
 	imply BLK
 	imply DM_ETH
 	imply DM_GPIO
arch/x86/dts/hpet.dtsi new file +7 -0
new file mode 100644
index 0000000..037dc7e
@@ -0,0 +1,7 @@
+/ {
+	hpet0: hpet at fed00000 {
+		compatible = "hpet-x86";
+		u-boot,dm-pre-reloc;
+		reg = <0xfed00000 0x1000>;
+	};
+};
drivers/timer/Kconfig +6 -0
index 2c96896..72ae6c5 100644
@@ -65,6 +65,12 @@ config X86_TSC_TIMER
 	help
 	  Select this to enable Time-Stamp Counter (TSC) timer for x86.
 
+config HPET_TIMER
+	bool "High Precision Event Timers (HPET) support"
+	depends on TIMER && X86
+	help
+	  Select this to enable High Precision Event Timers (HPET) for x86.
+
 config OMAP_TIMER
 	bool "Omap timer support"
 	depends on TIMER
drivers/timer/Makefile +1 -0
index a6e7832..557fecc 100644
@@ -8,6 +8,7 @@ obj-y += timer-uclass.o
 obj-$(CONFIG_ALTERA_TIMER)	+= altera_timer.o
 obj-$(CONFIG_SANDBOX_TIMER)	+= sandbox_timer.o
 obj-$(CONFIG_X86_TSC_TIMER)	+= tsc_timer.o
+obj-$(CONFIG_HPET_TIMER)	+= hpet_timer.o
 obj-$(CONFIG_OMAP_TIMER)	+= omap-timer.o
 obj-$(CONFIG_AST_TIMER)	+= ast_timer.o
 obj-$(CONFIG_STI_TIMER)		+= sti-timer.o
drivers/timer/hpet_timer.c new file +197 -0

197 lines not on this page · raw message

Signature · 1 line
2.7.4
#1 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

Quoted 6 lines · Ivan Gorinov

Adding HPET as an alternative timer for x86 (default is TSC). HPET main counter has constant clock frequency, calibration is not required.
This change also makes TSC timer driver optional on x86 platforms. If X86_TSC is disabled, early timer functions are provided by HPET.

Quoted 9 lines

HPET can be selected as the tick timer in the Device Tree "chosen" node:

/include/ "hpet.dtsi"

  chosen {
    tick-timer = "/hpet0";
  };

First question is how this will work in case of Broadwell and Ivybridge that have something to do with HPET in their CPU code, i.e.

arch/x86/cpu/broadwell/pch.c
arch/x86/cpu/ivybridge/lpc.c

?

Look for

    clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);

drivers/timer/hpet_timer.c line 86

Quoted 7 lines
drivers/timer/hpet_timer.c new file +4 -0
+static int hpet_timer_get_count(struct udevice *dev, u64 *count)
 
+static int hpet_timer_probe(struct udevice *dev)
 
+#ifndef CONFIG_X86_TSC_TIMER
 
+#define EARLY_HPET_BASE 0xfed00000

HPET address is fixed, AFAIU, on x86, and provided by config option in U-Boot.

drivers/timer/hpet_timer.c line 126

Quoted 5 lines
drivers/timer/hpet_timer.c new file +3 -0
+unsigned long notrace timer_early_get_rate(void)
 
+u64 notrace timer_early_get_count(void)
 
+int timer_init(void)

These functions have too much code duplication with above.

Quoted 1 line

+#endif

Signature · 2 lines
Andy Shevchenko <[email protected]>
Intel Finland Oy
author
#2 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

Quoted 16 lines · Andy Shevchenko
Quoted 6 lines · Ivan Gorinov

Adding HPET as an alternative timer for x86 (default is TSC). HPET main counter has constant clock frequency, calibration is not required.
This change also makes TSC timer driver optional on x86 platforms. If X86_TSC is disabled, early timer functions are provided by HPET.

Quoted 8 lines

HPET can be selected as the tick timer in the Device Tree "chosen" node:

/include/ "hpet.dtsi"

  chosen {
    tick-timer = "/hpet0";
  };
Quoted 5 lines

First question is how this will work in case of Broadwell and Ivybridge that have something to do with HPET in their CPU code, i.e.

arch/x86/cpu/broadwell/pch.c
arch/x86/cpu/ivybridge/lpc.c

The platform-specific code maps HPET registers to make sure they are available to the timer driver added by this patch.

Apparently, HPET is also used by the DRAM initialization code (MRC) on Ivy Bridge, before the U-Boot timer driver starts.

Quoted 6 lines

Look for

    clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);
Quoted 1 line

+static int hpet_timer_get_count(struct udevice *dev, u64 *count)

Quoted 8 lines

drivers/timer/hpet_timer.c line 86

Quoted 5 lines
drivers/timer/hpet_timer.c new file +3 -0
+static int hpet_timer_probe(struct udevice *dev)
 
+#ifndef CONFIG_X86_TSC_TIMER
 
+#define EARLY_HPET_BASE 0xfed00000

HPET address is fixed, AFAIU, on x86, and provided by config option in U-Boot.

Found it. Thank you!

Quoted 4 lines

drivers/timer/hpet_timer.c line 126

Quoted 3 lines
drivers/timer/hpet_timer.c new file +3 -0
+unsigned long notrace timer_early_get_rate(void)
+u64 notrace timer_early_get_count(void)
+int timer_init(void)

These functions have too much code duplication with above.

I will move the duplicated code into static functions.

#3 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

In reply to Andy Shevchenko

Hi,

Quoted 41 lines · Andy Shevchenko
Quoted 6 lines · Ivan Gorinov

Adding HPET as an alternative timer for x86 (default is TSC). HPET main counter has constant clock frequency, calibration is not required.
This change also makes TSC timer driver optional on x86 platforms. If X86_TSC is disabled, early timer functions are provided by HPET.

Quoted 9 lines

HPET can be selected as the tick timer in the Device Tree "chosen" node:

/include/ "hpet.dtsi"

  chosen {
    tick-timer = "/hpet0";
  };

First question is how this will work in case of Broadwell and Ivybridge that have something to do with HPET in their CPU code, i.e.

arch/x86/cpu/broadwell/pch.c
arch/x86/cpu/ivybridge/lpc.c

?

Look for

    clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);

drivers/timer/hpet_timer.c line 86

Quoted 7 lines
drivers/timer/hpet_timer.c new file +4 -0
+static int hpet_timer_get_count(struct udevice *dev, u64 *count)
 
+static int hpet_timer_probe(struct udevice *dev)
 
+#ifndef CONFIG_X86_TSC_TIMER
 
+#define EARLY_HPET_BASE 0xfed00000

HPET address is fixed, AFAIU, on x86, and provided by config option in U-Boot.

Quoted 7 lines

drivers/timer/hpet_timer.c line 126

Quoted 5 lines
drivers/timer/hpet_timer.c new file +3 -0
+unsigned long notrace timer_early_get_rate(void)
 
+u64 notrace timer_early_get_count(void)
 
+int timer_init(void)

These functions have too much code duplication with above.

Perhaps that code can be removed in favour of this driver? I am happy to test on these platforms if it helps.

Regards,
Simon

#4 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

Quoted 12 lines · Simon Glass
Quoted 10 lines · Andy Shevchenko

On Wed, 2018-03-28 at 17:58 -0700, Ivan Gorinov wrote:

First question is how this will work in case of Broadwell and Ivybridge that have something to do with HPET in their CPU code, i.e.

arch/x86/cpu/broadwell/pch.c
arch/x86/cpu/ivybridge/lpc.c

?

Quoted 7 lines
Quoted 3 lines

Look for

    clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);

Perhaps that code can be removed in favour of this driver? I am happy to test on these platforms if it helps.

That's my point.

Signature · 2 lines
With Best Regards,
Andy Shevchenko
author
#5 lore raw

PATCH 1/1 timer: Add High Precision Event Timers (HPET) support

Quoted 14 lines · Andy Shevchenko
Quoted 13 lines · Simon Glass
Quoted 10 lines · Andy Shevchenko

First question is how this will work in case of Broadwell and Ivybridge that have something to do with HPET in their CPU code, i.e.

arch/x86/cpu/broadwell/pch.c
arch/x86/cpu/ivybridge/lpc.c

?

Look for

Quoted 8 lines
Quoted 5 lines
Quoted 1 line
    clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7);

Perhaps that code can be removed in favour of this driver? I am happy to test on these platforms if it helps.

That's my point.

This code performs platform-specific enabling and may be required for the generic HPET driver and OS kernel to work.