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net: phy: mv88e61xx: Force CPU port link up

PATCH In review Chris Packham 3 participants 7 messages Jun 3, 2018 – Jun 13, 2018

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Network drivers Ethernet PHY
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Chris Packham

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#0 lore raw

PATCH 1/2 net: phy: mv88e61xx: Force CPU port link up

When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link.

Cc Kevin Smith <[email protected]>
Signed-off-by Chris Packham <[email protected]>

---

 drivers/net/phy/mv88e61xx.c | 51 ++++++++++++++++++++++---------------
 1 file changed, 30 insertions(+), 21 deletions(-)
drivers/net/phy/mv88e61xx.c +30 -21
index 17040bd6ccdd..ea54a1531053 100644
@@ -705,6 +705,31 @@ unforce:
 	return res;
 }
 
+static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
+{
+	int val;
+
+	val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
+	if (val < 0)
+		return val;
+
+	val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
+		 PORT_REG_PHYS_CTRL_FC_VALUE);
+	val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
+	       PORT_REG_PHYS_CTRL_PCS_AN_RST |
+	       PORT_REG_PHYS_CTRL_FC_FORCE |
+	       PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
+	       PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
+	       PORT_REG_PHYS_CTRL_SPD1000;
+
+	if (port == CONFIG_MV88E61XX_CPU_PORT)
+		val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
+		       PORT_REG_PHYS_CTRL_LINK_FORCE;
+
+	return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
+				   val);
+}
+
 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
 {
 	int val;

@@ -748,6 +773,11 @@ static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
 			if (val < 0)
 				return val;
 		}
+	} else {
+		val = mv88e61xx_fixed_port_setup(phydev,
+						 CONFIG_MV88E61XX_CPU_PORT);
+		if (val < 0)
+			return val;
 	}
 
 	return 0;

@@ -810,27 +840,6 @@ static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
 	return 0;
 }
 
-static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
-{
-	int val;
-
-	val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
-	if (val < 0)
-		return val;
-
-	val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
-		 PORT_REG_PHYS_CTRL_FC_VALUE);
-	val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
-	       PORT_REG_PHYS_CTRL_PCS_AN_RST |
-	       PORT_REG_PHYS_CTRL_FC_FORCE |
-	       PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
-	       PORT_REG_PHYS_CTRL_DUPLEX_FORCE |
-	       PORT_REG_PHYS_CTRL_SPD1000;
-
-	return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
-				   val);
-}
-
 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
 {
 	int val;
Signature · 1 line
2.17.0
author
#1 lore raw

PATCH 2/2 ARM: kirkwood: SBx81LIFKW: Enable network hardware

The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.

For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.

Signed-off-by Chris Packham <[email protected]>

---

 board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 14 ++++++++++++--
 configs/SBx81LIFKW_defconfig                |  6 ++++++
 include/configs/SBx81LIFKW.h                |  5 -----
 3 files changed, 18 insertions(+), 7 deletions(-)
board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c +12 -2
index 3cacdc837234..e58bbf07ef15 100644
@@ -164,9 +164,15 @@ int board_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_MV88E61XX_SWITCH
-/* Configure and enable Switch and PHY */
+#ifdef CONFIG_RESET_PHY_R
+/* automatically defined by kirkwood config.h */
 void reset_phy(void)
+{
+}
+#endif
+
+#ifdef CONFIG_MV88E61XX_SWITCH
+int mv88e61xx_hw_reset(struct phy_device *phydev)
 {
 	/* Ensure the 88e6097 gets at least 10ms Reset
 	 */

@@ -174,6 +180,10 @@ void reset_phy(void)
 	mdelay(20);
 	kw_gpio_set_value(MV88E6097_RESET, 1);
 	mdelay(20);
+
+	phydev->advertising = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
+
+	return 0;
 }
 #endif
configs/SBx81LIFKW_defconfig +6 -0
index ec9df1ac691c..348f861a143b 100644
@@ -14,6 +14,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_DHCP=y
 CONFIG_BOOTP_NTPSERVER=y
+CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_OF_CONTROL=y

@@ -29,5 +30,10 @@ CONFIG_I2C_MUX_PCA954x=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHYLIB=y
+CONFIG_MV88E61XX_SWITCH=y
+CONFIG_MV88E61XX_CPU_PORT=10
+CONFIG_MV88E61XX_PHY_PORTS=0x003
+CONFIG_MV88E61XX_FIXED_PORTS=0x300
 CONFIG_SPI=y
 CONFIG_KIRKWOOD_SPI=y
include/configs/SBx81LIFKW.h +0 -5
index 756eaa47fa92..bcc2c201d222 100644
@@ -103,15 +103,10 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define CONFIG_MII		/* expose smi over miiphy interface */
-#define CONFIG_PHYLIB
 #define CONFIG_MVGBE	/* Enable kirkwood Gbe Controller Driver */
 #define CONFIG_MVGBE_PORTS	{1, 0}	/* enable a single port */
 #define CONFIG_PHY_BASE_ADR	0x01
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
-#define CONFIG_RESET_PHY_R	/* use reset_phy() to init switch */
-#define CONFIG_MV88E61XX_SWITCH	/* Enable MV88E61XX switch driver */
-#define CONFIG_MV88E61XX_PHY_PORTS 0x303 /* Pt0,1,8,9 */
-#define CONFIG_MV88E61XX_CPU_PORT 10 /* 10(CPU) */
 #endif /* CONFIG_CMD_NET */
 
 /*
Signature · 1 line
2.17.0
#2 lore raw

PATCH 2/2 ARM: kirkwood: SBx81LIFKW: Enable network hardware

Quoted 9 lines · Chris Packham

The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.

For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.

Quoted 7 lines
Signed-off-by Chris Packham <[email protected]>

---

  board/alliedtelesis/SBx81LIFKW/sbx81lifkw.c | 14 ++++++++++++--
  configs/SBx81LIFKW_defconfig                |  6 ++++++
  include/configs/SBx81LIFKW.h                |  5 -----
  3 files changed, 18 insertions(+), 7 deletions(-)
Reviewed-by Stefan Roese <[email protected]>

Thanks,
Stefan

#3 lore raw

PATCH 2/2 ARM: kirkwood: SBx81LIFKW: Enable network hardware

In reply to Chris Packham
Quoted 10 lines · Chris Packham

The SBx81LIFKW boards connect to the internal chassis management network via a Marvell 88e6097 L2 switch. The chassis connections are direct serdes on ports 8 and 9 with a RGMII interface on port 10 connected to the CPU MAC.

For debugging purposes ports 0 and 1 are also taken out to headers on the board. Because the debug interfaces are sometimes connected to with straight ribbon cables we need to run them at 10Mbps.

Signed-off-by Chris Packham <[email protected]>

Applied to u-boot-marvell/master.

Thanks,
Stefan

#5 lore raw

PATCH 1/2 net: phy: mv88e61xx: Force CPU port link up

Quoted 9 lines · Joe Hershberger
Quoted 6 lines · Chris Packham

When connecting to from a CPU direct to a 88e6097 typically RGMII is used. In order for traffic to actually pass we need to force the link up so the CPU MAC on the other end will see the link.

Cc Kevin Smith <[email protected]>
Signed-off-by Chris Packham <[email protected]>
Signed-off-by Joe Hershberger <[email protected]>

Make that,

Acked-by Joe Hershberger <[email protected]>