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sunxi: clock: Fix EHCI and OHCI clocks on A64

PATCH Superseded Vasily Khoruzhick 5 participants 13 messages Jun 6, 2018 – Jun 8, 2018

Subsystems (4)
Arm (32-bit) USB Arm/Allwinner sunXi SoC support USB ohci driver

v1 of 3 Superseded Latest is v3 →

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Vasily Khoruzhick

author
#0 lore raw

PATCH 1/2 sunxi: clock: Fix EHCI and OHCI clocks on A64

EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29

Fixed commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +4 -2
index 8acf79fbba..8afeaf872e 100644
@@ -280,8 +280,10 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	26
 #define AHB_GATE_OFFSET_USB_EHCI0	24
 #elif defined(CONFIG_MACH_SUN50I)
-#define AHB_GATE_OFFSET_USB_OHCI0	29
-#define AHB_GATE_OFFSET_USB_EHCI0	25
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#define AHB_GATE_OFFSET_USB_EHCI1	25
 #else
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +6 -1
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
+	int extra_usb_gate_mask = 0;
 	int phys, ret;
 
 	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#endif
 	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	priv->usb_gate_mask <<= phys;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	setbits_le32(&priv->ccm->usb_clk_cfg,
+		     priv->usb_gate_mask | extra_usb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
Signature · 1 line
2.17.1
#2 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 28 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +3 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
+	int extra_usb_gate_mask = 0;
 	int phys, ret;
 
 	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

drivers/usb/host/ohci-sunxi.c no_phy: · line 92

Quoted 10 lines
drivers/usb/host/ohci-sunxi.c +3 -1
+#endif
 	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	priv->usb_gate_mask <<= phys;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	setbits_le32(&priv->ccm->usb_clk_cfg,
+		     priv->usb_gate_mask | extra_usb_gate_mask);

Why is the SoC / compatible information not coming from DT instead ? Why is the driver polluted by more ifdefs ?

Quoted 4 lines
drivers/usb/host/ohci-sunxi.c +0 -0
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
Signature · 2 lines
Best regards,
Marek Vasut
author
#3 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 34 lines · Marek Vasut
Quoted 33 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +4 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
      struct ohci_sunxi_priv *priv = dev_get_priv(dev);
      struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
      int extra_ahb_gate_mask = 0;
+     int extra_usb_gate_mask = 0;
      int phys, ret;
 
      priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
      extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
      priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#endif
      priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
      extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
      priv->usb_gate_mask <<= phys;
Quoted 8 lines

drivers/usb/host/ohci-sunxi.c no_phy: · line 92

Quoted 5 lines
drivers/usb/host/ohci-sunxi.c +2 -1
      setbits_le32(&priv->ccm->ahb_gate0,
                   priv->ahb_gate_mask | extra_ahb_gate_mask);
-     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+     setbits_le32(&priv->ccm->usb_clk_cfg,
+                  priv->usb_gate_mask | extra_usb_gate_mask);

Why is the SoC / compatible information not coming from DT instead ? Why is the driver polluted by more ifdefs ?

Because this platform doesn't have DM clock driver yet. This code will be removed once this driver is implemented.

Quoted 9 lines

drivers/usb/host/ohci-sunxi.c no_phy: · line 95

Quoted 4 lines
drivers/usb/host/ohci-sunxi.c +0 -0
 #ifdef CONFIG_SUNXI_GEN_SUN6I
      setbits_le32(&priv->ccm->ahb_reset0_cfg,
                   priv->ahb_gate_mask | extra_ahb_gate_mask);

--
Best regards,
Marek Vasut

#4 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 44 lines · Vasily Khoruzhick
Quoted 34 lines · Marek Vasut
Quoted 33 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +4 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
      struct ohci_sunxi_priv *priv = dev_get_priv(dev);
      struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
      int extra_ahb_gate_mask = 0;
+     int extra_usb_gate_mask = 0;
      int phys, ret;
 
      priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
      extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
      priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#endif
      priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
      extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
      priv->usb_gate_mask <<= phys;
Quoted 8 lines

drivers/usb/host/ohci-sunxi.c no_phy: · line 92

Quoted 5 lines
drivers/usb/host/ohci-sunxi.c +2 -1
      setbits_le32(&priv->ccm->ahb_gate0,
                   priv->ahb_gate_mask | extra_ahb_gate_mask);
-     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+     setbits_le32(&priv->ccm->usb_clk_cfg,
+                  priv->usb_gate_mask | extra_usb_gate_mask);

Why is the SoC / compatible information not coming from DT instead ? Why is the driver polluted by more ifdefs ?

Quoted 2 lines

Because this platform doesn't have DM clock driver yet. This code will be removed once this driver is implemented.

You don't need DM clock driver, you can check the compatible string I think ?

Signature · 2 lines
Best regards,
Marek Vasut
#5 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 45 lines · Marek Vasut
Quoted 44 lines · Vasily Khoruzhick
Quoted 42 lines · Marek Vasut
Quoted 28 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +3 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
      struct ohci_sunxi_priv *priv = dev_get_priv(dev);
      struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
      int extra_ahb_gate_mask = 0;
+     int extra_usb_gate_mask = 0;
      int phys, ret;
 
      priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
      extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
      priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+     extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

drivers/usb/host/ohci-sunxi.c no_phy: · line 92

Quoted 10 lines
drivers/usb/host/ohci-sunxi.c +3 -1
+#endif
      priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
      extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;
      priv->usb_gate_mask <<= phys;
 
      setbits_le32(&priv->ccm->ahb_gate0,
                   priv->ahb_gate_mask | extra_ahb_gate_mask);
-     setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+     setbits_le32(&priv->ccm->usb_clk_cfg,
+                  priv->usb_gate_mask | extra_usb_gate_mask);

Why is the SoC / compatible information not coming from DT instead ? Why is the driver polluted by more ifdefs ?

Quoted 5 lines
Quoted 2 lines

Because this platform doesn't have DM clock driver yet. This code will be removed once this driver is implemented.

You don't need DM clock driver, you can check the compatible string I think ?

Yes or driver_data, if we wanted to get rid of other #Ifdef on the file

author
#6 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 10 lines · Jagan Teki
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines

Why is the SoC / compatible information not coming from DT instead ? Why is the driver polluted by more ifdefs ?

Because this platform doesn't have DM clock driver yet. This code will be removed once this driver is implemented.

You don't need DM clock driver, you can check the compatible string I think ?

Yes or driver_data, if we wanted to get rid of other #Ifdef on the file

OK, I'll change it to use driver_data.

#7 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

In reply to Vasily Khoruzhick
Quoted 23 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +1 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
        struct ohci_sunxi_priv *priv = dev_get_priv(dev);
        struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
        int extra_ahb_gate_mask = 0;
+       int extra_usb_gate_mask = 0;
        int phys, ret;
 
        priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

drivers/usb/host/ohci-sunxi.c no_phy: · line 83

Quoted 5 lines
drivers/usb/host/ohci-sunxi.c +2 -0
@@ -78,13 +79,17 @@ no_phy:
        extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
        priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

This look reassigning same clock to twice?

author
#8 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 22 lines · Jagan Teki
Quoted 21 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +1 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
        struct ohci_sunxi_priv *priv = dev_get_priv(dev);
        struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
        int extra_ahb_gate_mask = 0;
+       int extra_usb_gate_mask = 0;
        int phys, ret;
Quoted 9 lines

drivers/usb/host/ohci-sunxi.c no_phy: · line 83

Quoted 7 lines
drivers/usb/host/ohci-sunxi.c +2 -0
        priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
        extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
        priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

This look reassigning same clock to twice?

extra_usb_gate_mask isn't shifted later and thus CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for phy 1 on A64.

#9 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 33 lines · Vasily Khoruzhick
Quoted 22 lines · Jagan Teki
Quoted 21 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
drivers/usb/host/ohci-sunxi.c +1 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
        struct ohci_sunxi_priv *priv = dev_get_priv(dev);
        struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
        int extra_ahb_gate_mask = 0;
+       int extra_usb_gate_mask = 0;
        int phys, ret;
Quoted 9 lines

drivers/usb/host/ohci-sunxi.c no_phy: · line 83

Quoted 7 lines
drivers/usb/host/ohci-sunxi.c +2 -0
        priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
        extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
        priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+       extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;

This look reassigning same clock to twice?

Quoted 3 lines

extra_usb_gate_mask isn't shifted later and thus CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for phy 1 on A64.

Where are you checking phy 1? and you still using
CCM_USB_CTRL_OHCI0_CLK not OHCI1_CLK

author
#10 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

Quoted 8 lines · Jagan Teki
Quoted 3 lines · Vasily Khoruzhick

extra_usb_gate_mask isn't shifted later and thus CCM_USB_CTRL_OHCI0_CLK and CCM_USB_CTRL_OHCI1_CLK will be enabled for phy 1 on A64.

Where are you checking phy 1? and you still using
CCM_USB_CTRL_OHCI0_CLK not OHCI1_CLK

phys is PHY index, usb_gate_mask is shifted to PHY index later - thus it'll be CCM_USB_CTRL_OHCI1_CLK,
extra_usb_gate_mask is not - it'll remain CCM_USB_CTRL_OHCI0_CLK.

Since A64 has only 2 USB controllers that covers it.

#11 lore raw

PATCH 2/2 usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use

In reply to Vasily Khoruzhick
Quoted 9 lines · Vasily Khoruzhick

On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0 clock when OHCI1 is in use.

Fixes commit dd3228170ad7 ("usb: sunxi: Switch to use generic-phy")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 drivers/usb/host/ohci-sunxi.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

Tested loading kernel+initrd+dtb on pine64+

Tested-by Vagrant Cascadian <[email protected]>

live well,
vagrant

Quoted 21 lines
drivers/usb/host/ohci-sunxi.c +4 -0
index ce2b47a5c4..5661557a3d 100644
@@ -36,6 +36,7 @@ static int ohci_usb_probe(struct udevice *dev)
 	struct ohci_sunxi_priv *priv = dev_get_priv(dev);
 	struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev);
 	int extra_ahb_gate_mask = 0;
+	int extra_usb_gate_mask = 0;
 	int phys, ret;
 
 	priv->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

@@ -78,13 +79,17 @@ no_phy:
 	extra_ahb_gate_mask = 1 << AHB_GATE_OFFSET_USB_EHCI0;
 #endif
 	priv->usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#ifdef CONFIG_MACH_SUN50I
+	extra_usb_gate_mask = CCM_USB_CTRL_OHCI0_CLK;
+#endif
 	priv->ahb_gate_mask <<= phys * AHB_CLK_DIST;
 	extra_ahb_gate_mask <<= phys * AHB_CLK_DIST;

drivers/usb/host/ohci-sunxi.c no_phy: · line 95

Quoted 10 lines
drivers/usb/host/ohci-sunxi.c +2 -1
 	priv->usb_gate_mask <<= phys;
 
 	setbits_le32(&priv->ccm->ahb_gate0,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);
-	setbits_le32(&priv->ccm->usb_clk_cfg, priv->usb_gate_mask);
+	setbits_le32(&priv->ccm->usb_clk_cfg,
+		     priv->usb_gate_mask | extra_usb_gate_mask);
 #ifdef CONFIG_SUNXI_GEN_SUN6I
 	setbits_le32(&priv->ccm->ahb_reset0_cfg,
 		     priv->ahb_gate_mask | extra_ahb_gate_mask);

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#12 lore raw

PATCH 1/2 sunxi: clock: Fix EHCI and OHCI clocks on A64

In reply to Vasily Khoruzhick
Quoted 8 lines · Vasily Khoruzhick

EHCI0 is bit 24, EHCI1 - 25, OHCI0 - 28, OHCI1 - 29

Fixed commit fef73766d9ad ("sunxi: clock: Fix OHCI clock gating for H3/H5")

Signed-off-by Vasily Khoruzhick <[email protected]>
---
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Tested loading kernel+initrd+dtb on pine64+

Tested-by Vagrant Cascadian <[email protected]>

live well,
vagrant

Quoted 7 lines
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +0 -0
index 8acf79fbba..8afeaf872e 100644
@@ -280,8 +280,10 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_USB_EHCI1	26
 #define AHB_GATE_OFFSET_USB_EHCI0	24

arch/arm/include/asm/arch-sunxi/clock_sun6i.h struct sunxi_ccm_reg { · line 289

Quoted 10 lines
arch/arm/include/asm/arch-sunxi/clock_sun6i.h +4 -2
 #elif defined(CONFIG_MACH_SUN50I)
-#define AHB_GATE_OFFSET_USB_OHCI0	29
-#define AHB_GATE_OFFSET_USB_EHCI0	25
+#define AHB_GATE_OFFSET_USB_OHCI0	28
+#define AHB_GATE_OFFSET_USB_OHCI1	29
+#define AHB_GATE_OFFSET_USB_EHCI0	24
+#define AHB_GATE_OFFSET_USB_EHCI1	25
 #else
 #define AHB_GATE_OFFSET_USB_OHCI1	30
 #define AHB_GATE_OFFSET_USB_OHCI0	29

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