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target/openrisc: Fix writes to interrupt mask register

PATCH In review Stafford Horne 2 participants 2 messages Jul 1, 2018

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Stafford Horne

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#0 lore raw

PATCH 1/1 target/openrisc: Fix writes to interrupt mask register

The interrupt controller mask register (PICMR) allows writing any value to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR meaning it was not possible to ever mask a interrupt once it was enabled.

I have tested this by running linux 4.18 and my regular checks, I don't see any issues.

Reported-by Davidson Francis <[email protected]>
Signed-off-by Stafford Horne <[email protected]>
---
 target/openrisc/sys_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
target/openrisc/sys_helper.c +1 -1
index 541615bfb3..b66a45c1e0 100644
@@ -142,7 +142,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
         }
         break;
     case TO_SPR(9, 0):  /* PICMR */
-        env->picmr |= rb;
+        env->picmr = rb;
         break;
     case TO_SPR(9, 2):  /* PICSR */
         env->picsr &= ~rb;
Signature · 1 line
2.17.0
Reviewed-by on v1 1/1
#1 lore raw
Quoted 8 lines · Stafford Horne

The interrupt controller mask register (PICMR) allows writing any value to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt writing a 1 unmasks (enables) the the interrupt.

For some reason the old code was or'ing the write values to the PICMR meaning it was not possible to ever mask a interrupt once it was enabled.

Quoted 8 lines

I have tested this by running linux 4.18 and my regular checks, I don't see any issues.

Reported-by Davidson Francis <[email protected]>
Signed-off-by Stafford Horne <[email protected]>
---
 target/openrisc/sys_helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by Richard Henderson <[email protected]>

r~