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ARM: socfpga: Assure correct CPACR configuration

PATCH New Marek Vasut 1 participant 3 messages Jul 14, 2018

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Marek Vasut

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#0 lore raw

PATCH 1/3 ARM: socfpga: Assure correct CPACR configuration

Make sure the ARM CPACR register is zeroed out, this is mandatory on Arria10.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/mach-socfpga/board.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
arch/arm/mach-socfpga/board.c +3 -1
index 26d84be6e9..e8c7503fba 100644
@@ -21,12 +21,14 @@ DECLARE_GLOBAL_DATA_PTR;
 void s_init(void) {
 #ifndef CONFIG_ARM64
 	/*
-	 * Preconfigure ACTLR, make sure Write Full Line of Zeroes is disabled.
+	 * Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
+	 * is disabled in ACTLR.
 	 * This is optional on CycloneV / ArriaV.
 	 * This is mandatory on Arria10, otherwise Linux refuses to boot.
 	 */
 	asm volatile(
 		"mcr p15, 0, %0, c1, c0, 1\n"
+		"mcr p15, 0, %0, c1, c0, 2\n"
 		"isb\n"
 		"dsb\n"
 	::"r"(0x0));
Signature · 1 line
2.16.2
author
#1 lore raw

PATCH 2/3 ARM: socfpga: Init missing security policies on A10

The Arria10 requires proper configuration of the NOC firewall, otherwise the access to certain areas of the LWHPS bridge fails in Linux. Add the missing setup.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/mach-socfpga/misc_arria10.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)
arch/arm/mach-socfpga/misc_arria10.c +13 -0
index a75cbc4ce6..80bf2f036f 100644
@@ -93,6 +93,19 @@ static void initialize_security_policies(void)
 	/* Put OCRAM in non-secure */
 	writel(0x003f0000, &noc_fw_ocram_base->region0);
 	writel(0x1, &noc_fw_ocram_base->enable);
+
+	/* Put DDR in non-secure */
+	writel(0xffff0000, SOCFPGA_SDR_FIREWALL_L3_ADDRESS + 0xc);
+	writel(0x1, SOCFPGA_SDR_FIREWALL_L3_ADDRESS);
+
+	/* Enable priviledged and non-priviledged access to L4 peripherals */
+	writel(~0, SOCFPGA_NOC_L4_PRIV_FLT_OFST);
+
+	/* Enable secure and non-secure transactions to bridges */
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST);
+	writel(~0, SOCFPGA_NOC_FW_H2F_SCR_OFST + 4);
+
+	writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set);
 }
 
 int arch_early_init_r(void)
Signature · 1 line
2.16.2
author
#2 lore raw

PATCH 3/3 ARM: dts: socfpga: Adjust NAND register layout on Arria10

In reply to Marek Vasut

Adjust the NAND register size on Arria10 to reflect reality.

Signed-off-by Marek Vasut <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Dinh Nguyen <[email protected]>
---
 arch/arm/dts/socfpga_arria10.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/socfpga_arria10.dtsi +2 -2
index b51febda9c..2f935a21e9 100644
@@ -637,8 +637,8 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "denali,denali-nand-dt", "altr,socfpga-denali-nand";
-			reg = <0xffb90000 0x72000>,
-			      <0xffb80000 0x10000>;
+			reg = <0xffb90000 0x20>,
+			      <0xffb80000 0x1000>;
 			reg-names = "nand_data", "denali_reg";
 			interrupts = <0 99 4>;
 			dma-mask = <0xffffffff>;
Signature · 1 line
2.16.2