clocksource: Convert to using %pOFn instead of device_node.name
Subsystems (11)
A message that is not in the archive (sent off-list or not yet received): 20181005143253.GE1881@mai
PATCH 1/13 clocksource: Convert to using %pOFn instead of device_node.name
From: Rob Herring <[email protected]>
In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier.
--- drivers/clocksource/asm9260_timer.c | 2 +- drivers/clocksource/cadence_ttc_timer.c | 2 +- drivers/clocksource/dw_apb_timer_of.c | 8 ++++---- drivers/clocksource/pxa_timer.c | 6 +++--- drivers/clocksource/time-orion.c | 8 ++++---- drivers/clocksource/timer-integrator-ap.c | 2 +- drivers/clocksource/timer-sp804.c | 2 +- drivers/clocksource/zevio-timer.c | 8 ++++---- 8 files changed, 19 insertions(+), 19 deletions(-)
drivers/clocksource/asm9260_timer.c +1 -1
@@ -193,7 +193,7 @@ static int __init asm9260_timer_init(struct device_node *np) priv.base =of_io_request_and_map (np,0 , np->name);if (IS_ERR (priv.base)) { -pr_err ("%s: unable to map resource\n" , np->name); +pr_err ("%pOFn: unable to map resource\n" , np);return PTR_ERR (priv.base); }
drivers/clocksource/cadence_ttc_timer.c +1 -1
@@ -535,7 +535,7 @@ static int __init ttc_timer_init(struct device_node *timer)if (ret)return ret; -pr_info ("%s #0 at %p, irq=%d\n" , timer->name, timer_baseaddr, irq); +pr_info ("%pOFn #0 at %p, irq=%d\n" , timer, timer_baseaddr, irq);return 0 ; }
drivers/clocksource/dw_apb_timer_of.c +4 -4
@@ -33,7 +33,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, *base =of_iomap (np,0 );if (!*base) -panic ("Unable to map regs for %s" , np->name); +panic ("Unable to map regs for %pOFn" , np);/* * Not all implementations use a periphal clock, so don't panic
@@ -42,8 +42,8 @@ static void __init timer_get_base_and_rate(struct device_node *np, pclk =of_clk_get_by_name (np,"pclk" );if (!IS_ERR (pclk))if (clk_prepare_enable (pclk)) -pr_warn ("pclk for %s is present, but could not be activated\n" , - np->name); +pr_warn ("pclk for %pOFn is present, but could not be activated\n" , + np); timer_clk =of_clk_get_by_name (np,"timer" );if (IS_ERR (timer_clk))
@@ -57,7 +57,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, try_clock_freq:if (of_property_read_u32 (np,"clock-freq" , rate) &&of_property_read_u32 (np,"clock-frequency" , rate)) -panic ("No clock nor clock-frequency property for %s" , np->name); +panic ("No clock nor clock-frequency property for %pOFn" , np); }static void __init add_clockevent (struct device_node *event_timer)
drivers/clocksource/pxa_timer.c +3 -3
@@ -191,13 +191,13 @@ static int __init pxa_timer_dt_init(struct device_node *np)/* timer registers are shared with watchdog timer */ timer_base =of_iomap (np,0 );if (!timer_base) { -pr_err ("%s: unable to map resource\n" , np->name); +pr_err ("%pOFn: unable to map resource\n" , np);return -ENXIO ; } clk =of_clk_get (np,0 );if (IS_ERR (clk)) { -pr_crit ("%s: unable to get clk\n" , np->name); +pr_crit ("%pOFn: unable to get clk\n" , np);return PTR_ERR (clk); }
@@ -210,7 +210,7 @@ static int __init pxa_timer_dt_init(struct device_node *np)/* we are only interested in OS-timer0 irq */ irq =irq_of_parse_and_map (np,0 );if (irq <=0 ) { -pr_crit ("%s: unable to parse OS-timer0 irq\n" , np->name); +pr_crit ("%pOFn: unable to parse OS-timer0 irq\n" , np);return -EINVAL ; }
drivers/clocksource/time-orion.c +4 -4
@@ -129,13 +129,13 @@ static int __init orion_timer_init(struct device_node *np)/* timer registers are shared with watchdog timer */ timer_base =of_iomap (np,0 );if (!timer_base) { -pr_err ("%s: unable to map resource\n" , np->name); +pr_err ("%pOFn: unable to map resource\n" , np);return -ENXIO ; } clk =of_clk_get (np,0 );if (IS_ERR (clk)) { -pr_err ("%s: unable to get clk\n" , np->name); +pr_err ("%pOFn: unable to get clk\n" , np);return PTR_ERR (clk); }
@@ -148,7 +148,7 @@ static int __init orion_timer_init(struct device_node *np)/* we are only interested in timer1 irq */ irq =irq_of_parse_and_map (np,1 );if (irq <=0 ) { -pr_err ("%s: unable to parse timer1 irq\n" , np->name); +pr_err ("%pOFn: unable to parse timer1 irq\n" , np);return -EINVAL ; }
@@ -174,7 +174,7 @@ static int __init orion_timer_init(struct device_node *np)/* setup timer1 as clockevent timer */ ret =setup_irq (irq, &orion_clkevt_irq);if (ret) { -pr_err ("%s: unable to setup irq\n" , np->name); +pr_err ("%pOFn: unable to setup irq\n" , np);return ret; }
drivers/clocksource/timer-integrator-ap.c +1 -1
@@ -190,7 +190,7 @@ static int __init integrator_ap_timer_init_of(struct device_node *node) clk =of_clk_get (node,0 );if (IS_ERR (clk)) { -pr_err ("No clock for %s\n" , node->name); +pr_err ("No clock for %pOFn\n" , node);return PTR_ERR (clk); }clk_prepare_enable (clk);
drivers/clocksource/timer-sp804.c +1 -1
@@ -249,7 +249,7 @@ static int __init sp804_of_init(struct device_node *np)if (of_clk_get_parent_count (np) ==3 ) { clk2 =of_clk_get (np,1 );if (IS_ERR (clk2)) { -pr_err ("sp804: %s clock not found: %d\n" , np->name, +pr_err ("sp804: %pOFn clock not found: %d\n" , np, (int )PTR_ERR (clk2)); clk2 =NULL ; }
drivers/clocksource/zevio-timer.c +4 -4
@@ -148,12 +148,12 @@ static int __init zevio_timer_add(struct device_node *node)of_address_to_resource (node,0 , &res);scnprintf (timer->clocksource_name,sizeof (timer->clocksource_name), -"%llx.%s_clocksource" , - (unsigned long long )res.start, node->name); +"%llx.%pOFn_clocksource" , + (unsigned long long )res.start, node);scnprintf (timer->clockevent_name,sizeof (timer->clockevent_name), -"%llx.%s_clockevent" , - (unsigned long long )res.start, node->name); +"%llx.%pOFn_clockevent" , + (unsigned long long )res.start, node);if (timer->interrupt_regs && irqnr) { timer->clkevt.name = timer->clockevent_name;
Signature · 1 line
2.7.4
PATCH 2/13 clocksource/drivers/renesas-ostm: Convert to SPDX identifiers
From: Kuninori Morimoto <[email protected]>
This patch updates license to use SPDX-License-Identifier instead of verbose license text.
--- drivers/clocksource/renesas-ostm.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-)
drivers/clocksource/renesas-ostm.c +1 -10
@@ -1,18 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Renesas Timer Support - OSTM * * Copyright (C) 2017 Renesas Electronics America, Inc. * Copyright (C) 2017 Chris Brandt -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* */ #include <linux/of_address.h>
Signature · 1 line
2.7.4
PATCH 3/13 clocksource/drivers/sh_cmt: Convert to SPDX identifiers
In reply to Daniel LezcanoFrom: Kuninori Morimoto <[email protected]>
This patch updates license to use SPDX-License-Identifier instead of verbose license text.
--- drivers/clocksource/sh_cmt.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)
drivers/clocksource/sh_cmt.c +1 -9
@@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SuperH Timer Support - CMT * * Copyright (C) 2008 Magnus Damm -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. */ #include <linux/clk.h>
Signature · 1 line
2.7.4
PATCH 4/13 clocksource/drivers/sh_mtu2: Convert to SPDX identifiers
In reply to Daniel LezcanoFrom: Kuninori Morimoto <[email protected]>
This patch updates license to use SPDX-License-Identifier instead of verbose license text.
--- drivers/clocksource/sh_mtu2.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)
drivers/clocksource/sh_mtu2.c +1 -9
@@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SuperH Timer Support - MTU2 * * Copyright (C) 2009 Magnus Damm -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. */ #include <linux/clk.h>
Signature · 1 line
2.7.4
PATCH 5/13 clocksource/drivers/sh_tmu: Convert to SPDX identifiers
In reply to Daniel LezcanoFrom: Kuninori Morimoto <[email protected]>
This patch updates license to use SPDX-License-Identifier instead of verbose license text.
--- drivers/clocksource/sh_tmu.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-)
drivers/clocksource/sh_tmu.c +1 -9
@@ -1,16 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SuperH Timer Support - TMU * * Copyright (C) 2009 Magnus Damm -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. */ #include <linux/clk.h>
Signature · 1 line
2.7.4
PATCH 6/13 clocksource/drivers/sh_cmt: Fixup for 64-bit machines
In reply to Daniel LezcanoFrom: Sergei Shtylyov <[email protected]>
When trying to use CMT for clockevents on R-Car gen3 SoCs, I noticed that 'max_delta_ns' for the broadcast timer (CMT) was shown as 1000 in /proc/timer_list. It turned out that when calculating it, the driver did 1 << 32 (causing what I think was undefined behavior) resulting in a zero delta, later clamped to 1000 by cev_delta2ns(). The root cause turned out to be that the driver abused *unsigned long* for the CMT register values (which are 16/32-bit), so that the calculation of 'ch->max_match_value' in sh_cmt_setup_channel() used the wrong branch. Using more proper 'u32' instead fixed 'max_delta_ns' and even fixed the switching an active clocksource to CMT (which caused the system to turn non-interactive before).
--- drivers/clocksource/sh_cmt.c | 72 ++++++++++++++++++++------------------------ 1 file changed, 33 insertions(+), 39 deletions(-)
drivers/clocksource/sh_cmt.c +33 -39
@@ -70,18 +70,17 @@ struct sh_cmt_info {unsigned int channels_mask;unsigned long width;/* 16 or 32 bit version of hardware block */ -unsigned long overflow_bit; -unsigned long clear_bits; +u32 overflow_bit; +u32 clear_bits;/* callbacks for CMSTR and CMCSR access */ -unsigned long (*read_control)(void __iomem *base,unsigned long offs); +u32 (*read_control)(void __iomem *base,unsigned long offs);void (*write_control)(void __iomem *base,unsigned long offs, -unsigned long value); +u32 value);/* callbacks for CMCNT and CMCOR access */ -unsigned long (*read_count)(void __iomem *base,unsigned long offs); -void (*write_count)(void __iomem *base,unsigned long offs, -unsigned long value); +u32 (*read_count)(void __iomem *base,unsigned long offs); +void (*write_count)(void __iomem *base,unsigned long offs,u32 value); };struct sh_cmt_channel {
@@ -95,9 +94,9 @@ struct sh_cmt_channel {unsigned int timer_bit;unsigned long flags; -unsigned long match_value; -unsigned long next_match_value; -unsigned long max_match_value; +u32 match_value; +u32 next_match_value; +u32 max_match_value;raw_spinlock_t lock;struct clock_event_device ced;struct clocksource cs;
@@ -152,24 +151,22 @@ struct sh_cmt_device {#define SH_CMT32_CMCSR_CKS_RCLK1 (7 << 0)#define SH_CMT32_CMCSR_CKS_MASK (7 << 0) -static unsigned long sh_cmt_read16 (void __iomem *base,unsigned long offs) +static u32 sh_cmt_read16 (void __iomem *base,unsigned long offs) {return ioread16 (base + (offs <<1 )); } -static unsigned long sh_cmt_read32 (void __iomem *base,unsigned long offs) +static u32 sh_cmt_read32 (void __iomem *base,unsigned long offs) {return ioread32 (base + (offs <<2 )); } -static void sh_cmt_write16 (void __iomem *base,unsigned long offs, -unsigned long value) +static void sh_cmt_write16 (void __iomem *base,unsigned long offs,u32 value) {iowrite16 (value, base + (offs <<1 )); } -static void sh_cmt_write32 (void __iomem *base,unsigned long offs, -unsigned long value) +static void sh_cmt_write32 (void __iomem *base,unsigned long offs,u32 value) {iowrite32 (value, base + (offs <<2 )); }
@@ -234,7 +231,7 @@ static const struct sh_cmt_info sh_cmt_info[] = {#define CMCNT 1/* channel register */ #define CMCOR 2/* channel register */ -static inline unsigned long sh_cmt_read_cmstr (struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmstr (struct sh_cmt_channel *ch) {if (ch->iostart)return ch->cmt->info->read_control (ch->iostart,0 );
@@ -242,8 +239,7 @@ static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_channel *ch)return ch->cmt->info->read_control (ch->cmt->mapbase,0 ); } -static inline void sh_cmt_write_cmstr (struct sh_cmt_channel *ch, -unsigned long value) +static inline void sh_cmt_write_cmstr (struct sh_cmt_channel *ch,u32 value) {if (ch->iostart) ch->cmt->info->write_control (ch->iostart,0 , value);
@@ -251,39 +247,35 @@ static inline void sh_cmt_write_cmstr(struct sh_cmt_channel *ch, ch->cmt->info->write_control (ch->cmt->mapbase,0 , value); } -static inline unsigned long sh_cmt_read_cmcsr (struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmcsr (struct sh_cmt_channel *ch) {return ch->cmt->info->read_control (ch->ioctrl,CMCSR ); } -static inline void sh_cmt_write_cmcsr (struct sh_cmt_channel *ch, -unsigned long value) +static inline void sh_cmt_write_cmcsr (struct sh_cmt_channel *ch,u32 value) { ch->cmt->info->write_control (ch->ioctrl,CMCSR , value); } -static inline unsigned long sh_cmt_read_cmcnt (struct sh_cmt_channel *ch) +static inline u32 sh_cmt_read_cmcnt (struct sh_cmt_channel *ch) {return ch->cmt->info->read_count (ch->ioctrl,CMCNT ); } -static inline void sh_cmt_write_cmcnt (struct sh_cmt_channel *ch, -unsigned long value) +static inline void sh_cmt_write_cmcnt (struct sh_cmt_channel *ch,u32 value) { ch->cmt->info->write_count (ch->ioctrl,CMCNT , value); } -static inline void sh_cmt_write_cmcor (struct sh_cmt_channel *ch, -unsigned long value) +static inline void sh_cmt_write_cmcor (struct sh_cmt_channel *ch,u32 value) { ch->cmt->info->write_count (ch->ioctrl,CMCOR , value); } -static unsigned long sh_cmt_get_counter (struct sh_cmt_channel *ch, -int *has_wrapped) +static u32 sh_cmt_get_counter (struct sh_cmt_channel *ch,u32 *has_wrapped) { -unsigned long v1, v2, v3; -int o1, o2; +u32 v1, v2, v3; +u32 o1, o2; o1 =sh_cmt_read_cmcsr (ch) & ch->cmt->info->overflow_bit;
@@ -303,7 +295,8 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_channel *ch,static void sh_cmt_start_stop_ch (struct sh_cmt_channel *ch,int start) { -unsigned long flags, value; +unsigned long flags; +u32 value;/* start stop register shared by multiple timer channels */ raw_spin_lock_irqsave (&ch->cmt->lock, flags);
@@ -410,11 +403,11 @@ static void sh_cmt_disable(struct sh_cmt_channel *ch)static void sh_cmt_clock_event_program_verify (struct sh_cmt_channel *ch,int absolute) { -unsigned long new_match; -unsigned long value = ch->next_match_value; -unsigned long delay =0 ; -unsigned long now =0 ; -int has_wrapped; +u32 value = ch->next_match_value; +u32 new_match; +u32 delay =0 ; +u32 now =0 ; +u32 has_wrapped; now =sh_cmt_get_counter (ch, &has_wrapped); ch->flags |=FLAG_REPROGRAM ;/* force reprogram */
@@ -611,9 +604,10 @@ static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs)static u64 sh_cmt_clocksource_read (struct clocksource *cs) {struct sh_cmt_channel *ch =cs_to_sh_cmt (cs); -unsigned long flags, raw; +unsigned long flags;unsigned long value; -int has_wrapped; +u32 has_wrapped; +u32 raw;raw_spin_lock_irqsave (&ch->lock, flags); value = ch->total_cycles;
Signature · 1 line
2.7.4
PATCH 7/13 clocksource/drivers/sh_cmt: Fix clocksource width for 32-bit machines
In reply to Daniel LezcanoFrom: Sergei Shtylyov <[email protected]>
The driver seems to abuse *unsigned long* not only for the (32-bit) register values but also for the 'sh_cmt_channel::total_cycles' which needs to always be 64-bit -- as a result, the clocksource's mask is needlessly clamped down to 32-bits on the 32-bit machines...
--- drivers/clocksource/sh_cmt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/clocksource/sh_cmt.c +3 -3
@@ -100,7 +100,7 @@ struct sh_cmt_channel {raw_spinlock_t lock;struct clock_event_device ced;struct clocksource cs; -unsigned long total_cycles; +u64 total_cycles;bool cs_enabled; };
@@ -605,8 +605,8 @@ static u64 sh_cmt_clocksource_read(struct clocksource *cs) {struct sh_cmt_channel *ch =cs_to_sh_cmt (cs);unsigned long flags; -unsigned long value;u32 has_wrapped; +u64 value;u32 raw;raw_spin_lock_irqsave (&ch->lock, flags);
@@ -680,7 +680,7 @@ static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, cs->disable = sh_cmt_clocksource_disable; cs->suspend = sh_cmt_clocksource_suspend; cs->resume = sh_cmt_clocksource_resume; - cs->mask =CLOCKSOURCE_MASK (sizeof (unsigned long ) *8 ); + cs->mask =CLOCKSOURCE_MASK (sizeof (u64) *8 ); cs->flags =CLOCK_SOURCE_IS_CONTINUOUS ; dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",
Signature · 1 line
2.7.4
PATCH 8/13 clocksource/drivers/sh_cmt: Properly line-wrap sh_cmt_of_table[] initializer
In reply to Daniel LezcanoFrom: Sergei Shtylyov <[email protected]>
There's no good reason for the sh_cmt_of_table[] initializer to violate the 80-column limit, especially after the commit 8d50e9476bb4 ("clocksource/drivers/sh_cmt: Mark "renesas,cmt-48-gen2" deprecated") partially fixed it -- fix the R-Car gen2 related entries as well.
--- drivers/clocksource/sh_cmt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)
drivers/clocksource/sh_cmt.c +8 -2
@@ -927,8 +927,14 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { .compatible = "renesas,cmt-48-gen2", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, - { .compatible = "renesas,rcar-gen2-cmt0", .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] }, - { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, + { + .compatible = "renesas,rcar-gen2-cmt0", + .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] + }, + { + .compatible = "renesas,rcar-gen2-cmt1", + .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] + }, { } };MODULE_DEVICE_TABLE (of, sh_cmt_of_table);
Signature · 1 line
2.7.4
PATCH 9/13 dt-bindings: timer: renesas: cmt: document R-Car gen3 support
In reply to Daniel LezcanoFrom: Sergei Shtylyov <[email protected]>
Document support for the R-Car gen3 CMT types 0/1 bindings -- they seem to be the same CMT types 0/1 as in the R-Car gen2 SoCs.
Also document R8A779{7|8}0 bindings as these are the R-Car gen3 SoCs for which the initial support was done.
--- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 7 +++++++ 1 file changed, 7 insertions(+)
Documentation/devicetree/bindings/timer/renesas,cmt.txt +7 -0
@@ -34,6 +34,10 @@ Required Properties: - "renesas,r8a7793-cmt1" for the 48-bit CMT1 device included in r8a7793. - "renesas,r8a7794-cmt0" for the 32-bit CMT0 device included in r8a7794. - "renesas,r8a7794-cmt1" for the 48-bit CMT1 device included in r8a7794. + - "renesas,r8a77970-cmt0" for the 32-bit CMT0 device included in r8a77970. + - "renesas,r8a77970-cmt1" for the 48-bit CMT1 device included in r8a77970. + - "renesas,r8a77980-cmt0" for the 32-bit CMT0 device included in r8a77980. + - "renesas,r8a77980-cmt1" for the 48-bit CMT1 device included in r8a77980. - "renesas,rcar-gen2-cmt0" for 32-bit CMT0 devices included in R-Car Gen2 and RZ/G1.
@@ -41,6 +45,9 @@ Required Properties: and RZ/G1. These are fallbacks for r8a73a4, R-Car Gen2 and RZ/G1 entries listed above. + - "renesas,rcar-gen3-cmt0" for 32-bit CMT0 devices included in R-Car Gen3. + - "renesas,rcar-gen3-cmt1" for 48-bit CMT1 devices included in R-Car Gen3. + These are fallbacks for R-Car Gen3 entries listed above. - reg: base address and length of the registers block for the timer module. - interrupts: interrupt-specifier for the timer, one per channel.
Signature · 1 line
2.7.4
PATCH 10/13 clocksource/drivers/sh_cmt: Add R-Car gen3 support
In reply to Daniel LezcanoFrom: Sergei Shtylyov <[email protected]>
Add support for the R-Car gen3 CMT types 0/1 -- they seem to be the same CMT types 0/1 as in R-Car gen2 SoCs.
--- drivers/clocksource/sh_cmt.c | 8 ++++++++ 1 file changed, 8 insertions(+)
drivers/clocksource/sh_cmt.c +8 -0
@@ -935,6 +935,14 @@ static const struct of_device_id sh_cmt_of_table[] __maybe_unused = { .compatible = "renesas,rcar-gen2-cmt1", .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] }, + { + .compatible = "renesas,rcar-gen3-cmt0", + .data = &sh_cmt_info[SH_CMT0_RCAR_GEN2] + }, + { + .compatible = "renesas,rcar-gen3-cmt1", + .data = &sh_cmt_info[SH_CMT1_RCAR_GEN2] + }, { } };MODULE_DEVICE_TABLE (of, sh_cmt_of_table);
Signature · 1 line
2.7.4
PATCH 11/13 clocksource/drivers: Unify the names to timer-* format
In reply to Daniel LezcanoIn order to make some housekeeping in the directory, this patch renames drivers to the timer-* format in order to unify their names.
There is no functional changes.
---
MAINTAINERS | 10 ++++-----
drivers/clocksource/Makefile | 26 +++++++++++-----------
...{time-armada-370-xp.c => timer-armada-370-xp.c} | 0
.../{cadence_ttc_timer.c => timer-cadence-ttc.c} | 0
.../clocksource/{time-efm32.c => timer-efm32.c} | 0
.../{fsl_ftm_timer.c => timer-fsl-ftm.c} | 0
.../{time-lpc32xx.c => timer-lpc32xx.c} | 0
.../clocksource/{time-orion.c => timer-orion.c} | 0
drivers/clocksource/{owl-timer.c => timer-owl.c} | 0
.../{time-pistachio.c => timer-pistachio.c} | 0
drivers/clocksource/{qcom-timer.c => timer-qcom.c} | 0
.../clocksource/{versatile.c => timer-versatile.c} | 0
.../clocksource/{vf_pit_timer.c => timer-vf-pit.c} | 0
.../clocksource/{vt8500_timer.c => timer-vt8500.c} | 0
.../clocksource/{zevio-timer.c => timer-zevio.c} | 0
15 files changed, 18 insertions(+), 18 deletions(-)
rename drivers/clocksource/{time-armada-370-xp.c => timer-armada-370-xp.c} (100%)
rename drivers/clocksource/{cadence_ttc_timer.c => timer-cadence-ttc.c} (100%)
rename drivers/clocksource/{time-efm32.c => timer-efm32.c} (100%)
rename drivers/clocksource/{fsl_ftm_timer.c => timer-fsl-ftm.c} (100%)
rename drivers/clocksource/{time-lpc32xx.c => timer-lpc32xx.c} (100%)
rename drivers/clocksource/{time-orion.c => timer-orion.c} (100%)
rename drivers/clocksource/{owl-timer.c => timer-owl.c} (100%)
rename drivers/clocksource/{time-pistachio.c => timer-pistachio.c} (100%)
rename drivers/clocksource/{qcom-timer.c => timer-qcom.c} (100%)
rename drivers/clocksource/{versatile.c => timer-versatile.c} (100%)
rename drivers/clocksource/{vf_pit_timer.c => timer-vf-pit.c} (100%)
rename drivers/clocksource/{vt8500_timer.c => timer-vt8500.c} (100%)
rename drivers/clocksource/{zevio-timer.c => timer-zevio.c} (100%)MAINTAINERS +5 -5
@@ -1181,7 +1181,7 @@ N: owl F: arch/arm/mach-actions/ F: arch/arm/boot/dts/owl-* F: arch/arm64/boot/dts/actions/ -F: drivers/clocksource/owl-* +F: drivers/clocksource/timer-owl* F: drivers/pinctrl/actions/* F: drivers/soc/actions/ F: include/dt-bindings/power/owl-*
@@ -1604,7 +1604,7 @@ L: [email protected] (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/lpc43* F: drivers/clk/nxp/clk-lpc18xx* -F: drivers/clocksource/time-lpc32xx.c +F: drivers/clocksource/timer-lpc32xx.c F: drivers/i2c/busses/i2c-lpc2k.c F: drivers/memory/pl172.c F: drivers/mtd/spi-nor/nxp-spifi.c
@@ -2220,7 +2220,7 @@ F: arch/arm/mach-vexpress/ F: */*/vexpress* F: */*/*/vexpress* F: drivers/clk/versatile/clk-vexpress-osc.c -F: drivers/clocksource/versatile.c +F: drivers/clocksource/timer-versatile.c N: mps2 ARM/VFP SUPPORT
@@ -2242,7 +2242,7 @@ M: Tony Prisk <[email protected]> L: [email protected] (moderated for non-subscribers) S: Maintained F: arch/arm/mach-vt8500/ -F: drivers/clocksource/vt8500_timer.c +F: drivers/clocksource/timer-vt8500.c F: drivers/i2c/busses/i2c-wmt.c F: drivers/mmc/host/wmt-sdmmc.c F: drivers/pwm/pwm-vt8500.c
@@ -2307,7 +2307,7 @@ F: drivers/cpuidle/cpuidle-zynq.c F: drivers/block/xsysace.c N: zynq N: xilinx -F: drivers/clocksource/cadence_ttc_timer.c +F: drivers/clocksource/timer-cadence-ttc.c F: drivers/i2c/busses/i2c-cadence.c F: drivers/mmc/host/sdhci-of-arasan.c F: drivers/edac/synopsys_edac.c
drivers/clocksource/Makefile +13 -13
@@ -23,8 +23,8 @@ obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o -obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o -obj-$(CONFIG_ORION_TIMER) += time-orion.o +obj-$(CONFIG_ARMADA_370_XP_TIMER) += timer-armada-370-xp.o +obj-$(CONFIG_ORION_TIMER) += timer-orion.o obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o
@@ -36,25 +36,25 @@ obj-$(CONFIG_SUN4I_TIMER) += sun4i_timer.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += meson6_timer.o obj-$(CONFIG_TEGRA_TIMER) += tegra20_timer.o -obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o -obj-$(CONFIG_NSPIRE_TIMER) += zevio-timer.o +obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o +obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o -obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence_ttc_timer.o -obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o +obj-$(CONFIG_CADENCE_TTC_TIMER) += timer-cadence-ttc.o +obj-$(CONFIG_CLKSRC_EFM32) += timer-efm32.o obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o -obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o +obj-$(CONFIG_CLKSRC_LPC32XX) += timer-lpc32xx.o obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o -obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o -obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o -obj-$(CONFIG_CLKSRC_QCOM) += qcom-timer.o +obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o +obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o +obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o -obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o +obj-$(CONFIG_CLKSRC_PISTACHIO) += timer-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o -obj-$(CONFIG_OWL_TIMER) += owl-timer.o +obj-$(CONFIG_OWL_TIMER) += timer-owl.o obj-$(CONFIG_SPRD_TIMER) += timer-sprd.o obj-$(CONFIG_NPCM7XX_TIMER) += timer-npcm7xx.o
@@ -66,7 +66,7 @@ obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST) += dummy_timer.o obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o -obj-$(CONFIG_CLKSRC_VERSATILE) += versatile.o +obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o
drivers/clocksource/timer-armada-370-xp.c renamed from drivers/clocksource/time-armada-370-xp.c +0 -0
drivers/clocksource/timer-cadence-ttc.c renamed from drivers/clocksource/cadence_ttc_timer.c +0 -0
drivers/clocksource/timer-efm32.c renamed from drivers/clocksource/time-efm32.c +0 -0
drivers/clocksource/timer-fsl-ftm.c renamed from drivers/clocksource/fsl_ftm_timer.c +0 -0
drivers/clocksource/timer-lpc32xx.c renamed from drivers/clocksource/time-lpc32xx.c +0 -0
drivers/clocksource/timer-orion.c renamed from drivers/clocksource/time-orion.c +0 -0
drivers/clocksource/timer-owl.c renamed from drivers/clocksource/owl-timer.c +0 -0
drivers/clocksource/timer-pistachio.c renamed from drivers/clocksource/time-pistachio.c +0 -0
drivers/clocksource/timer-qcom.c renamed from drivers/clocksource/qcom-timer.c +0 -0
drivers/clocksource/timer-versatile.c renamed from drivers/clocksource/versatile.c +0 -0
drivers/clocksource/timer-vf-pit.c renamed from drivers/clocksource/vf_pit_timer.c +0 -0
drivers/clocksource/timer-vt8500.c renamed from drivers/clocksource/vt8500_timer.c +0 -0
drivers/clocksource/timer-zevio.c renamed from drivers/clocksource/zevio-timer.c +0 -0
Signature · 1 line
2.7.4
PATCH 12/13 clocksource: Remove obsolete CLOCKSOURCE_OF_DECLARE
In reply to Daniel LezcanoThe macro CLOCKSOURCE_OF_DECLARE was renamed more TIMER_OF_DECLARE, and we kept an alias CLOCKSOURCE_OF_DECLARE in order to smooth the transition for drivers.
This change was done 1.5 year ago, we can reasonably remove this backward compatible macro as it is no longer used anywhere.
--- include/linux/clocksource.h | 3 --- 1 file changed, 3 deletions(-)
include/linux/clocksource.h +0 -3
@@ -257,9 +257,6 @@ extern int clocksource_i8253_init(void);#define TIMER_OF_DECLARE (name, compat, fn) \ OF_DECLARE_1_RET(timer, name, compat, fn) -#define CLOCKSOURCE_OF_DECLARE (name, compat, fn) \ - TIMER_OF_DECLARE(name, compat, fn) -#ifdef CONFIG_TIMER_PROBE extern void timer_probe (void );#else
Signature · 1 line
2.7.4
PATCH 13/13 clocksource/drivers/dw_apb: Add reset control
In reply to Daniel LezcanoFrom: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
This patch is needed for systems where the bootloader has left the timer not used in reset.
- Trivial conflict with commit a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"
--- drivers/clocksource/dw_apb_timer_of.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
drivers/clocksource/dw_apb_timer_of.c +12 -0
@@ -22,6 +22,7 @@#include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/clk.h> +#include <linux/reset.h> #include <linux/sched_clock.h> static void __init timer_get_base_and_rate(struct device_node *np,
@@ -29,6 +30,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, {struct clk *timer_clk;struct clk *pclk; +struct reset_control *rstc; *base =of_iomap (np,0 );
@@ -36,6 +38,16 @@ static void __init timer_get_base_and_rate(struct device_node *np,panic ("Unable to map regs for %pOFn" , np);/* +* Reset the timer if the reset control is available, wiping +* out the state the firmware may have left it +*/ + rstc =of_reset_control_get (np,NULL ); +if (!IS_ERR (rstc)) { +reset_control_assert (rstc); +reset_control_deassert (rstc); + } + +/* * Not all implementations use a periphal clock, so don't panic * if it's not present */
Signature · 1 line
2.7.4
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
Quoted 7 lines · Daniel Lezcano
From: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
Quoted 8 lines
This patch is needed for systems where the bootloader has left the timer not used in reset.
- Trivial conflict with commit
a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"Signed-off-by Marek Vasut <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>
Ingo just noticed, that this SOB chain is wrong. How is Marek involved here? Can you please fix that up and send me another pull request?
Thanks,
tglx
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
Quoted 12 lines · Thomas Gleixner
Quoted 10 lines · Daniel Lezcano
From: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
This patch is needed for systems where the bootloader has left the timer not used in reset.
Quoted 8 lines
Quoted 5 lines
- Trivial conflict with commit
a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"Signed-off-by Marek Vasut <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>Ingo just noticed, that this SOB chain is wrong. How is Marek involved here? Can you please fix that up and send me another pull request?
Thomas,
I will fix it as soon as possible but I would like to give the opportunity to Dinh to explain why he sent the patch with Marek's SOB.
Dinh ?
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
Quoted 22 lines · Daniel Lezcano
Quoted 12 lines · Thomas Gleixner
Quoted 10 lines · Daniel Lezcano
From: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
This patch is needed for systems where the bootloader has left the timer not used in reset.
Quoted 8 lines
Quoted 5 lines
- Trivial conflict with commit
a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"Signed-off-by Marek Vasut <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>Ingo just noticed, that this SOB chain is wrong. How is Marek involved here? Can you please fix that up and send me another pull request?
Quoted 6 lines
Thomas,
I will fix it as soon as possible but I would like to give the opportunity to Dinh to explain why he sent the patch with Marek's SOB.
Dinh ?
No rush.
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
Quoted 24 lines · Thomas Gleixner
Quoted 22 lines · Daniel Lezcano
Quoted 20 lines · Thomas Gleixner
Quoted 7 lines · Daniel Lezcano
From: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
Quoted 8 lines
This patch is needed for systems where the bootloader has left the timer not used in reset.
- Trivial conflict with commit
a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"Signed-off-by Marek Vasut <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>Ingo just noticed, that this SOB chain is wrong. How is Marek involved here? Can you please fix that up and send me another pull request?
Quoted 8 lines
Quoted 6 lines
Thomas,
I will fix it as soon as possible but I would like to give the opportunity to Dinh to explain why he sent the patch with Marek's SOB.
Dinh ?
No rush.
I reported this to Dinh and gave him some prototype patches to start with, since I didn't have the time to write a patch. You can change it to Reported-by: if you want.
Signature · 2 lines
Best regards, Marek Vasut
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
Quoted 30 lines · Marek Vasut
Quoted 29 lines · Thomas Gleixner
Quoted 27 lines · Daniel Lezcano
Quoted 12 lines · Thomas Gleixner
Quoted 10 lines · Daniel Lezcano
From: Dinh Nguyen <[email protected]>
Add code to retrieve the reset property from the dw-apb timers and if the property is available, the safe operation is to assert the timer into reset, and followed by a deassert of the timer reset (brings the timer out of reset).
This patch is needed for systems where the bootloader has left the timer not used in reset.
Quoted 8 lines
Quoted 5 lines
- Trivial conflict with commit
a74bd1ad7a:
"Convert to using %pOFn instead of device_node.name"Signed-off-by Marek Vasut <[email protected]>Signed-off-by Dinh Nguyen <[email protected]>Ingo just noticed, that this SOB chain is wrong. How is Marek involved here? Can you please fix that up and send me another pull request?
Thomas,
I will fix it as soon as possible but I would like to give the opportunity to Dinh to explain why he sent the patch with Marek's SOB.
Quoted 7 lines
Quoted 3 lines
Quoted 1 line
Dinh ?
No rush.
I reported this to Dinh and gave him some prototype patches to start with, since I didn't have the time to write a patch. You can change it to Reported-by: if you want.
Ok, thanks
Signature · 5 lines
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook | <http://twitter.com/#!/linaroorg> Twitter | <http://www.linaro.org/linaro-blog/> Blog
Re: [PATCH 13/13] clocksource/drivers/dw_apb: Add reset control
In reply to Marek VasutQuoted 4 lines · Marek Vasut
I reported this to Dinh and gave him some prototype patches to start with, since I didn't have the time to write a patch. You can change it to Reported-by: if you want.
Marek, thanks for clarification!
Quoted 11 lines · Daniel Lezcano
From: Rob Herring <[email protected]>
In preparation to remove the node name pointer from struct
device_node, convert printf users to use the %pOFn format specifier.Cc Daniel Lezcano <[email protected]>Cc Thomas Gleixner <[email protected]>Cc Michal Simek <[email protected]>Cc linux-arm-kernel at lists.infradead.orgSigned-off-by Rob Herring <[email protected]>Signed-off-by Daniel Lezcano <[email protected]>
Quoted 3 lines
--- drivers/clocksource/asm9260_timer.c | 2 +- drivers/clocksource/cadence_ttc_timer.c | 2 +-
Thanks,
Michal