tools: Fix diverse typos
PATCH 1/1 tools: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )
No change in functionality intended.
Cc Arnaldo Carvalho de Melo <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
--- tools/lib/subcmd/parse-options.h | 4 +-- tools/lib/traceevent/event-parse.c | 12 ++++----- tools/lib/traceevent/plugin_kvm.c | 2 +- tools/perf/Documentation/perf-list.txt | 2 +- tools/perf/Documentation/perf-report.txt | 2 +- tools/perf/Documentation/perf-stat.txt | 4 +-- tools/perf/arch/x86/tests/insn-x86.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/builtin-trace.c | 2 +- .../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++----- tools/perf/tests/attr.c | 2 +- tools/perf/util/annotate.c | 2 +- tools/perf/util/bpf-loader.c | 2 +- tools/perf/util/header.c | 2 +- tools/perf/util/hist.c | 2 +- tools/perf/util/jitdump.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/probe-event.c | 4 +-- tools/perf/util/sort.c | 2 +- 30 files changed, 62 insertions(+), 62 deletions(-)
tools/lib/subcmd/parse-options.h +2 -2
@@ -71,7 +71,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `argh`:: * token to explain the kind of argument this option wants. Keep it -* homogenous across the repository. +* homogeneous across the repository. * * `help`:: * the short help associated to what the option does.
@@ -80,7 +80,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `flags`:: * mask of parse_opt_option_flags. -* PARSE_OPT_OPTARG: says that the argument is optionnal (not for BOOLEANs) +* PARSE_OPT_OPTARG: says that the argument is optional (not for BOOLEANs) * PARSE_OPT_NOARG: says that this option takes no argument, for CALLBACKs * PARSE_OPT_NONEG: says that this option cannot be negated * PARSE_OPT_HIDDEN this option is skipped in the default usage, showed in
tools/lib/traceevent/event-parse.c +6 -6
@@ -1145,7 +1145,7 @@ static enum tep_event_type read_token(char **tok) }/** -* tep_read_token - access to utilites to use the pevent parser +* tep_read_token - access to utilities to use the pevent parser * @tok: The token to return * * This will parse tokens from the string given by
@@ -3258,7 +3258,7 @@ static int event_read_print(struct tep_event_format *event)* @name: the name of the common field to return * * Returns a common field from the event by the given @name. -* This only searchs the common fields and not all field. +* This only searches the common fields and not all field. */ struct tep_format_field *tep_find_common_field (struct tep_event_format *event,const char *name)
@@ -3302,7 +3302,7 @@ tep_find_field(struct tep_event_format *event, const char *name)* @name: the name of the field * * Returns a field by the given @name. -* This searchs the common field names first, then +* This searches the common field names first, then * the non-common ones if a common one was not found. */ struct tep_format_field *
@@ -3838,7 +3838,7 @@ static void print_bitmask_to_seq(struct tep_handle *pevent,/* * data points to a bit mask of size bytes. * In the kernel, this is an array of long words, thus -* endianess is very important. +* endianness is very important. */ if (pevent->file_bigendian) index = size - (len +1 );
@@ -5313,9 +5313,9 @@ pid_from_cmdlist(struct tep_handle *pevent, const char *comm, struct cmdline *ne* This returns the cmdline structure that holds a pid for a given * comm, or NULL if none found. As there may be more than one pid for * a given comm, the result of this call can be passed back into -* a recurring call in the @next paramater, and then it will find the +* a recurring call in the @next parameter, and then it will find the * next pid. -* Also, it does a linear seach, so it may be slow. +* Also, it does a linear search, so it may be slow. */ struct cmdline *tep_data_pid_from_comm (struct tep_handle *pevent,const char *comm,struct cmdline *next)
tools/lib/traceevent/plugin_kvm.c +1 -1
@@ -387,7 +387,7 @@ static int kvm_mmu_print_role(struct trace_seq *s, struct tep_record *record,/* * We can only use the structure if file is of the same -* endianess. +* endianness. */ if (tep_is_file_bigendian (event->pevent) ==tep_is_host_bigendian (event->pevent)) {
tools/perf/Documentation/perf-list.txt +1 -1
@@ -172,7 +172,7 @@ like cycles and instructions and some software events. Other PMUs and global measurements are normally root only. Some event qualifiers, such as "any", are also root only. -This can be overriden by setting the kernel.perf_event_paranoid +This can be overridden by setting the kernel.perf_event_paranoid sysctl to -1, which allows non root to use these events. For accessing trace point events perf needs to have read access to
tools/perf/Documentation/perf-report.txt +1 -1
@@ -244,7 +244,7 @@ OPTIONS Usually more convenient to use --branch-history for this. value can be: - - percent: diplay overhead percent (default) + - percent: display overhead percent (default) - period: display event period - count: display event count
tools/perf/Documentation/perf-stat.txt +2 -2
@@ -50,7 +50,7 @@ report:: /sys/bus/event_source/devices/<pmu>/format/* Note that the last two syntaxes support prefix and glob matching in - the PMU name to simplify creation of events accross multiple instances + the PMU name to simplify creation of events across multiple instances of the same type of PMU in large systems (e.g. memory controller PMUs). Multiple PMU instances are typical for uncore PMUs, so the prefix 'uncore_' is also ignored when performing this match.
@@ -277,7 +277,7 @@ echo 0 > /proc/sys/kernel/nmi_watchdog for best results. Otherwise the bottlenecks may be inconsistent on workload with changing phases. -This enables --metric-only, unless overriden with --no-metric-only. +This enables --metric-only, unless overridden with --no-metric-only. To interpret the results it is usually needed to know on which CPUs the workload runs on. If needed the CPUs can be forced using
tools/perf/arch/x86/tests/insn-x86.c +1 -1
@@ -170,7 +170,7 @@ static int test_data_set(struct test_data *dat_set, int x86_64)* * If the test passes %0 is returned, otherwise %-1 is returned. Use the * verbose (-v) option to see all the instructions and whether or not they -* decoded successfuly. +* decoded successfully. */ int test__insn_x86 (struct test *test__maybe_unused ,int subtest__maybe_unused ) {
tools/perf/builtin-top.c +1 -1
@@ -595,7 +595,7 @@ static void *display_thread_tui(void *arg)/* * Initialize the uid_filter_str, in the future the TUI will allow -* Zooming in/out UIDs. For now juse use whatever the user passed +* Zooming in/out UIDs. For now just use whatever the user passed * via --uid. */ evlist__for_each_entry (top->evlist, pos) {
tools/perf/builtin-trace.c +1 -1
@@ -2782,7 +2782,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv)* Now that we already used evsel->attr to ask the kernel to setup the * events, lets reuse evsel->attr.sample_max_stack as the limit in * trace__resolve_callchain(), allowing per-event max-stack settings -* to override an explicitely set --max-stack global setting. +* to override an explicitly set --max-stack global setting. */ evlist__for_each_entry (evlist, evsel) { if (evsel__has_callchain(evsel) &&
tools/perf/pmu-events/arch/x86/broadwell/cache.json +2 -2
@@ -433,7 +433,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -445,7 +445,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +1 -1
@@ -317,7 +317,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "EventCode": "0x87", "Counter": "0,1,2,3", "UMask": "0x1",
tools/perf/pmu-events/arch/x86/broadwellde/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/broadwellx/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/jaketown/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/knightslanding/cache.json +15 -15
@@ -121,7 +121,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -187,7 +187,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -253,7 +253,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -319,7 +319,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -385,7 +385,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -451,7 +451,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -539,7 +539,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -605,7 +605,7 @@ "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -682,7 +682,7 @@ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -748,7 +748,7 @@ "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -869,7 +869,7 @@ "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -935,7 +935,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1067,7 +1067,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1133,7 +1133,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1199,7 +1199,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
tools/perf/pmu-events/arch/x86/sandybridge/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +6 -6
@@ -428,7 +428,7 @@ "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", "UMask": "0x10", "Unit": "CHA" },
@@ -967,7 +967,7 @@ "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", "Unit": "M2M" }, {
@@ -1041,7 +1041,7 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", "Unit": "UPI LL" },
@@ -1051,17 +1051,17 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", "Unit": "UPI LL" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer", + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", "Unit": "UPI LL" },
tools/perf/tests/attr.c +1 -1
@@ -182,7 +182,7 @@ int test__attr(struct test *test __maybe_unused, int subtest __maybe_unused)char path_perf[PATH_MAX ];char path_dir[PATH_MAX ]; -/* First try developement tree tests. */ +/* First try development tree tests. */ if (!lstat ("./tests" , &st))return run_dir ("./tests" ,"./perf" );
tools/perf/util/annotate.c +1 -1
@@ -1758,7 +1758,7 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args)while (!feof (file)) {/* * The source code line number (lineno) needs to be kept in -* accross calls to symbol__parse_objdump_line(), so that it +* across calls to symbol__parse_objdump_line(), so that it * can associate it with the instructions till the next one. * See disasm_line__new() and struct disasm_line::line_nr. */
tools/perf/util/bpf-loader.c +1 -1
@@ -99,7 +99,7 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source)if (err)return ERR_PTR (-BPF_LOADER_ERRNO__COMPILE ); }else -pr_debug ("bpf: successfull builtin compilation\n" ); +pr_debug ("bpf: successful builtin compilation\n" ); obj =bpf_object__open_buffer (obj_buf, obj_buf_sz, filename);if (!IS_ERR_OR_NULL (obj) && llvm_param.dump_obj)
tools/perf/util/header.c +1 -1
@@ -2798,7 +2798,7 @@ static int perf_header__adds_write(struct perf_header *header,lseek (fd, sec_start,SEEK_SET );/* * may write more than needed due to dropped feature, but -* this is okay, reader will skip the mising entries +* this is okay, reader will skip the missing entries */ err =do_write (&ff, feat_sec, sec_size);if (err <0 )
tools/perf/util/hist.c +1 -1
@@ -1160,7 +1160,7 @@ void hist_entry__delete(struct hist_entry *he)/* * If this is not the last column, then we need to pad it according to the -* pre-calculated max lenght for this column, otherwise don't bother adding +* pre-calculated max length for this column, otherwise don't bother adding * spaces because that would break viewing this with, for instance, 'less', * that would show tons of trailing spaces when a long C++ demangled method * names is sampled.
tools/perf/util/jitdump.c +1 -1
@@ -38,7 +38,7 @@ struct jit_buf_desc {uint64_t sample_type;size_t bufsize;FILE *in; -bool needs_bswap;/* handles cross-endianess */ +bool needs_bswap;/* handles cross-endianness */ bool use_arch_timestamp;void *debug_data;void *unwinding_data;
tools/perf/util/machine.c +1 -1
@@ -137,7 +137,7 @@ struct machine *machine__new_kallsyms(void)struct machine *machine =machine__new_host ();/* * FIXME: -* 1) We should switch to machine__load_kallsyms(), i.e. not explicitely +* 1) We should switch to machine__load_kallsyms(), i.e. not explicitly * ask for not using the kcore parsing code, once this one is fixed * to create a map per module. */
tools/perf/util/probe-event.c +2 -2
@@ -692,7 +692,7 @@ static int add_exec_to_probe_trace_events(struct probe_trace_event *tevs,return ret;for (i =0 ; i < ntevs && ret >=0 ; i++) { -/* point.address is the addres of point.symbol + point.offset */ +/* point.address is the address of point.symbol + point.offset */ tevs[i].point.address -= stext; tevs[i].point.module =strdup (exec);if (!tevs[i].point.module) {
@@ -3062,7 +3062,7 @@ static int try_to_find_absolute_address(struct perf_probe_event *pev,/* * Give it a '0x' leading symbol name. * In __add_probe_trace_events, a NULL symbol is interpreted as -* invalud. +* invalid. */ if (asprintf (&tp->symbol,"0x%lx" , tp->address) <0 ) goto errout;
tools/perf/util/sort.c +1 -1
@@ -36,7 +36,7 @@ enum sort_mode sort__mode = SORT_MODE__NORMAL;* -t, --field-separator * * option, that uses a special separator character and don't pad with spaces, -* replacing all occurances of this separator in symbol names (and other +* replacing all occurrences of this separator in symbol names (and other * output) with a '.' character, that thus it's the only non valid separator. */ static int repsep_snprintf (char *bf,size_t size,const char *fmt, ...)
Peter Zijlstra
maintainerQuoted 7 lines · Ingo Molnar
Go over the
tools/files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )
Quoted 12 lines
.../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++-----
Yeah, so I think those are generated from somewhere, fixing them here isn't going to nessecarily help much.
Andi, how do we get the source for that fixed?
Quoted 21 lines · Peter Zijlstra
Quoted 7 lines · Ingo Molnar
Go over the
tools/files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )Quoted 12 lines
.../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++-----
Quoted 2 lines
Yeah, so I think those are generated from somewhere, fixing them here isn't going to nessecarily help much.
It's in our source code, the output is visible to our users, so such typos should be fixed.
But yes, I agree that the fixes should also be applied at the Intel source of the JSON definitions.
Thanks,
Ingo
Arnaldo Carvalho de Melo
maintainerEm Mon, Dec 03, 2018 at 11:22:00AM +0100, Ingo Molnar escreveu:
Quoted 3 lines
Go over the
tools/files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
Steven, Tzvetomir,
I'm going to split this patch into different subsystems, will have you in the CC list for the libtracecmd ones, so that it becomes easier for you guys to pick these fixes,
Thanks,
- Arnaldo
Quoted 708 lines
( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )No change in functionality intended.
Cc Arnaldo Carvalho de Melo <[email protected]>Cc Peter Zijlstra <[email protected]>Signed-off-by Ingo Molnar <[email protected]>--- tools/lib/subcmd/parse-options.h | 4 +-- tools/lib/traceevent/event-parse.c | 12 ++++----- tools/lib/traceevent/plugin_kvm.c | 2 +- tools/perf/Documentation/perf-list.txt | 2 +- tools/perf/Documentation/perf-report.txt | 2 +- tools/perf/Documentation/perf-stat.txt | 4 +-- tools/perf/arch/x86/tests/insn-x86.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/builtin-trace.c | 2 +- .../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++----- tools/perf/tests/attr.c | 2 +- tools/perf/util/annotate.c | 2 +- tools/perf/util/bpf-loader.c | 2 +- tools/perf/util/header.c | 2 +- tools/perf/util/hist.c | 2 +- tools/perf/util/jitdump.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/probe-event.c | 4 +-- tools/perf/util/sort.c | 2 +- 30 files changed, 62 insertions(+), 62 deletions(-)tools/lib/subcmd/parse-options.h +2
-2@@ -71,7 +71,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `argh`:: * token to explain the kind of argument this option wants. Keep it -* homogenous across the repository. +* homogeneous across the repository. * * `help`:: * the short help associated to what the option does. @@ -80,7 +80,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `flags`:: * mask of parse_opt_option_flags. -* PARSE_OPT_OPTARG: says that the argument is optionnal (not for BOOLEANs) +* PARSE_OPT_OPTARG: says that the argument is optional (not for BOOLEANs) * PARSE_OPT_NOARG: says that this option takes no argument, for CALLBACKs * PARSE_OPT_NONEG: says that this option cannot be negated * PARSE_OPT_HIDDEN this option is skipped in the default usage, showed in tools/lib/traceevent/event-parse.c +6
-6@@ -1145,7 +1145,7 @@ static enum tep_event_type read_token(char **tok) }/** -* tep_read_token - access to utilites to use the pevent parser +* tep_read_token - access to utilities to use the pevent parser * @tok: The token to return * * This will parse tokens from the string given by @@ -3258,7 +3258,7 @@ static int event_read_print(struct tep_event_format *event)* @name: the name of the common field to return * * Returns a common field from the event by the given @name. -* This only searchs the common fields and not all field. +* This only searches the common fields and not all field. */ struct tep_format_field *tep_find_common_field (struct tep_event_format *event,const char *name)@@ -3302,7 +3302,7 @@ tep_find_field(struct tep_event_format *event, const char *name)* @name: the name of the field * * Returns a field by the given @name. -* This searchs the common field names first, then +* This searches the common field names first, then * the non-common ones if a common one was not found. */ struct tep_format_field *@@ -3838,7 +3838,7 @@ static void print_bitmask_to_seq(struct tep_handle *pevent,/* * data points to a bit mask of size bytes. * In the kernel, this is an array of long words, thus -* endianess is very important. +* endianness is very important. */ if (pevent->file_bigendian) index = size - (len +1 );@@ -5313,9 +5313,9 @@ pid_from_cmdlist(struct tep_handle *pevent, const char *comm, struct cmdline *ne* This returns the cmdline structure that holds a pid for a given * comm, or NULL if none found. As there may be more than one pid for * a given comm, the result of this call can be passed back into -* a recurring call in the @next paramater, and then it will find the +* a recurring call in the @next parameter, and then it will find the * next pid. -* Also, it does a linear seach, so it may be slow. +* Also, it does a linear search, so it may be slow. */ struct cmdline *tep_data_pid_from_comm (struct tep_handle *pevent,const char *comm,struct cmdline *next)tools/lib/traceevent/plugin_kvm.c +1
-1@@ -387,7 +387,7 @@ static int kvm_mmu_print_role(struct trace_seq *s, struct tep_record *record,/* * We can only use the structure if file is of the same -* endianess. +* endianness. */ if (tep_is_file_bigendian (event->pevent) ==tep_is_host_bigendian (event->pevent)) {tools/perf/Documentation/perf-list.txt +1
-1@@ -172,7 +172,7 @@ like cycles and instructions and some software events. Other PMUs and global measurements are normally root only. Some event qualifiers, such as "any", are also root only. -This can be overriden by setting the kernel.perf_event_paranoid +This can be overridden by setting the kernel.perf_event_paranoid sysctl to -1, which allows non root to use these events. For accessing trace point events perf needs to have read access totools/perf/Documentation/perf-report.txt +1
-1@@ -244,7 +244,7 @@ OPTIONS Usually more convenient to use --branch-history for this. value can be: - - percent: diplay overhead percent (default) + - percent: display overhead percent (default) - period: display event period - count: display event counttools/perf/Documentation/perf-stat.txt +2
-2@@ -50,7 +50,7 @@ report:: /sys/bus/event_source/devices/<pmu>/format/* Note that the last two syntaxes support prefix and glob matching in - the PMU name to simplify creation of events accross multiple instances + the PMU name to simplify creation of events across multiple instances of the same type of PMU in large systems (e.g. memory controller PMUs). Multiple PMU instances are typical for uncore PMUs, so the prefix 'uncore_' is also ignored when performing this match.@@ -277,7 +277,7 @@ echo 0 > /proc/sys/kernel/nmi_watchdog for best results. Otherwise the bottlenecks may be inconsistent on workload with changing phases. -This enables --metric-only, unless overriden with --no-metric-only. +This enables --metric-only, unless overridden with --no-metric-only. To interpret the results it is usually needed to know on which CPUs the workload runs on. If needed the CPUs can be forced usingtools/perf/arch/x86/tests/insn-x86.c +1
-1@@ -170,7 +170,7 @@ static int test_data_set(struct test_data *dat_set, int x86_64)* * If the test passes %0 is returned, otherwise %-1 is returned. Use the * verbose (-v) option to see all the instructions and whether or not they -* decoded successfuly. +* decoded successfully. */ int test__insn_x86 (struct test *test__maybe_unused ,int subtest__maybe_unused ) {tools/perf/builtin-top.c +1
-1@@ -595,7 +595,7 @@ static void *display_thread_tui(void *arg)/* * Initialize the uid_filter_str, in the future the TUI will allow -* Zooming in/out UIDs. For now juse use whatever the user passed +* Zooming in/out UIDs. For now just use whatever the user passed * via --uid. */ evlist__for_each_entry (top->evlist, pos) {tools/perf/builtin-trace.c +1
-1@@ -2782,7 +2782,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv)* Now that we already used evsel->attr to ask the kernel to setup the * events, lets reuse evsel->attr.sample_max_stack as the limit in * trace__resolve_callchain(), allowing per-event max-stack settings -* to override an explicitely set --max-stack global setting. +* to override an explicitly set --max-stack global setting. */ evlist__for_each_entry (evlist, evsel) { if (evsel__has_callchain(evsel) &&tools/perf/pmu-events/arch/x86/broadwell/cache.json +2
-2@@ -433,7 +433,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",@@ -445,7 +445,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +1
-1@@ -317,7 +317,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "EventCode": "0x87", "Counter": "0,1,2,3", "UMask": "0x1",tools/perf/pmu-events/arch/x86/broadwellde/cache.json +2
-2@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +1
-1@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },tools/perf/pmu-events/arch/x86/broadwellx/cache.json +2
-2@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +1
-1@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },tools/perf/pmu-events/arch/x86/jaketown/cache.json +2
-2@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +1
-1@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",tools/perf/pmu-events/arch/x86/knightslanding/cache.json +15
-15@@ -121,7 +121,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -187,7 +187,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -253,7 +253,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -319,7 +319,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -385,7 +385,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -451,7 +451,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -539,7 +539,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -605,7 +605,7 @@ "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -682,7 +682,7 @@ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -748,7 +748,7 @@ "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -869,7 +869,7 @@ "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -935,7 +935,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -1067,7 +1067,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -1133,7 +1133,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {@@ -1199,7 +1199,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {tools/perf/pmu-events/arch/x86/sandybridge/cache.json +2
-2@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +1
-1@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +6
-6@@ -428,7 +428,7 @@ "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", "UMask": "0x10", "Unit": "CHA" },@@ -967,7 +967,7 @@ "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", "Unit": "M2M" }, {@@ -1041,7 +1041,7 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", "Unit": "UPI LL" },@@ -1051,17 +1051,17 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", "Unit": "UPI LL" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer", + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", "Unit": "UPI LL" },tools/perf/tests/attr.c +1
-1@@ -182,7 +182,7 @@ int test__attr(struct test *test __maybe_unused, int subtest __maybe_unused)char path_perf[PATH_MAX ];char path_dir[PATH_MAX ]; -/* First try developement tree tests. */ +/* First try development tree tests. */ if (!lstat ("./tests" , &st))return run_dir ("./tests" ,"./perf" );tools/perf/util/annotate.c +1
-1@@ -1758,7 +1758,7 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args)while (!feof (file)) {/* * The source code line number (lineno) needs to be kept in -* accross calls to symbol__parse_objdump_line(), so that it +* across calls to symbol__parse_objdump_line(), so that it * can associate it with the instructions till the next one. * See disasm_line__new() and struct disasm_line::line_nr. */ tools/perf/util/bpf-loader.c +1
-1@@ -99,7 +99,7 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source)if (err)return ERR_PTR (-BPF_LOADER_ERRNO__COMPILE ); }else -pr_debug ("bpf: successfull builtin compilation\n" ); +pr_debug ("bpf: successful builtin compilation\n" ); obj =bpf_object__open_buffer (obj_buf, obj_buf_sz, filename);if (!IS_ERR_OR_NULL (obj) && llvm_param.dump_obj)tools/perf/util/header.c +1
-1@@ -2798,7 +2798,7 @@ static int perf_header__adds_write(struct perf_header *header,lseek (fd, sec_start,SEEK_SET );/* * may write more than needed due to dropped feature, but -* this is okay, reader will skip the mising entries +* this is okay, reader will skip the missing entries */ err =do_write (&ff, feat_sec, sec_size);if (err <0 )tools/perf/util/hist.c +1
-1@@ -1160,7 +1160,7 @@ void hist_entry__delete(struct hist_entry *he)/* * If this is not the last column, then we need to pad it according to the -* pre-calculated max lenght for this column, otherwise don't bother adding +* pre-calculated max length for this column, otherwise don't bother adding * spaces because that would break viewing this with, for instance, 'less', * that would show tons of trailing spaces when a long C++ demangled method * names is sampled. tools/perf/util/jitdump.c +1
-1@@ -38,7 +38,7 @@ struct jit_buf_desc {uint64_t sample_type;size_t bufsize;FILE *in; -bool needs_bswap;/* handles cross-endianess */ +bool needs_bswap;/* handles cross-endianness */ bool use_arch_timestamp;void *debug_data;void *unwinding_data;tools/perf/util/machine.c +1
-1@@ -137,7 +137,7 @@ struct machine *machine__new_kallsyms(void)struct machine *machine =machine__new_host ();/* * FIXME: -* 1) We should switch to machine__load_kallsyms(), i.e. not explicitely +* 1) We should switch to machine__load_kallsyms(), i.e. not explicitly * ask for not using the kcore parsing code, once this one is fixed * to create a map per module. */ tools/perf/util/probe-event.c +2
-2@@ -692,7 +692,7 @@ static int add_exec_to_probe_trace_events(struct probe_trace_event *tevs,return ret;for (i =0 ; i < ntevs && ret >=0 ; i++) { -/* point.address is the addres of point.symbol + point.offset */ +/* point.address is the address of point.symbol + point.offset */ tevs[i].point.address -= stext; tevs[i].point.module =strdup (exec);if (!tevs[i].point.module) {@@ -3062,7 +3062,7 @@ static int try_to_find_absolute_address(struct perf_probe_event *pev,/* * Give it a '0x' leading symbol name. * In __add_probe_trace_events, a NULL symbol is interpreted as -* invalud. +* invalid. */ if (asprintf (&tp->symbol,"0x%lx" , tp->address) <0 ) goto errout;tools/perf/util/sort.c +1
-1@@ -36,7 +36,7 @@ enum sort_mode sort__mode = SORT_MODE__NORMAL;* -t, --field-separator * * option, that uses a special separator character and don't pad with spaces, -* replacing all occurances of this separator in symbol names (and other +* replacing all occurrences of this separator in symbol names (and other * output) with a '.' character, that thus it's the only non valid separator. */ static int repsep_snprintf (char *bf,size_t size,const char *fmt, ...)
Signature · 1 line
- Arnaldo
Quoted 10 lines · On Tue, 4 Dec 2018 10:41:22 -0300 Arnaldo Carvalho de Melo <[email protected]>…
Em Mon, Dec 03, 2018 at 11:22:00AM +0100, Ingo Molnar escreveu:
Quoted 3 lines
Go over the
tools/files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.Steven, Tzvetomir,
I'm going to split this patch into different subsystems, will have you in the CC list for the libtracecmd ones, so that it becomes easier for you guys to pick these fixes,
Thanks Arnaldo, much appreciated.
-- Steve
I've let the JSON maintainers know.
-Andi
Arnaldo Carvalho de Melo
maintainerEm Tue, Dec 04, 2018 at 09:16:32AM -0800, Andi Kleen escreveu:
Quoted 2 lines
I've let the JSON maintainers know.
Thanks!
- Arnaldo
tip-bot for Ingo Molnar
merge bot[tip:perf/core] tools lib traceevent: Fix diverse typos in comments
In reply to Ingo Molnartools lib traceevent: Fix diverse typos in comments
Commit-ID: 0dac8c80c833e2f9f09b9d358c51c6359f1d306b Gitweb: https://git.kernel.org/tip/0dac8c80c833e2f9f09b9d358c51c6359f1d306b Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:31 -0300
tools lib traceevent: Fix diverse typos in comments
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Steven Rostedt (VMware) <[email protected]>
Cc Tzvetomir Stoyanov <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/lib/traceevent/event-parse.c | 12 ++++++------ tools/lib/traceevent/plugin_kvm.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-)
tools/lib/traceevent/event-parse.c +6 -6
@@ -1145,7 +1145,7 @@ static enum tep_event_type read_token(char **tok) }/** -* tep_read_token - access to utilites to use the pevent parser +* tep_read_token - access to utilities to use the pevent parser * @tok: The token to return * * This will parse tokens from the string given by
@@ -3258,7 +3258,7 @@ static int event_read_print(struct tep_event *event)* @name: the name of the common field to return * * Returns a common field from the event by the given @name. -* This only searchs the common fields and not all field. +* This only searches the common fields and not all field. */ struct tep_format_field *tep_find_common_field (struct tep_event *event,const char *name)
@@ -3302,7 +3302,7 @@ tep_find_field(struct tep_event *event, const char *name)* @name: the name of the field * * Returns a field by the given @name. -* This searchs the common field names first, then +* This searches the common field names first, then * the non-common ones if a common one was not found. */ struct tep_format_field *
@@ -3841,7 +3841,7 @@ static void print_bitmask_to_seq(struct tep_handle *pevent,/* * data points to a bit mask of size bytes. * In the kernel, this is an array of long words, thus -* endianess is very important. +* endianness is very important. */ if (pevent->file_bigendian) index = size - (len +1 );
@@ -5316,9 +5316,9 @@ pid_from_cmdlist(struct tep_handle *pevent, const char *comm, struct cmdline *ne* This returns the cmdline structure that holds a pid for a given * comm, or NULL if none found. As there may be more than one pid for * a given comm, the result of this call can be passed back into -* a recurring call in the @next paramater, and then it will find the +* a recurring call in the @next parameter, and then it will find the * next pid. -* Also, it does a linear seach, so it may be slow. +* Also, it does a linear search, so it may be slow. */ struct cmdline *tep_data_pid_from_comm (struct tep_handle *pevent,const char *comm,struct cmdline *next)
tools/lib/traceevent/plugin_kvm.c +1 -1
@@ -387,7 +387,7 @@ static int kvm_mmu_print_role(struct trace_seq *s, struct tep_record *record,/* * We can only use the structure if file is of the same -* endianess. +* endianness. */ if (tep_is_file_bigendian (event->pevent) ==tep_is_host_bigendian (event->pevent)) {
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf tools Documentation: Fix diverse typos
In reply to Ingo Molnarperf tools Documentation: Fix diverse typos
Commit-ID: e1eebe9cc3d548a2fbbd97d978d133801a348cc3 Gitweb: https://git.kernel.org/tip/e1eebe9cc3d548a2fbbd97d978d133801a348cc3 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:31 -0300
perf tools Documentation: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
In this particular case, it affects documentation, so may be interesting to cherry pick as it is information that is presented to the user.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/Documentation/perf-list.txt | 2 +- tools/perf/Documentation/perf-report.txt | 2 +- tools/perf/Documentation/perf-stat.txt | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-)
tools/perf/Documentation/perf-list.txt +1 -1
@@ -172,7 +172,7 @@ like cycles and instructions and some software events. Other PMUs and global measurements are normally root only. Some event qualifiers, such as "any", are also root only. -This can be overriden by setting the kernel.perf_event_paranoid +This can be overridden by setting the kernel.perf_event_paranoid sysctl to -1, which allows non root to use these events. For accessing trace point events perf needs to have read access to
tools/perf/Documentation/perf-report.txt +1 -1
@@ -252,7 +252,7 @@ OPTIONS Usually more convenient to use --branch-history for this. value can be: - - percent: diplay overhead percent (default) + - percent: display overhead percent (default) - period: display event period - count: display event count
tools/perf/Documentation/perf-stat.txt +2 -2
@@ -50,7 +50,7 @@ report:: /sys/bus/event_source/devices/<pmu>/format/* Note that the last two syntaxes support prefix and glob matching in - the PMU name to simplify creation of events accross multiple instances + the PMU name to simplify creation of events across multiple instances of the same type of PMU in large systems (e.g. memory controller PMUs). Multiple PMU instances are typical for uncore PMUs, so the prefix 'uncore_' is also ignored when performing this match.
@@ -277,7 +277,7 @@ echo 0 > /proc/sys/kernel/nmi_watchdog for best results. Otherwise the bottlenecks may be inconsistent on workload with changing phases. -This enables --metric-only, unless overriden with --no-metric-only. +This enables --metric-only, unless overridden with --no-metric-only. To interpret the results it is usually needed to know on which CPUs the workload runs on. If needed the CPUs can be forced using
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf bpf-loader: Fix debugging message typo
In reply to Ingo Molnarperf bpf-loader: Fix debugging message typo
Commit-ID: d401b02c41f6afcb8ed32479a016a20cbfd59d6f Gitweb: https://git.kernel.org/tip/d401b02c41f6afcb8ed32479a016a20cbfd59d6f Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:31 -0300
perf bpf-loader: Fix debugging message typo
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
This one has information that is presented to the user, albeit in debug mode.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Wang Nan <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/util/bpf-loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
tools/perf/util/bpf-loader.c +1 -1
@@ -99,7 +99,7 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source)if (err)return ERR_PTR (-BPF_LOADER_ERRNO__COMPILE ); }else -pr_debug ("bpf: successfull builtin compilation\n" ); +pr_debug ("bpf: successful builtin compilation\n" ); obj =bpf_object__open_buffer (obj_buf, obj_buf_sz, filename);if (!IS_ERR_OR_NULL (obj) && llvm_param.dump_obj)
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf vendor events intel: Fix diverse typos
In reply to Ingo Molnarperf vendor events intel: Fix diverse typos
Commit-ID: 9512bca1ede7cba3a718d90db33973c556c69534 Gitweb: https://git.kernel.org/tip/9512bca1ede7cba3a718d90db33973c556c69534 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:30 -0300
perf vendor events intel: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Alexander Shishkin <[email protected]>
Cc Andi Kleen <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Kan Liang <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- .../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++----- 12 files changed, 36 insertions(+), 36 deletions(-)
tools/perf/pmu-events/arch/x86/broadwell/cache.json +2 -2
@@ -433,7 +433,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -445,7 +445,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +1 -1
@@ -317,7 +317,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "EventCode": "0x87", "Counter": "0,1,2,3", "UMask": "0x1",
tools/perf/pmu-events/arch/x86/broadwellde/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/broadwellx/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/jaketown/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/knightslanding/cache.json +15 -15
@@ -121,7 +121,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -187,7 +187,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -253,7 +253,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -319,7 +319,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -385,7 +385,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -451,7 +451,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -539,7 +539,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -605,7 +605,7 @@ "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -682,7 +682,7 @@ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -748,7 +748,7 @@ "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -869,7 +869,7 @@ "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -935,7 +935,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1067,7 +1067,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1133,7 +1133,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1199,7 +1199,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
tools/perf/pmu-events/arch/x86/sandybridge/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +6 -6
@@ -428,7 +428,7 @@ "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", "UMask": "0x10", "Unit": "CHA" },
@@ -967,7 +967,7 @@ "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", "Unit": "M2M" }, {
@@ -1041,7 +1041,7 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", "Unit": "UPI LL" },
@@ -1051,17 +1051,17 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", "Unit": "UPI LL" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer", + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", "Unit": "UPI LL" },
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf tools: Fix diverse comment typos
In reply to Ingo Molnarperf tools: Fix diverse comment typos
Commit-ID: f04ae48fe61a13e3ea63c2761837f646bd1f6980 Gitweb: https://git.kernel.org/tip/f04ae48fe61a13e3ea63c2761837f646bd1f6980 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:31 -0300
perf tools: Fix diverse comment typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry-picking and/or backporting, split this into multiple patches.
Just typos in comments, no need to backport, reducing the possibility of possible backporting artifacts.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/arch/x86/tests/insn-x86.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/builtin-trace.c | 2 +- tools/perf/tests/attr.c | 2 +- tools/perf/util/annotate.c | 2 +- tools/perf/util/header.c | 2 +- tools/perf/util/hist.c | 2 +- tools/perf/util/jitdump.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/probe-event.c | 4 ++-- tools/perf/util/sort.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-)
tools/perf/arch/x86/tests/insn-x86.c +1 -1
@@ -170,7 +170,7 @@ static int test_data_set(struct test_data *dat_set, int x86_64)* * If the test passes %0 is returned, otherwise %-1 is returned. Use the * verbose (-v) option to see all the instructions and whether or not they -* decoded successfuly. +* decoded successfully. */ int test__insn_x86 (struct test *test__maybe_unused ,int subtest__maybe_unused ) {
tools/perf/builtin-top.c +1 -1
@@ -595,7 +595,7 @@ static void *display_thread_tui(void *arg)/* * Initialize the uid_filter_str, in the future the TUI will allow -* Zooming in/out UIDs. For now juse use whatever the user passed +* Zooming in/out UIDs. For now just use whatever the user passed * via --uid. */ evlist__for_each_entry (top->evlist, pos) {
tools/perf/builtin-trace.c +1 -1
@@ -2782,7 +2782,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv)* Now that we already used evsel->attr to ask the kernel to setup the * events, lets reuse evsel->attr.sample_max_stack as the limit in * trace__resolve_callchain(), allowing per-event max-stack settings -* to override an explicitely set --max-stack global setting. +* to override an explicitly set --max-stack global setting. */ evlist__for_each_entry (evlist, evsel) { if (evsel__has_callchain(evsel) &&
tools/perf/tests/attr.c +1 -1
@@ -182,7 +182,7 @@ int test__attr(struct test *test __maybe_unused, int subtest __maybe_unused)char path_perf[PATH_MAX ];char path_dir[PATH_MAX ]; -/* First try developement tree tests. */ +/* First try development tree tests. */ if (!lstat ("./tests" , &st))return run_dir ("./tests" ,"./perf" );
tools/perf/util/annotate.c +1 -1
@@ -1772,7 +1772,7 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args)while (!feof (file)) {/* * The source code line number (lineno) needs to be kept in -* accross calls to symbol__parse_objdump_line(), so that it +* across calls to symbol__parse_objdump_line(), so that it * can associate it with the instructions till the next one. * See disasm_line__new() and struct disasm_line::line_nr. */
tools/perf/util/header.c +1 -1
@@ -2798,7 +2798,7 @@ static int perf_header__adds_write(struct perf_header *header,lseek (fd, sec_start,SEEK_SET );/* * may write more than needed due to dropped feature, but -* this is okay, reader will skip the mising entries +* this is okay, reader will skip the missing entries */ err =do_write (&ff, feat_sec, sec_size);if (err <0 )
tools/perf/util/hist.c +1 -1
@@ -1160,7 +1160,7 @@ void hist_entry__delete(struct hist_entry *he)/* * If this is not the last column, then we need to pad it according to the -* pre-calculated max lenght for this column, otherwise don't bother adding +* pre-calculated max length for this column, otherwise don't bother adding * spaces because that would break viewing this with, for instance, 'less', * that would show tons of trailing spaces when a long C++ demangled method * names is sampled.
tools/perf/util/jitdump.c +1 -1
@@ -38,7 +38,7 @@ struct jit_buf_desc {uint64_t sample_type;size_t bufsize;FILE *in; -bool needs_bswap;/* handles cross-endianess */ +bool needs_bswap;/* handles cross-endianness */ bool use_arch_timestamp;void *debug_data;void *unwinding_data;
tools/perf/util/machine.c +1 -1
@@ -137,7 +137,7 @@ struct machine *machine__new_kallsyms(void)struct machine *machine =machine__new_host ();/* * FIXME: -* 1) We should switch to machine__load_kallsyms(), i.e. not explicitely +* 1) We should switch to machine__load_kallsyms(), i.e. not explicitly * ask for not using the kcore parsing code, once this one is fixed * to create a map per module. */
tools/perf/util/probe-event.c +2 -2
@@ -692,7 +692,7 @@ static int add_exec_to_probe_trace_events(struct probe_trace_event *tevs,return ret;for (i =0 ; i < ntevs && ret >=0 ; i++) { -/* point.address is the addres of point.symbol + point.offset */ +/* point.address is the address of point.symbol + point.offset */ tevs[i].point.address -= stext; tevs[i].point.module =strdup (exec);if (!tevs[i].point.module) {
@@ -3062,7 +3062,7 @@ static int try_to_find_absolute_address(struct perf_probe_event *pev,/* * Give it a '0x' leading symbol name. * In __add_probe_trace_events, a NULL symbol is interpreted as -* invalud. +* invalid. */ if (asprintf (&tp->symbol,"0x%lx" , tp->address) <0 ) goto errout;
tools/perf/util/sort.c +1 -1
@@ -37,7 +37,7 @@ enum sort_mode sort__mode = SORT_MODE__NORMAL;* -t, --field-separator * * option, that uses a special separator character and don't pad with spaces, -* replacing all occurances of this separator in symbol names (and other +* replacing all occurrences of this separator in symbol names (and other * output) with a '.' character, that thus it's the only non valid separator. */ static int repsep_snprintf (char *bf,size_t size,const char *fmt, ...)
tip-bot for Ingo Molnar
merge bot[tip:perf/core] tools lib subcmd: Fix a few source code comment typos
In reply to Ingo Molnartools lib subcmd: Fix a few source code comment typos
Commit-ID: 8cf0fe36de6a02845318a61a58e2d87d309bfc98 Gitweb: https://git.kernel.org/tip/8cf0fe36de6a02845318a61a58e2d87d309bfc98 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Thu, 6 Dec 2018 14:12:31 -0300
tools lib subcmd: Fix a few source code comment typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry-picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Josh Poimboeuf <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/lib/subcmd/parse-options.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
tools/lib/subcmd/parse-options.h +2 -2
@@ -71,7 +71,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `argh`:: * token to explain the kind of argument this option wants. Keep it -* homogenous across the repository. +* homogeneous across the repository. * * `help`:: * the short help associated to what the option does.
@@ -80,7 +80,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `flags`:: * mask of parse_opt_option_flags. -* PARSE_OPT_OPTARG: says that the argument is optionnal (not for BOOLEANs) +* PARSE_OPT_OPTARG: says that the argument is optional (not for BOOLEANs) * PARSE_OPT_NOARG: says that this option takes no argument, for CALLBACKs * PARSE_OPT_NONEG: says that this option cannot be negated * PARSE_OPT_HIDDEN this option is skipped in the default usage, showed in
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf vendor events intel: Fix diverse typos
In reply to Ingo Molnarperf vendor events intel: Fix diverse typos
Commit-ID: b1d6f155e1bbb67778c17aba661fb4ea4e1a3641 Gitweb: https://git.kernel.org/tip/b1d6f155e1bbb67778c17aba661fb4ea4e1a3641 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:31 -0300
perf vendor events intel: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Alexander Shishkin <[email protected]>
Cc Andi Kleen <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Kan Liang <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- .../perf/pmu-events/arch/x86/broadwell/cache.json | 4 +-- .../pmu-events/arch/x86/broadwell/pipeline.json | 2 +- .../pmu-events/arch/x86/broadwellde/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellde/pipeline.json | 2 +- .../perf/pmu-events/arch/x86/broadwellx/cache.json | 4 +-- .../pmu-events/arch/x86/broadwellx/pipeline.json | 2 +- tools/perf/pmu-events/arch/x86/jaketown/cache.json | 4 +-- .../pmu-events/arch/x86/jaketown/pipeline.json | 2 +- .../pmu-events/arch/x86/knightslanding/cache.json | 30 +++++++++++----------- .../pmu-events/arch/x86/sandybridge/cache.json | 4 +-- .../pmu-events/arch/x86/sandybridge/pipeline.json | 2 +- .../pmu-events/arch/x86/skylakex/uncore-other.json | 12 ++++----- 12 files changed, 36 insertions(+), 36 deletions(-)
tools/perf/pmu-events/arch/x86/broadwell/cache.json +2 -2
@@ -433,7 +433,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -445,7 +445,7 @@ }, { "PEBS": "1", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +1 -1
@@ -317,7 +317,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "EventCode": "0x87", "Counter": "0,1,2,3", "UMask": "0x1",
tools/perf/pmu-events/arch/x86/broadwellde/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/broadwellx/cache.json +2 -2
@@ -439,7 +439,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "CounterHTOff": "0,1,2,3" },
@@ -451,7 +451,7 @@ "PEBS": "1", "Counter": "0,1,2,3", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "SampleAfterValue": "100003", "L1_Hit_Indication": "1", "CounterHTOff": "0,1,2,3"
tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +1 -1
@@ -322,7 +322,7 @@ "BriefDescription": "Stalls caused by changing prefix length of the instruction.", "Counter": "0,1,2,3", "EventName": "ILD_STALL.LCP", - "PublicDescription": "This event counts stalls occured due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", + "PublicDescription": "This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.", "SampleAfterValue": "2000003", "CounterHTOff": "0,1,2,3,4,5,6,7" },
tools/perf/pmu-events/arch/x86/jaketown/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/knightslanding/cache.json +15 -15
@@ -121,7 +121,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Prefetch requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -187,7 +187,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any Read request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -253,7 +253,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand code reads and prefetch code read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -319,7 +319,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data write requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -385,7 +385,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data and L1 prefetch data read requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -451,7 +451,7 @@ "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts any request that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -539,7 +539,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L1 data HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -605,7 +605,7 @@ "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Software Prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -682,7 +682,7 @@ "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Bus locks and split lock requests that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -748,7 +748,7 @@ "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts UC code reads (valid only for Outstanding response type) that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -869,7 +869,7 @@ "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Partial reads (UC or WC and is valid only for Outstanding response type). that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -935,7 +935,7 @@ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts L2 code HW prefetches that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1067,7 +1067,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand code reads and prefetch code reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1133,7 +1133,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts Demand cacheable data writes that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
@@ -1199,7 +1199,7 @@ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", "SampleAfterValue": "100007", - "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The oustanding response should be programmed only on PMC0. ", + "BriefDescription": "Counts demand cacheable data and L1 prefetch data reads that are outstanding, per weighted cycle, from the time of the request to when any response is received. The outstanding response should be programmed only on PMC0. ", "Offcore": "1" }, {
tools/perf/pmu-events/arch/x86/sandybridge/cache.json +2 -2
@@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41",
@@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42",
tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +1 -1
@@ -778,7 +778,7 @@ "CounterHTOff": "0,1,2,3,4,5,6,7" }, { - "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceeding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", + "PublicDescription": "This event counts loads that followed a store to the same address, where the data could not be forwarded inside the pipeline from the store to the load. The most common reason why store forwarding would be blocked is when a load's address range overlaps with a preceding smaller uncompleted store. See the table of not supported store forwards in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. The penalty for blocked store forwarding is that the load must wait for the store to complete before it can be issued.", "EventCode": "0x03", "Counter": "0,1,2,3", "UMask": "0x2",
tools/perf/pmu-events/arch/x86/skylakex/uncore-other.json +6 -6
@@ -428,7 +428,7 @@ "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", - "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This reponse will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", + "PublicDescription": "Counts when a transaction with the opcode type Rsp*WB Snoop Response was received which indicates which indicates the data was written back to it's home. This is returned when a non-RFO request hits a cacheline in the Modified state. The Cache can either downgrade the cacheline to a S (Shared) or I (Invalid) state depending on how the system has been configured. This response will also be sent when a cache requests E (Exclusive) ownership of a cache line without receiving data, because the cache must acquire ownership.", "UMask": "0x10", "Unit": "CHA" },
@@ -967,7 +967,7 @@ "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", - "PublicDescription": "Counts when the M2M (Mesh to Memory) recieves a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", + "PublicDescription": "Counts when the M2M (Mesh to Memory) receives a prefetch request and inserts it into its outstanding prefetch queue. Explanatory Side Note: the prefect queue is made from CAM: Content Addressable Memory", "Unit": "M2M" }, {
@@ -1041,7 +1041,7 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot0 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", "Unit": "UPI LL" },
@@ -1051,17 +1051,17 @@ "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot1 RxQ buffer (Receive Queue) and passed directly across the BGF and into the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", "Unit": "UPI LL" }, { - "BriefDescription": "FLITs received which bypassed the Slot0 Recieve Buffer", + "BriefDescription": "FLITs received which bypassed the Slot0 Receive Buffer", "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", - "PublicDescription": "Counts incoming FLITs (FLow control unITs) whcih bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", + "PublicDescription": "Counts incoming FLITs (FLow control unITs) which bypassed the slot2 RxQ buffer (Receive Queue) and passed directly to the Egress. This is a latency optimization, and should generally be the common case. If this value is less than the number of FLITs transferred, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", "Unit": "UPI LL" },
tip-bot for Ingo Molnar
merge bot[tip:perf/core] tools lib traceevent: Fix diverse typos in comments
In reply to Ingo Molnartools lib traceevent: Fix diverse typos in comments
Commit-ID: 3e449f7c36c3ac49f140b5dc3c40693e551f47d2 Gitweb: https://git.kernel.org/tip/3e449f7c36c3ac49f140b5dc3c40693e551f47d2 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:34 -0300
tools lib traceevent: Fix diverse typos in comments
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Steven Rostedt (VMware) <[email protected]>
Cc Tzvetomir Stoyanov <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/lib/traceevent/event-parse.c | 12 ++++++------ tools/lib/traceevent/plugin_kvm.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-)
tools/lib/traceevent/event-parse.c +6 -6
@@ -1145,7 +1145,7 @@ static enum tep_event_type read_token(char **tok) }/** -* tep_read_token - access to utilites to use the pevent parser +* tep_read_token - access to utilities to use the pevent parser * @tok: The token to return * * This will parse tokens from the string given by
@@ -3258,7 +3258,7 @@ static int event_read_print(struct tep_event *event)* @name: the name of the common field to return * * Returns a common field from the event by the given @name. -* This only searchs the common fields and not all field. +* This only searches the common fields and not all field. */ struct tep_format_field *tep_find_common_field (struct tep_event *event,const char *name)
@@ -3302,7 +3302,7 @@ tep_find_field(struct tep_event *event, const char *name)* @name: the name of the field * * Returns a field by the given @name. -* This searchs the common field names first, then +* This searches the common field names first, then * the non-common ones if a common one was not found. */ struct tep_format_field *
@@ -3841,7 +3841,7 @@ static void print_bitmask_to_seq(struct tep_handle *pevent,/* * data points to a bit mask of size bytes. * In the kernel, this is an array of long words, thus -* endianess is very important. +* endianness is very important. */ if (pevent->file_bigendian) index = size - (len +1 );
@@ -5316,9 +5316,9 @@ pid_from_cmdlist(struct tep_handle *pevent, const char *comm, struct cmdline *ne* This returns the cmdline structure that holds a pid for a given * comm, or NULL if none found. As there may be more than one pid for * a given comm, the result of this call can be passed back into -* a recurring call in the @next paramater, and then it will find the +* a recurring call in the @next parameter, and then it will find the * next pid. -* Also, it does a linear seach, so it may be slow. +* Also, it does a linear search, so it may be slow. */ struct cmdline *tep_data_pid_from_comm (struct tep_handle *pevent,const char *comm,struct cmdline *next)
tools/lib/traceevent/plugin_kvm.c +1 -1
@@ -387,7 +387,7 @@ static int kvm_mmu_print_role(struct trace_seq *s, struct tep_record *record,/* * We can only use the structure if file is of the same -* endianess. +* endianness. */ if (tep_is_file_bigendian (event->pevent) ==tep_is_host_bigendian (event->pevent)) {
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf tools Documentation: Fix diverse typos
In reply to Ingo Molnarperf tools Documentation: Fix diverse typos
Commit-ID: 1a7ea3283f7d15d7ce76a30870c3ca648adf1fc4 Gitweb: https://git.kernel.org/tip/1a7ea3283f7d15d7ce76a30870c3ca648adf1fc4 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:36 -0300
perf tools Documentation: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
In this particular case, it affects documentation, so may be interesting to cherry pick as it is information that is presented to the user.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/Documentation/perf-list.txt | 2 +- tools/perf/Documentation/perf-report.txt | 2 +- tools/perf/Documentation/perf-stat.txt | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-)
tools/perf/Documentation/perf-list.txt +1 -1
@@ -172,7 +172,7 @@ like cycles and instructions and some software events. Other PMUs and global measurements are normally root only. Some event qualifiers, such as "any", are also root only. -This can be overriden by setting the kernel.perf_event_paranoid +This can be overridden by setting the kernel.perf_event_paranoid sysctl to -1, which allows non root to use these events. For accessing trace point events perf needs to have read access to
tools/perf/Documentation/perf-report.txt +1 -1
@@ -252,7 +252,7 @@ OPTIONS Usually more convenient to use --branch-history for this. value can be: - - percent: diplay overhead percent (default) + - percent: display overhead percent (default) - period: display event period - count: display event count
tools/perf/Documentation/perf-stat.txt +2 -2
@@ -50,7 +50,7 @@ report:: /sys/bus/event_source/devices/<pmu>/format/* Note that the last two syntaxes support prefix and glob matching in - the PMU name to simplify creation of events accross multiple instances + the PMU name to simplify creation of events across multiple instances of the same type of PMU in large systems (e.g. memory controller PMUs). Multiple PMU instances are typical for uncore PMUs, so the prefix 'uncore_' is also ignored when performing this match.
@@ -277,7 +277,7 @@ echo 0 > /proc/sys/kernel/nmi_watchdog for best results. Otherwise the bottlenecks may be inconsistent on workload with changing phases. -This enables --metric-only, unless overriden with --no-metric-only. +This enables --metric-only, unless overridden with --no-metric-only. To interpret the results it is usually needed to know on which CPUs the workload runs on. If needed the CPUs can be forced using
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf bpf-loader: Fix debugging message typo
In reply to Ingo Molnarperf bpf-loader: Fix debugging message typo
Commit-ID: e4a8b0af5121392da2d40204ee330fd9e88d0858 Gitweb: https://git.kernel.org/tip/e4a8b0af5121392da2d40204ee330fd9e88d0858 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:39 -0300
perf bpf-loader: Fix debugging message typo
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry picking and/or backporting, split this into multiple patches.
This one has information that is presented to the user, albeit in debug mode.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Wang Nan <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/util/bpf-loader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
tools/perf/util/bpf-loader.c +1 -1
@@ -99,7 +99,7 @@ struct bpf_object *bpf__prepare_load(const char *filename, bool source)if (err)return ERR_PTR (-BPF_LOADER_ERRNO__COMPILE ); }else -pr_debug ("bpf: successfull builtin compilation\n" ); +pr_debug ("bpf: successful builtin compilation\n" ); obj =bpf_object__open_buffer (obj_buf, obj_buf_sz, filename);if (!IS_ERR_OR_NULL (obj) && llvm_param.dump_obj)
tip-bot for Ingo Molnar
merge bot[tip:perf/core] perf tools: Fix diverse comment typos
In reply to Ingo Molnarperf tools: Fix diverse comment typos
Commit-ID: adba163441597ffb56141233a2ef722b75caca87 Gitweb: https://git.kernel.org/tip/adba163441597ffb56141233a2ef722b75caca87 Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:47 -0300
perf tools: Fix diverse comment typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry-picking and/or backporting, split this into multiple patches.
Just typos in comments, no need to backport, reducing the possibility of possible backporting artifacts.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/perf/arch/x86/tests/insn-x86.c | 2 +- tools/perf/builtin-top.c | 2 +- tools/perf/builtin-trace.c | 2 +- tools/perf/tests/attr.c | 2 +- tools/perf/util/annotate.c | 2 +- tools/perf/util/header.c | 2 +- tools/perf/util/hist.c | 2 +- tools/perf/util/jitdump.c | 2 +- tools/perf/util/machine.c | 2 +- tools/perf/util/probe-event.c | 4 ++-- tools/perf/util/sort.c | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-)
tools/perf/arch/x86/tests/insn-x86.c +1 -1
@@ -170,7 +170,7 @@ static int test_data_set(struct test_data *dat_set, int x86_64)* * If the test passes %0 is returned, otherwise %-1 is returned. Use the * verbose (-v) option to see all the instructions and whether or not they -* decoded successfuly. +* decoded successfully. */ int test__insn_x86 (struct test *test__maybe_unused ,int subtest__maybe_unused ) {
tools/perf/builtin-top.c +1 -1
@@ -595,7 +595,7 @@ static void *display_thread_tui(void *arg)/* * Initialize the uid_filter_str, in the future the TUI will allow -* Zooming in/out UIDs. For now juse use whatever the user passed +* Zooming in/out UIDs. For now just use whatever the user passed * via --uid. */ evlist__for_each_entry (top->evlist, pos) {
tools/perf/builtin-trace.c +1 -1
@@ -2782,7 +2782,7 @@ static int trace__run(struct trace *trace, int argc, const char **argv)* Now that we already used evsel->attr to ask the kernel to setup the * events, lets reuse evsel->attr.sample_max_stack as the limit in * trace__resolve_callchain(), allowing per-event max-stack settings -* to override an explicitely set --max-stack global setting. +* to override an explicitly set --max-stack global setting. */ evlist__for_each_entry (evlist, evsel) { if (evsel__has_callchain(evsel) &&
tools/perf/tests/attr.c +1 -1
@@ -182,7 +182,7 @@ int test__attr(struct test *test __maybe_unused, int subtest __maybe_unused)char path_perf[PATH_MAX ];char path_dir[PATH_MAX ]; -/* First try developement tree tests. */ +/* First try development tree tests. */ if (!lstat ("./tests" , &st))return run_dir ("./tests" ,"./perf" );
tools/perf/util/annotate.c +1 -1
@@ -1772,7 +1772,7 @@ static int symbol__disassemble(struct symbol *sym, struct annotate_args *args)while (!feof (file)) {/* * The source code line number (lineno) needs to be kept in -* accross calls to symbol__parse_objdump_line(), so that it +* across calls to symbol__parse_objdump_line(), so that it * can associate it with the instructions till the next one. * See disasm_line__new() and struct disasm_line::line_nr. */
tools/perf/util/header.c +1 -1
@@ -2798,7 +2798,7 @@ static int perf_header__adds_write(struct perf_header *header,lseek (fd, sec_start,SEEK_SET );/* * may write more than needed due to dropped feature, but -* this is okay, reader will skip the mising entries +* this is okay, reader will skip the missing entries */ err =do_write (&ff, feat_sec, sec_size);if (err <0 )
tools/perf/util/hist.c +1 -1
@@ -1160,7 +1160,7 @@ void hist_entry__delete(struct hist_entry *he)/* * If this is not the last column, then we need to pad it according to the -* pre-calculated max lenght for this column, otherwise don't bother adding +* pre-calculated max length for this column, otherwise don't bother adding * spaces because that would break viewing this with, for instance, 'less', * that would show tons of trailing spaces when a long C++ demangled method * names is sampled.
tools/perf/util/jitdump.c +1 -1
@@ -38,7 +38,7 @@ struct jit_buf_desc {uint64_t sample_type;size_t bufsize;FILE *in; -bool needs_bswap;/* handles cross-endianess */ +bool needs_bswap;/* handles cross-endianness */ bool use_arch_timestamp;void *debug_data;void *unwinding_data;
tools/perf/util/machine.c +1 -1
@@ -137,7 +137,7 @@ struct machine *machine__new_kallsyms(void)struct machine *machine =machine__new_host ();/* * FIXME: -* 1) We should switch to machine__load_kallsyms(), i.e. not explicitely +* 1) We should switch to machine__load_kallsyms(), i.e. not explicitly * ask for not using the kcore parsing code, once this one is fixed * to create a map per module. */
tools/perf/util/probe-event.c +2 -2
@@ -692,7 +692,7 @@ static int add_exec_to_probe_trace_events(struct probe_trace_event *tevs,return ret;for (i =0 ; i < ntevs && ret >=0 ; i++) { -/* point.address is the addres of point.symbol + point.offset */ +/* point.address is the address of point.symbol + point.offset */ tevs[i].point.address -= stext; tevs[i].point.module =strdup (exec);if (!tevs[i].point.module) {
@@ -3062,7 +3062,7 @@ static int try_to_find_absolute_address(struct perf_probe_event *pev,/* * Give it a '0x' leading symbol name. * In __add_probe_trace_events, a NULL symbol is interpreted as -* invalud. +* invalid. */ if (asprintf (&tp->symbol,"0x%lx" , tp->address) <0 ) goto errout;
tools/perf/util/sort.c +1 -1
@@ -37,7 +37,7 @@ enum sort_mode sort__mode = SORT_MODE__NORMAL;* -t, --field-separator * * option, that uses a special separator character and don't pad with spaces, -* replacing all occurances of this separator in symbol names (and other +* replacing all occurrences of this separator in symbol names (and other * output) with a '.' character, that thus it's the only non valid separator. */ static int repsep_snprintf (char *bf,size_t size,const char *fmt, ...)
tip-bot for Ingo Molnar
merge bot[tip:perf/core] tools lib subcmd: Fix a few source code comment typos
In reply to Ingo Molnartools lib subcmd: Fix a few source code comment typos
Commit-ID: 65c9fee2da2fbbedbba402996ddb412072e762fc Gitweb: https://git.kernel.org/tip/65c9fee2da2fbbedbba402996ddb412072e762fc Author: Ingo Molnar <[email protected]> AuthorDate: Mon, 3 Dec 2018 11:22:00 +0100 Committer: Arnaldo Carvalho de Melo <[email protected]> CommitDate: Mon, 17 Dec 2018 14:56:51 -0300
tools lib subcmd: Fix a few source code comment typos
Go over the tools/ files that are maintained in Arnaldo's tree and fix common typos: half of them were in comments, the other half in JSON files.
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is, additionally, maintained outside the kernel tree, so to ease cherry-picking and/or backporting, split this into multiple patches.
Signed-off-by Ingo Molnar <[email protected]>
Cc Jiri Olsa <[email protected]>
Cc Josh Poimboeuf <[email protected]>
Cc Namhyung Kim <[email protected]>
Cc Peter Zijlstra <[email protected]>
Signed-off-by Arnaldo Carvalho de Melo <[email protected]>
--- tools/lib/subcmd/parse-options.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
tools/lib/subcmd/parse-options.h +2 -2
@@ -71,7 +71,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `argh`:: * token to explain the kind of argument this option wants. Keep it -* homogenous across the repository. +* homogeneous across the repository. * * `help`:: * the short help associated to what the option does.
@@ -80,7 +80,7 @@ typedef int parse_opt_cb(const struct option *, const char *arg, int unset);* * `flags`:: * mask of parse_opt_option_flags. -* PARSE_OPT_OPTARG: says that the argument is optionnal (not for BOOLEANs) +* PARSE_OPT_OPTARG: says that the argument is optional (not for BOOLEANs) * PARSE_OPT_NOARG: says that this option takes no argument, for CALLBACKs * PARSE_OPT_NONEG: says that this option cannot be negated * PARSE_OPT_HIDDEN this option is skipped in the default usage, showed in