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Don't enable CONFIG_SPL_DM_USB for non-DM SPL

PATCH Superseded Martyn Welch 3 participants 6 messages Dec 3, 2018 – Dec 10, 2018

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#0 lore raw

PATCH v3 1/3 Don't enable CONFIG_SPL_DM_USB for non-DM SPL

When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.

This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.

Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.

---

Changes in v3:
- New in v3

Changes in v2: None

 drivers/usb/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/usb/Kconfig +1 -1
index 03746dd12f..a46ce42bf1 100644
@@ -49,7 +49,7 @@ config DM_USB
 
 config SPL_DM_USB
 	bool "Enable driver model for USB in SPL"
-	depends on DM_USB
+	depends on SPL_DM && DM_USB
 	default y
 
 source "drivers/usb/host/Kconfig"
Signature · 1 line
2.19.2
#1 lore raw

PATCH v3 2/3 Enable FEC driver to retrieve PHY address from device tree

Currently if we have more than one phy on the MDIO bus, we do not have a good mechanism for determining which should be used at runtime. Enable the FEC driver to determine the address for the PHY from the device tree.

---

Changes in v3:
- No changes in v3

Changes in v2:
- New in v2

 drivers/net/fec_mxc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/net/fec_mxc.c +21 -0
index 99c5c649a0..425f6197cb 100644
@@ -1264,11 +1264,32 @@ static const struct eth_ops fecmxc_ops = {
 	.read_rom_hwaddr	= fecmxc_read_rom_hwaddr,
 };
 
+static int device_get_phy_addr(struct udevice *dev)
+{
+	struct ofnode_phandle_args phandle_args;
+	int reg;
+
+	if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+				       &phandle_args)) {
+		debug("Failed to find phy-handle");
+		return -ENODEV;
+	}
+
+	reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
+
+	return reg;
+}
+
 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
 {
 	struct phy_device *phydev;
+	int addr;
 	int mask = 0xffffffff;
 
+	addr = device_get_phy_addr(dev);
+	if (addr >= 0)
+		mask = 1 << addr;
+
 #ifdef CONFIG_FEC_MXC_PHYADDR
 	mask = 1 << CONFIG_FEC_MXC_PHYADDR;
 #endif
Signature · 1 line
2.19.2
#2 lore raw

PATCH v3 3/3 imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

In reply to Martyn Welch

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). This port provides both SPL and DCD based boot options (hence the two defconfigs).

CPU:   Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU:   Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   FSL_SDHC: 0
In:    serial
Out:   serial
Err:   serial
Net:   FEC0

Working:
- Eth0
- i2C
- MMC/SD
- NAND
- UART (1 & 5)
- USB (host & otg)

---

Changes in v3:
- Correct spelling of Phytec
- Remove unneeded license information
- Correct image name in documentation
- Correct whitespacing
- Enable SPL to boot from MMC
- Simplify defconfig

Changes in v2:
- Switch to driver model

 arch/arm/dts/Makefile                 |   3 +-
 arch/arm/dts/imx6ul-pcl063.dtsi       | 173 +++++++++++++++++++++
 arch/arm/dts/imx6ul-phycore-segin.dts |  76 ++++++++++
 arch/arm/mach-imx/mx6/Kconfig         |  13 ++
 board/phytec/pcl063/Kconfig           |  12 ++
 board/phytec/pcl063/MAINTAINERS       |   8 +
 board/phytec/pcl063/Makefile          |   7 +
 board/phytec/pcl063/README            |  26 ++++
 board/phytec/pcl063/pcl063.c          | 206 ++++++++++++++++++++++++++
 board/phytec/pcl063/spl.c             | 160 ++++++++++++++++++++
 configs/phycore_pcl063_defconfig      |  61 ++++++++
 include/configs/pcl063.h              | 100 +++++++++++++
 12 files changed, 844 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx6ul-pcl063.dtsi
 create mode 100644 arch/arm/dts/imx6ul-phycore-segin.dts
 create mode 100644 board/phytec/pcl063/Kconfig
 create mode 100644 board/phytec/pcl063/MAINTAINERS
 create mode 100644 board/phytec/pcl063/Makefile
 create mode 100644 board/phytec/pcl063/README
 create mode 100644 board/phytec/pcl063/pcl063.c
 create mode 100644 board/phytec/pcl063/spl.c
 create mode 100644 configs/phycore_pcl063_defconfig
 create mode 100644 include/configs/pcl063.h
arch/arm/dts/Makefile +2 -1
index d8be3a30dc..942d805698 100644
@@ -450,7 +450,8 @@ dtb-$(CONFIG_MX6UL) += \
 	imx6ul-isiot-nand.dtb \
 	imx6ul-opos6uldev.dtb \
 	imx6ul-14x14-evk.dtb \
-	imx6ul-9x9-evk.dtb
+	imx6ul-9x9-evk.dtb \
+	imx6ul-phycore-segin.dtb
 
 dtb-$(CONFIG_MX6ULL) += imx6ull-14x14-evk.dtb
 
arch/arm/dts/imx6ul-pcl063.dtsi new file +173 -0

173 lines not on this page · raw message

arch/arm/dts/imx6ul-phycore-segin.dts new file +76 -0

76 lines not on this page · raw message

arch/arm/mach-imx/mx6/Kconfig +13 -0
index 06c25bae36..e253f495c5 100644
@@ -428,6 +428,18 @@ config TARGET_PFLA02
 	select MX6QDL
 	select SUPPORT_SPL
 
+config TARGET_PCL063
+	bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
+	select MX6UL
+	select DM
+	select DM_ETH
+	select DM_GPIO
+	select DM_I2C
+	select DM_MMC
+	select DM_SERIAL
+	select DM_THERMAL
+	select SUPPORT_SPL
+
 config TARGET_SECOMX6
 	bool "secomx6 boards"
 
@@ -550,6 +562,7 @@ source "board/freescale/mx6ullevk/Kconfig"
 source "board/grinn/liteboard/Kconfig"
 source "board/phytec/pcm058/Kconfig"
 source "board/phytec/pfla02/Kconfig"
+source "board/phytec/pcl063/Kconfig"
 source "board/gateworks/gw_ventana/Kconfig"
 source "board/kosagi/novena/Kconfig"
 source "board/samtec/vining_2000/Kconfig"
board/phytec/pcl063/Kconfig new file +12 -0
new file mode 100644
index 0000000000..977db70f64
@@ -0,0 +1,12 @@
+if TARGET_PCL063
+
+config SYS_BOARD
+	default "pcl063"
+
+config SYS_VENDOR
+	default "phytec"
+
+config SYS_CONFIG_NAME
+	default "pcl063"
+
+endif
board/phytec/pcl063/MAINTAINERS new file +8 -0
new file mode 100644
index 0000000000..c65a951f3d
@@ -0,0 +1,8 @@
+PCL063 BOARD
+M:	Martyn Welch <[email protected]>
+S:	Maintained
+F:	arch/arm/dts/imx6ul-pcl063.dtsi
+F:	arch/arm/dts/imx6ul-phycore-segin.dts
+F:	board/phytec/pcl063/
+F:	configs/phycore_pcl063_defconfig
+F:	include/configs/pcl063.h
board/phytec/pcl063/Makefile new file +7 -0
new file mode 100644
index 0000000000..53c73c9b08
@@ -0,0 +1,7 @@
+# Copyright (C) 2018 Collabora Ltd.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := pcl063.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
board/phytec/pcl063/README new file +26 -0
new file mode 100644
index 0000000000..be83bdb0d8
@@ -0,0 +1,26 @@
+How to use U-Boot on PHYTEC phyBOARD-i.MX6UL-Segin
+--------------------------------------------------
+
+- Configure and build U-Boot for phyCORE-i.MX6UL:
+
+    $ make mrproper
+    $ make phycore_pcl063_defconfig
+    $ make
+
+  This will generate SPL and u-boot-dtb.img images.
+
+- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
+
+    $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
+    $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
+
+- Jumper settings:
+
+  JP1:   Open: Boot from NAND
+       Closed: Boot from SD/MMC1
+
+- Connect the Serial cable to UART0 and the PC for the console.
+
+- Insert the micro SD card in the board and power it up.
+
+- U-Boot messages should come up.
board/phytec/pcl063/pcl063.c new file +206 -0

206 lines not on this page · raw message

board/phytec/pcl063/spl.c new file +160 -0

160 lines not on this page · raw message

configs/phycore_pcl063_defconfig new file +61 -0

61 lines not on this page · raw message

include/configs/pcl063.h new file +100 -0

100 lines not on this page · raw message

Signature · 1 line
2.19.2
#3 lore raw

PATCH v3 1/3 Don't enable CONFIG_SPL_DM_USB for non-DM SPL

In reply to Martyn Welch
Quoted 10 lines · Martyn Welch

When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.

This leads to unexpected and confusing failures when building a DM based U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.

Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.

It looks OK, but I don't see Sven on CC and I don't see 2/3 and 3/3.

Signature · 2 lines
Best regards,
Marek Vasut
#4 lore raw

PATCH v3 1/3 Don't enable CONFIG_SPL_DM_USB for non-DM SPL

Quoted 9 lines · Marek Vasut
Quoted 8 lines · Martyn Welch

When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.

This leads to unexpected and confusing failures when building a DM based
U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.

Quoted 7 lines
Quoted 4 lines

Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.

It looks OK, but I don't see Sven on CC and I don't see 2/3 and 3/3.

My mistake, trying to get used to patman. I'll resend and ensure you and Sven are CCed on all 3 patches.

Martyn

#5 lore raw

PATCH v3 1/3 Don't enable CONFIG_SPL_DM_USB for non-DM SPL

Quoted 13 lines · Martyn Welch
Quoted 12 lines · Marek Vasut
Quoted 11 lines · Martyn Welch

When CONFIG_SPL_DM_USB was added, it was added defaulted on without protection to ensure it didn't get set for non-DM SPL builds.

This leads to unexpected and confusing failures when building a DM based
U-Boot but with a non-DM SPL, as the defconfig is unlikely to have CONFIG_SPL_DM_USB actively disabled.

Tweak the Kconfig to not enable this setting unless CONFIG_SPL_DM is set.

Quoted 7 lines
Quoted 4 lines
Quoted 1 line

It looks OK, but I don't see Sven on CC and I don't see 2/3 and 3/3.

My mistake, trying to get used to patman. I'll resend and ensure you and Sven are CCed on all 3 patches.

Thanks!

Signature · 2 lines
Best regards,
Marek Vasut