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clk: socfpga: stratix10: fix rate calculation for pll clocks

PATCH Applied Dinh Nguyen 2 participants 2 messages Dec 18, 2018 – Jan 11, 2019

Subsystems (2)
Common clk Arm/socfpga clock framework support
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Dinh Nguyen

author maintainer
#0 lore raw

PATCH 1/1 clk: socfpga: stratix10: fix rate calculation for pll clocks

The main PLL calculation has a mistake. We should be using the multiplying the VCO frequency, not the parent clock frequency.

Fixes 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for

Stratix10 platform")

Cc [email protected]
Signed-off-by Dinh Nguyen <[email protected]>
---
 drivers/clk/socfpga/clk-pll-s10.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/clk/socfpga/clk-pll-s10.c +1 -1
index 2d5d8b43727e..c4d0b6f6abf2 100644
@@ -43,7 +43,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
 	/* Read mdiv and fdiv from the fdbck register */
 	reg = readl(socfpgaclk->hw.reg + 0x4);
 	mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT;
-	vco_freq = (unsigned long long)parent_rate * (mdiv + 6);
+	vco_freq = (unsigned long long)vco_freq * (mdiv + 6);
 
 	return (unsigned long)vco_freq;
 }
Signature · 1 line
2.20.0
maintainer Applied
#1 lore raw

Quoting Dinh Nguyen (2018-12-17 16:06:14)

Quoted 8 lines

The main PLL calculation has a mistake. We should be using the multiplying the VCO frequency, not the parent clock frequency.

Fixes 07afb8db7340 ("clk: socfpga: stratix10: add clock driver for

Stratix10 platform")

Cc [email protected]
Signed-off-by Dinh Nguyen <[email protected]>

---

Applied to clk-fixes