Heterogeneuos memory node attributes
Subsystems (11)
v4 cover Heterogeneuos memory node attributes
The series seems quite calm now. I've received some approvals of the on the proposal, and heard no objections on the new core interfaces.
Please let me know if there is anyone or group of people I should request and wait for a review. And if anyone reading this would like additional time as well before I post a potentially subsequent version, please let me know.
I also wanted to inquire on upstream strategy if/when all desired reviews are received. The series is spanning a few subsystems, so I'm not sure who's tree is the best candidate. I could see an argument for driver-core, acpi, or mm as possible paths. Please let me know if there's a more appropriate option or any other gating concerns.
== Changes from v3 ==
I've fixed the documentation issues that have been raised for v3
Moved the hmat files according to Rafael's recommendation
Added received Reviewed-by's
Otherwise this v4 is much the same as v3.
== Background ==
Platforms may provide multiple types of cpu attached system memory. The memory ranges for each type may have different characteristics that applications may wish to know about when considering what node they want their memory allocated from.
It had previously been difficult to describe these setups as memory rangers were generally lumped into the NUMA node of the CPUs. New platform attributes have been created and in use today that describe the more complex memory hierarchies that can be created.
This series' objective is to provide the attributes from such systems that are useful for applications to know about, and readily usable with existing tools and libraries.
Keith Busch (13):
acpi: Create subtable parsing infrastructure
acpi: Add HMAT to generic parsing tables acpi/hmat: Parse and report heterogeneous memory
node: Link memory nodes to their compute nodes Documentation/ABI: Add new node sysfs attributes acpi/hmat: Register processor domain to its memory
node: Add heterogenous memory access attributes Documentation/ABI: Add node performance attributes acpi/hmat: Register performance attributes
node: Add memory caching attributes Documentation/ABI: Add node cache attributes acpi/hmat: Register memory side cache attributes doc/mm: New documentation for memory performance
Documentation/ABI/stable/sysfs-devices-node | 87 +++++- Documentation/admin-guide/mm/numaperf.rst | 184 +++++++++++++ arch/arm64/kernel/acpi_numa.c | 2 +- arch/arm64/kernel/smp.c | 4 +- arch/ia64/kernel/acpi.c | 12 +- arch/x86/kernel/acpi/boot.c | 36 +-- drivers/acpi/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/hmat/Kconfig | 9 + drivers/acpi/hmat/Makefile | 1 + drivers/acpi/hmat/hmat.c | 375 ++++++++++++++++++++++++++ drivers/acpi/numa.c | 16 +- drivers/acpi/scan.c | 4 +- drivers/acpi/tables.c | 76 +++++- drivers/base/Kconfig | 8 + drivers/base/node.c | 317 +++++++++++++++++++++- drivers/irqchip/irq-gic-v2m.c | 2 +- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its.c | 6 +- drivers/irqchip/irq-gic-v3.c | 10 +- drivers/irqchip/irq-gic.c | 4 +- drivers/mailbox/pcc.c | 2 +- include/linux/acpi.h | 6 +- include/linux/node.h | 70 ++++- 25 files changed, 1172 insertions(+), 65 deletions(-) create mode 100644 Documentation/admin-guide/mm/numaperf.rst create mode 100644 drivers/acpi/hmat/Kconfig create mode 100644 drivers/acpi/hmat/Makefile create mode 100644 drivers/acpi/hmat/hmat.c
Signature · 1 line
2.14.4
PATCH v4 1/13 acpi: Create subtable parsing infrastructure
Parsing entries in an ACPI table had assumed a generic header structure. There is no standard ACPI header, though, so less common layouts with different field sizes required custom parsers to go through their subtable entry list.
Create the infrastructure for adding different table types so parsing the entries array may be more reused for all ACPI system tables and the common code doesn't need to be duplicated.
--- arch/arm64/kernel/acpi_numa.c | 2 +- arch/arm64/kernel/smp.c | 4 +- arch/ia64/kernel/acpi.c | 12 ++--- arch/x86/kernel/acpi/boot.c | 36 +++++++------- drivers/acpi/numa.c | 16 +++---- drivers/acpi/scan.c | 4 +- drivers/acpi/tables.c | 67 +++++++++++++++++++++++---- drivers/irqchip/irq-gic-v2m.c | 2 +- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its.c | 6 +-- drivers/irqchip/irq-gic-v3.c | 10 ++-- drivers/irqchip/irq-gic.c | 4 +- drivers/mailbox/pcc.c | 2 +- include/linux/acpi.h | 5 +- 15 files changed, 112 insertions(+), 62 deletions(-)
arch/arm64/kernel/acpi_numa.c +1 -1
@@ -45,7 +45,7 @@ static inline int get_cpu_for_acpi_id(u32 uid)return -EINVAL ; } -static int __init acpi_parse_gicc_pxm (struct acpi_subtable_header *header, +static int __init acpi_parse_gicc_pxm (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_srat_gicc_affinity *pa;
arch/arm64/kernel/smp.c +2 -2
@@ -553,7 +553,7 @@ acpi_map_gic_cpu_interface(struct acpi_madt_generic_interrupt *processor) }static int __init -acpi_parse_gic_cpu_interface (struct acpi_subtable_header *header, +acpi_parse_gic_cpu_interface (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_generic_interrupt *processor;
@@ -562,7 +562,7 @@ acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,if (BAD_MADT_GICC_ENTRY (processor, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);acpi_map_gic_cpu_interface (processor);
arch/ia64/kernel/acpi.c +6 -6
@@ -177,7 +177,7 @@ struct acpi_table_madt *acpi_madt __initdata;static u8 has_8259;static int __init -acpi_parse_lapic_addr_ovr (struct acpi_subtable_header * header, +acpi_parse_lapic_addr_ovr (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_local_apic_override *lapic;
@@ -216,7 +216,7 @@ acpi_parse_lsapic(struct acpi_subtable_header * header, const unsigned long end) }static int __init -acpi_parse_lapic_nmi (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_lapic_nmi (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_local_apic_nmi *lacpi_nmi;
@@ -230,7 +230,7 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long e }static int __init -acpi_parse_iosapic (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_iosapic (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_io_sapic *iosapic;
@@ -245,7 +245,7 @@ acpi_parse_iosapic(struct acpi_subtable_header * header, const unsigned long endstatic unsigned int __initdata acpi_madt_rev;static int __init -acpi_parse_plat_int_src (struct acpi_subtable_header * header, +acpi_parse_plat_int_src (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_interrupt_source *plintsrc;
@@ -329,7 +329,7 @@ unsigned int get_cpei_target_cpu(void) }static int __init -acpi_parse_int_src_ovr (struct acpi_subtable_header * header, +acpi_parse_int_src_ovr (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_interrupt_override *p;
@@ -350,7 +350,7 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header, }static int __init -acpi_parse_nmi_src (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_nmi_src (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_nmi_source *nmi_src;
arch/x86/kernel/acpi/boot.c +18 -18
@@ -197,7 +197,7 @@ static int acpi_register_lapic(int id, u32 acpiid, u8 enabled) }static int __init -acpi_parse_x2apic (struct acpi_subtable_header *header,const unsigned long end) +acpi_parse_x2apic (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_local_x2apic *processor =NULL ;#ifdef CONFIG_X86_X2APIC
@@ -210,7 +210,7 @@ acpi_parse_x2apic(struct acpi_subtable_header *header, const unsigned long end)if (BAD_MADT_ENTRY (processor, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);#ifdef CONFIG_X86_X2APIC apic_id = processor->local_apic_id;
@@ -242,7 +242,7 @@ acpi_parse_x2apic(struct acpi_subtable_header *header, const unsigned long end) }static int __init -acpi_parse_lapic (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_lapic (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_local_apic *processor =NULL ;
@@ -251,7 +251,7 @@ acpi_parse_lapic(struct acpi_subtable_header * header, const unsigned long end)if (BAD_MADT_ENTRY (processor, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);/* Ignore invalid ID */ if (processor->id ==0xff )
@@ -272,7 +272,7 @@ acpi_parse_lapic(struct acpi_subtable_header * header, const unsigned long end) }static int __init -acpi_parse_sapic (struct acpi_subtable_header *header,const unsigned long end) +acpi_parse_sapic (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_local_sapic *processor =NULL ;
@@ -281,7 +281,7 @@ acpi_parse_sapic(struct acpi_subtable_header *header, const unsigned long end)if (BAD_MADT_ENTRY (processor, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common); acpi_register_lapic((processor->id << 8) | processor->eid,/* APIC ID */ processor->processor_id, /* ACPI ID */
@@ -291,7 +291,7 @@ acpi_parse_sapic(struct acpi_subtable_header *header, const unsigned long end) }static int __init -acpi_parse_lapic_addr_ovr (struct acpi_subtable_header * header, +acpi_parse_lapic_addr_ovr (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_local_apic_override *lapic_addr_ovr =NULL ;
@@ -301,7 +301,7 @@ acpi_parse_lapic_addr_ovr(struct acpi_subtable_header * header,if (BAD_MADT_ENTRY (lapic_addr_ovr, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common); acpi_lapic_addr = lapic_addr_ovr->address;
@@ -309,7 +309,7 @@ acpi_parse_lapic_addr_ovr(struct acpi_subtable_header * header, }static int __init -acpi_parse_x2apic_nmi (struct acpi_subtable_header *header, +acpi_parse_x2apic_nmi (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_local_x2apic_nmi *x2apic_nmi =NULL ;
@@ -319,7 +319,7 @@ acpi_parse_x2apic_nmi(struct acpi_subtable_header *header,if (BAD_MADT_ENTRY (x2apic_nmi, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);if (x2apic_nmi->lint !=1 ) printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");
@@ -328,7 +328,7 @@ acpi_parse_x2apic_nmi(struct acpi_subtable_header *header, }static int __init -acpi_parse_lapic_nmi (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_lapic_nmi (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_local_apic_nmi *lapic_nmi =NULL ;
@@ -337,7 +337,7 @@ acpi_parse_lapic_nmi(struct acpi_subtable_header * header, const unsigned long eif (BAD_MADT_ENTRY (lapic_nmi, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);if (lapic_nmi->lint !=1 ) printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");
@@ -449,7 +449,7 @@ static int __init mp_register_ioapic_irq(u8 bus_irq, u8 polarity, }static int __init -acpi_parse_ioapic (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_ioapic (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_io_apic *ioapic =NULL ;struct ioapic_domain_cfg cfg = {
@@ -462,7 +462,7 @@ acpi_parse_ioapic(struct acpi_subtable_header * header, const unsigned long end)if (BAD_MADT_ENTRY (ioapic, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);/* Statically assign IRQ numbers for IOAPICs hosting legacy IRQs */ if (ioapic->global_irq_base <nr_legacy_irqs ())
@@ -508,7 +508,7 @@ static void __init acpi_sci_ioapic_setup(u8 bus_irq, u16 polarity, u16 trigger, }static int __init -acpi_parse_int_src_ovr (struct acpi_subtable_header * header, +acpi_parse_int_src_ovr (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_interrupt_override *intsrc =NULL ;
@@ -518,7 +518,7 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header,if (BAD_MADT_ENTRY (intsrc, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);if (intsrc->source_irq == acpi_gbl_FADT.sci_interrupt) { acpi_sci_ioapic_setup(intsrc->source_irq,
@@ -550,7 +550,7 @@ acpi_parse_int_src_ovr(struct acpi_subtable_header * header, }static int __init -acpi_parse_nmi_src (struct acpi_subtable_header * header,const unsigned long end) +acpi_parse_nmi_src (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_madt_nmi_source *nmi_src =NULL ;
@@ -559,7 +559,7 @@ acpi_parse_nmi_src(struct acpi_subtable_header * header, const unsigned long endif (BAD_MADT_ENTRY (nmi_src, end))return -EINVAL ; -acpi_table_print_madt_entry (header); +acpi_table_print_madt_entry (&header->common);/* TBD: Support nimsrc entries? */
drivers/acpi/numa.c +8 -8
@@ -338,7 +338,7 @@ acpi_numa_x2apic_affinity_init(struct acpi_srat_x2apic_cpu_affinity *pa) }static int __init -acpi_parse_x2apic_affinity (struct acpi_subtable_header *header, +acpi_parse_x2apic_affinity (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_srat_x2apic_cpu_affinity *processor_affinity;
@@ -347,7 +347,7 @@ acpi_parse_x2apic_affinity(struct acpi_subtable_header *header,if (!processor_affinity)return -EINVAL ; -acpi_table_print_srat_entry (header); +acpi_table_print_srat_entry (&header->common);/* let architecture-dependent part to do it */ acpi_numa_x2apic_affinity_init (processor_affinity);
@@ -356,7 +356,7 @@ acpi_parse_x2apic_affinity(struct acpi_subtable_header *header, }static int __init -acpi_parse_processor_affinity (struct acpi_subtable_header *header, +acpi_parse_processor_affinity (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_srat_cpu_affinity *processor_affinity;
@@ -365,7 +365,7 @@ acpi_parse_processor_affinity(struct acpi_subtable_header *header,if (!processor_affinity)return -EINVAL ; -acpi_table_print_srat_entry (header); +acpi_table_print_srat_entry (&header->common);/* let architecture-dependent part to do it */ acpi_numa_processor_affinity_init (processor_affinity);
@@ -374,7 +374,7 @@ acpi_parse_processor_affinity(struct acpi_subtable_header *header, }static int __init -acpi_parse_gicc_affinity (struct acpi_subtable_header *header, +acpi_parse_gicc_affinity (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_srat_gicc_affinity *processor_affinity;
@@ -383,7 +383,7 @@ acpi_parse_gicc_affinity(struct acpi_subtable_header *header,if (!processor_affinity)return -EINVAL ; -acpi_table_print_srat_entry (header); +acpi_table_print_srat_entry (&header->common);/* let architecture-dependent part to do it */ acpi_numa_gicc_affinity_init (processor_affinity);
@@ -394,7 +394,7 @@ acpi_parse_gicc_affinity(struct acpi_subtable_header *header,static int __initdata parsed_numa_memblks;static int __init -acpi_parse_memory_affinity (struct acpi_subtable_header * header, +acpi_parse_memory_affinity (union acpi_subtable_headers * header,const unsigned long end) {struct acpi_srat_mem_affinity *memory_affinity;
@@ -403,7 +403,7 @@ acpi_parse_memory_affinity(struct acpi_subtable_header * header,if (!memory_affinity)return -EINVAL ; -acpi_table_print_srat_entry (header); +acpi_table_print_srat_entry (&header->common);/* let architecture-dependent part to do it */ if (!acpi_numa_memory_affinity_init (memory_affinity))
drivers/acpi/scan.c +2 -2
@@ -2240,10 +2240,10 @@ static struct acpi_probe_entry *ape;static int acpi_probe_count;static DEFINE_MUTEX (acpi_probe_mutex); -static int __init acpi_match_madt (struct acpi_subtable_header *header, +static int __init acpi_match_madt (union acpi_subtable_headers *header,const unsigned long end) { -if (!ape->subtable_valid || ape->subtable_valid (header, ape)) +if (!ape->subtable_valid || ape->subtable_valid (&header->common, ape))if (!ape->probe_subtbl (header, end)) acpi_probe_count++;
drivers/acpi/tables.c +57 -10
109 lines not on this page · raw message
drivers/irqchip/irq-gic-v2m.c +1 -1
@@ -446,7 +446,7 @@ static struct fwnode_handle *gicv2m_get_fwnode(struct device *dev) }static int __init -acpi_parse_madt_msi (struct acpi_subtable_header *header, +acpi_parse_madt_msi (union acpi_subtable_headers *header,const unsigned long end) {int ret;
drivers/irqchip/irq-gic-v3-its-pci-msi.c +1 -1
@@ -159,7 +159,7 @@ static int __init its_pci_of_msi_init(void)#ifdef CONFIG_ACPI static int __init -its_pci_msi_parse_madt (struct acpi_subtable_header *header, +its_pci_msi_parse_madt (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_generic_translator *its_entry;
drivers/irqchip/irq-gic-v3-its-platform-msi.c +1 -1
@@ -117,7 +117,7 @@ static int __init its_pmsi_init_one(struct fwnode_handle *fwnode,#ifdef CONFIG_ACPI static int __init -its_pmsi_parse_madt (struct acpi_subtable_header *header, +its_pmsi_parse_madt (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_generic_translator *its_entry;
drivers/irqchip/irq-gic-v3-its.c +3 -3
@@ -3764,13 +3764,13 @@ static int __init acpi_get_its_numa_node(u32 its_id)return NUMA_NO_NODE ; } -static int __init gic_acpi_match_srat_its (struct acpi_subtable_header *header, +static int __init gic_acpi_match_srat_its (union acpi_subtable_headers *header,const unsigned long end) {return 0 ; } -static int __init gic_acpi_parse_srat_its (struct acpi_subtable_header *header, +static int __init gic_acpi_parse_srat_its (union acpi_subtable_headers *header,const unsigned long end) {int node;
@@ -3837,7 +3837,7 @@ static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }static void __init acpi_its_srat_maps_free (void ) { }#endif -static int __init gic_acpi_parse_madt_its (struct acpi_subtable_header *header, +static int __init gic_acpi_parse_madt_its (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_generic_translator *its_entry;
drivers/irqchip/irq-gic-v3.c +5 -5
@@ -1392,7 +1392,7 @@ gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) }static int __init -gic_acpi_parse_madt_redist (struct acpi_subtable_header *header, +gic_acpi_parse_madt_redist (union acpi_subtable_headers *header,const unsigned long end) { struct acpi_madt_generic_redistributor *redist =
@@ -1410,7 +1410,7 @@ gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, }static int __init -gic_acpi_parse_madt_gicc (struct acpi_subtable_header *header, +gic_acpi_parse_madt_gicc (union acpi_subtable_headers *header,const unsigned long end) { struct acpi_madt_generic_interrupt *gicc =
@@ -1452,14 +1452,14 @@ static int __init gic_acpi_collect_gicr_base(void)return -ENODEV ; } -static int __init gic_acpi_match_gicr (struct acpi_subtable_header *header, +static int __init gic_acpi_match_gicr (union acpi_subtable_headers *header,const unsigned long end) {/* Subtable presence means that redist exists, that's it */ return 0 ; } -static int __init gic_acpi_match_gicc (struct acpi_subtable_header *header, +static int __init gic_acpi_match_gicc (union acpi_subtable_headers *header,const unsigned long end) { struct acpi_madt_generic_interrupt *gicc =
@@ -1525,7 +1525,7 @@ static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header,return true; } -static int __init gic_acpi_parse_virt_madt_gicc (struct acpi_subtable_header *header, +static int __init gic_acpi_parse_virt_madt_gicc (union acpi_subtable_headers *header,const unsigned long end) { struct acpi_madt_generic_interrupt *gicc =
drivers/irqchip/irq-gic.c +2 -2
@@ -1508,7 +1508,7 @@ static struct } acpi_data__initdata ;static int __init -gic_acpi_parse_madt_cpu (struct acpi_subtable_header *header, +gic_acpi_parse_madt_cpu (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_madt_generic_interrupt *processor;
@@ -1540,7 +1540,7 @@ gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, }/* The things you have to do to just *count* something... */ -static int __init acpi_dummy_func (struct acpi_subtable_header *header, +static int __init acpi_dummy_func (union acpi_subtable_headers *header,const unsigned long end) {return 0 ;
drivers/mailbox/pcc.c +1 -1
@@ -382,7 +382,7 @@ static const struct mbox_chan_ops pcc_chan_ops = {* * This gets called for each entry in the PCC table. */ -static int parse_pcc_subspace (struct acpi_subtable_header *header, +static int parse_pcc_subspace (union acpi_subtable_headers *header,const unsigned long end) {struct acpi_pcct_subspace *ss = (struct acpi_pcct_subspace *) header;
include/linux/acpi.h +4 -1
@@ -141,10 +141,13 @@ enum acpi_address_range_id {/* Table Handlers */ +union acpi_subtable_headers { +struct acpi_subtable_header common; +};typedef int (*acpi_tbl_table_handler )(struct acpi_table_header *table); -typedef int (*acpi_tbl_entry_handler )(struct acpi_subtable_header *header, +typedef int (*acpi_tbl_entry_handler )(union acpi_subtable_headers *header,const unsigned long end);/* Debugger support */
Signature · 1 line
2.14.4
PATCH v4 2/13 acpi: Add HMAT to generic parsing tables
In reply to Keith BuschThe Heterogeneous Memory Attribute Table (HMAT) header has different field lengths than the existing parsing uses. Add the HMAT type to the parsing rules so it may be generically parsed.
--- drivers/acpi/tables.c | 9 +++++++++ include/linux/acpi.h | 1 + 2 files changed, 10 insertions(+)
drivers/acpi/tables.c +9 -0
@@ -51,6 +51,7 @@ static int acpi_apic_instance __initdata;enum acpi_subtable_type {ACPI_SUBTABLE_COMMON , +ACPI_SUBTABLE_HMAT , };struct acpi_subtable_entry {
@@ -232,6 +233,8 @@ acpi_get_entry_type(struct acpi_subtable_entry *entry)switch (entry->type) {case ACPI_SUBTABLE_COMMON :return entry->hdr->common.type; +case ACPI_SUBTABLE_HMAT : +return entry->hdr->hmat.type; }return 0 ; }
@@ -242,6 +245,8 @@ acpi_get_entry_length(struct acpi_subtable_entry *entry)switch (entry->type) {case ACPI_SUBTABLE_COMMON :return entry->hdr->common.length; +case ACPI_SUBTABLE_HMAT : +return entry->hdr->hmat.length; }return 0 ; }
@@ -252,6 +257,8 @@ acpi_get_subtable_header_length(struct acpi_subtable_entry *entry)switch (entry->type) {case ACPI_SUBTABLE_COMMON :return sizeof (entry->hdr->common); +case ACPI_SUBTABLE_HMAT : +return sizeof (entry->hdr->hmat); }return 0 ; }
@@ -259,6 +266,8 @@ acpi_get_subtable_header_length(struct acpi_subtable_entry *entry)static enum acpi_subtable_type __init acpi_get_subtable_type (char *id) { +if (strncmp (id,ACPI_SIG_HMAT ,4 ) ==0 ) +return ACPI_SUBTABLE_HMAT ;return ACPI_SUBTABLE_COMMON ; }
include/linux/acpi.h +1 -0
@@ -143,6 +143,7 @@ enum acpi_address_range_id {/* Table Handlers */ union acpi_subtable_headers {struct acpi_subtable_header common; +struct acpi_hmat_structure hmat; };typedef int (*acpi_tbl_table_handler )(struct acpi_table_header *table);
Signature · 1 line
2.14.4
PATCH v4 3/13 acpi/hmat: Parse and report heterogeneous memory
In reply to Keith BuschSystems may provide different memory types and export this information in the ACPI Heterogeneous Memory Attribute Table (HMAT). Parse these tables provided by the platform and report the memory access and caching attributes.
--- drivers/acpi/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/hmat/Kconfig | 8 ++ drivers/acpi/hmat/Makefile | 1 + drivers/acpi/hmat/hmat.c | 180 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 191 insertions(+) create mode 100644 drivers/acpi/hmat/Kconfig create mode 100644 drivers/acpi/hmat/Makefile create mode 100644 drivers/acpi/hmat/hmat.c
drivers/acpi/Kconfig +1 -0
@@ -465,6 +465,7 @@ config ACPI_REDUCED_HARDWARE_ONLY If you are unsure what to do, do not enable this option. source "drivers/acpi/nfit/Kconfig" +source "drivers/acpi/hmat/Kconfig" source "drivers/acpi/apei/Kconfig" source "drivers/acpi/dptf/Kconfig"
drivers/acpi/Makefile +1 -0
@@ -79,6 +79,7 @@ obj-$(CONFIG_ACPI_PROCESSOR) += processor.o obj-$(CONFIG_ACPI) += container.o obj-$(CONFIG_ACPI_THERMAL) += thermal.o obj-$(CONFIG_ACPI_NFIT) += nfit/ +obj-$(CONFIG_ACPI_HMAT) += hmat/ obj-$(CONFIG_ACPI) += acpi_memhotplug.o obj-$(CONFIG_ACPI_HOTPLUG_IOAPIC) += ioapic.o obj-$(CONFIG_ACPI_BATTERY) += battery.o
drivers/acpi/hmat/Kconfig new file +8 -0
@@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +config ACPI_HMAT + bool "ACPI Heterogeneous Memory Attribute Table Support" + depends on ACPI_NUMA + help + Parses representation of the ACPI Heterogeneous Memory Attributes + Table (HMAT) and set the memory node relationships and access + attributes.
drivers/acpi/hmat/Makefile new file +1 -0
@@ -0,0 +1 @@ +obj-$(CONFIG_ACPI_HMAT) := hmat.o
drivers/acpi/hmat/hmat.c new file +180 -0
180 lines not on this page · raw message
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 03/13] acpi/hmat: Parse and report heterogeneous memory
Quoted 35 lines · Keith Busch
Systems may provide different memory types and export this information in the ACPI Heterogeneous Memory Attribute Table (HMAT). Parse these tables provided by the platform and report the memory access and caching attributes.
Signed-off-by Keith Busch <[email protected]>--- drivers/acpi/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/hmat/Kconfig | 8 ++ drivers/acpi/hmat/Makefile | 1 + drivers/acpi/hmat/hmat.c | 180 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 191 insertions(+) create mode 100644 drivers/acpi/hmat/Kconfig create mode 100644 drivers/acpi/hmat/Makefile create mode 100644 drivers/acpi/hmat/hmat.cdrivers/acpi/Kconfig +1
-0@@ -465,6 +465,7 @@ config ACPI_REDUCED_HARDWARE_ONLY If you are unsure what to do, do not enable this option. source "drivers/acpi/nfit/Kconfig" +source "drivers/acpi/hmat/Kconfig" source "drivers/acpi/apei/Kconfig" source "drivers/acpi/dptf/Kconfig"drivers/acpi/Makefile +0
-0
drivers/acpi/Makefile obj-$(CONFIG_ACPI_PROCESSOR) += processor.o · line 82
Quoted 4 lines
drivers/acpi/Makefile +1
-0@@ -79,6 +79,7 @@ obj-$(CONFIG_ACPI_PROCESSOR) += processor.o obj-$(CONFIG_ACPI) += container.o obj-$(CONFIG_ACPI_THERMAL) += thermal.o obj-$(CONFIG_ACPI_NFIT) += nfit/ +obj-$(CONFIG_ACPI_HMAT) += hmat/
Yes, I prefer it to go into a separate directory.
Who do you want to maintain it, me or Dan?
Quoted 9 lines
drivers/acpi/Makefile +0
-0obj-$(CONFIG_ACPI) += acpi_memhotplug.o obj-$(CONFIG_ACPI_HOTPLUG_IOAPIC) += ioapic.o obj-$(CONFIG_ACPI_BATTERY) += battery.odrivers/acpi/hmat/Kconfig new file +0
-0
drivers/acpi/hmat/Kconfig line 8
Quoted 8 lines
drivers/acpi/hmat/Kconfig new file +8
-0@@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +config ACPI_HMAT + bool "ACPI Heterogeneous Memory Attribute Table Support" + depends on ACPI_NUMA + help + Parses representation of the ACPI Heterogeneous Memory Attributes + Table (HMAT) and set the memory node relationships and access + attributes.
What about:
"If set, this option causes the kernel to set the memory NUMA node relationships and access attributes in accordance with ACPI HMAT (Heterogeneous Memory Attributes Table)."
Quoted 13 lines
drivers/acpi/hmat/Makefile new file +1
-0@@ -0,0 +1 @@ +obj-$(CONFIG_ACPI_HMAT) := hmat.odrivers/acpi/hmat/hmat.c new file +0
-0
drivers/acpi/hmat/hmat.c line 5
Quoted 5 lines
drivers/acpi/hmat/hmat.c new file +5
-0@@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0 +/* +* Heterogeneous Memory Attributes Table (HMAT) representation +* +* Copyright (c) 2018, Intel Corporation.
Can you put a comment describing the code somewhat in here?
drivers/acpi/hmat/hmat.c line 18
Quoted 13 lines
drivers/acpi/hmat/hmat.c new file +13
-0+*/ + +#include <acpi/acpi_numa.h> +#include <linux/acpi.h> +#include <linux/bitops.h> +#include <linux/cpu.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/node.h> +#include <linux/slab.h> +#include <linux/sysfs.h>
Are all of the headers above really necessary to build the code?
Quoted 39 lines
drivers/acpi/hmat/hmat.c new file +39
-0+ +static __init const char *hmat_data_type (u8 type) +{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : +return "Access Latency" ; +case ACPI_HMAT_READ_LATENCY : +return "Read Latency" ; +case ACPI_HMAT_WRITE_LATENCY : +return "Write Latency" ; +case ACPI_HMAT_ACCESS_BANDWIDTH : +return "Access Bandwidth" ; +case ACPI_HMAT_READ_BANDWIDTH : +return "Read Bandwidth" ; +case ACPI_HMAT_WRITE_BANDWIDTH : +return "Write Bandwidth" ; +default : +return "Reserved" ; + }; +} + +static __init const char *hmat_data_type_suffix (u8 type) +{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : +case ACPI_HMAT_READ_LATENCY : +case ACPI_HMAT_WRITE_LATENCY : +return " nsec" ; +case ACPI_HMAT_ACCESS_BANDWIDTH : +case ACPI_HMAT_READ_BANDWIDTH : +case ACPI_HMAT_WRITE_BANDWIDTH : +return " MB/s" ; +default : +return "" ; + }; +} + +static __init int hmat_parse_locality (union acpi_subtable_headers *header, +const unsigned long end)
drivers/acpi/hmat/hmat.c line 67
Quoted 10 lines
drivers/acpi/hmat/hmat.c new file +10
-0+{ +struct acpi_hmat_locality *loc = (void *)header; +unsigned int init, targ, total_size, ipds, tpds; +u32 *inits, *targs, value; +u16 *entries; +u8 type; + +if (loc->header.length <sizeof (*loc)) { +pr_err ("HMAT: Unexpected locality header length: %d\n" , + loc->header.length);
Why pr_err()? Is the error really high-prio?
Same below.
Quoted 22 lines
drivers/acpi/hmat/hmat.c new file +22
-0+return -EINVAL ; + } + + type = loc->data_type; + ipds = loc->number_of_initiator_Pds; + tpds = loc->number_of_target_Pds; + total_size =sizeof (*loc) +sizeof (*entries) * ipds * tpds + +sizeof (*inits) * ipds +sizeof (*targs) * tpds; +if (loc->header.length < total_size) { +pr_err ("HMAT: Unexpected locality header length:%d, minimum required:%d\n" , + loc->header.length, total_size); +return -EINVAL ; + } + +pr_info ("HMAT: Locality: Flags:%02x Type:%s Initiator Domains:%d Target Domains:%d Base:%lld\n" , + loc->flags,hmat_data_type (type), ipds, tpds, + loc->entry_base_unit); + + inits = (u32 *)(loc +1 ); + targs = &inits[ipds]; + entries = (u16 *)(&targs[tpds]); +for (targ =0 ; targ < tpds; targ++) {
drivers/acpi/hmat/hmat.c line 99
Quoted 10 lines
drivers/acpi/hmat/hmat.c new file +10
-0+for (init =0 ; init < ipds; init++) { + value = entries[init * tpds + targ]; + value = (value * loc->entry_base_unit) /10 ; +pr_info (" Initiator-Target[%d-%d]:%d%s\n" , + inits[init], targs[targ], value, +hmat_data_type_suffix (type)); + } + } +return 0 ; +}
The format and meaning of what is printed into the log should be documented somewhere IMO.
Of course, that applies to the functions below as well.
Quoted 72 lines
drivers/acpi/hmat/hmat.c new file +72
-0+ +static __init int hmat_parse_cache (union acpi_subtable_headers *header, +const unsigned long end) +{ +struct acpi_hmat_cache *cache = (void *)header; +u32 attrs; + +if (cache->header.length <sizeof (*cache)) { +pr_err ("HMAT: Unexpected cache header length: %d\n" , + cache->header.length); +return -EINVAL ; + } + + attrs = cache->cache_attributes; +pr_info ("HMAT: Cache: Domain:%d Size:%llu Attrs:%08x SMBIOS Handles:%d\n" , + cache->memory_PD, cache->cache_size, attrs, + cache->number_of_SMBIOShandles); + +return 0 ; +} + +static int __init hmat_parse_address_range (union acpi_subtable_headers *header, +const unsigned long end) +{ +struct acpi_hmat_address_range *spa = (void *)header; + +if (spa->header.length !=sizeof (*spa)) { +pr_err ("HMAT: Unexpected address range header length: %d\n" , + spa->header.length); +return -EINVAL ; + } +pr_info ("HMAT: Memory (%#llx length %#llx) Flags:%04x Processor Domain:%d Memory Domain:%d\n" , + spa->physical_address_base, spa->physical_address_length, + spa->flags, spa->processor_PD, spa->memory_PD); +return 0 ; +} + +static int __init hmat_parse_subtable (union acpi_subtable_headers *header, +const unsigned long end) +{ +struct acpi_hmat_structure *hdr = (void *)header; + +if (!hdr) +return -EINVAL ; + +switch (hdr->type) { +case ACPI_HMAT_TYPE_ADDRESS_RANGE : +return hmat_parse_address_range (header, end); +case ACPI_HMAT_TYPE_LOCALITY : +return hmat_parse_locality (header, end); +case ACPI_HMAT_TYPE_CACHE : +return hmat_parse_cache (header, end); +default : +return -EINVAL ; + } +} + +static __init int hmat_init (void ) +{ +struct acpi_table_header *tbl; +enum acpi_hmat_type i; +acpi_status status; + +if (srat_disabled ()) +return 0 ; + + status =acpi_get_table (ACPI_SIG_HMAT ,0 , &tbl); +if (ACPI_FAILURE (status)) +return 0 ; + +for (i =ACPI_HMAT_TYPE_ADDRESS_RANGE ; i <ACPI_HMAT_TYPE_RESERVED ; i++) { + if (acpi_table_parse_entries(ACPI_SIG_HMAT,
drivers/acpi/hmat/hmat.c
Quoted 10 lines
drivers/acpi/hmat/hmat.c new file +9
-1+ sizeof(struct acpi_table_hmat), i, + hmat_parse_subtable, 0) < 0) + goto out_put; + } +out_put: +acpi_put_table (tbl); +return 0 ; +} +subsys_initcall (hmat_init); --
It looks like this particular patch only causes some extra messages to be printed into the log, no attributes setting etc yet.
I would like the changelog to mention that.
PATCH v4 4/13 node: Link memory nodes to their compute nodes
In reply to Keith BuschSystems may be constructed with various specialized nodes. Some nodes may provide memory, some provide compute devices that access and use that memory, and others may provide both. Nodes that provide memory are referred to as memory targets, and nodes that can initiate memory access are referred to as memory initiators.
Memory targets will often have varying access characteristics from different initiators, and platforms may have ways to express those relationships. In preparation for these systems, provide interfaces for the kernel to export the memory relationship among different nodes memory targets and their initiators with symlinks to each other's nodes, and export node lists showing the same relationship.
If a system provides access locality for each initiator-target pair, nodes may be grouped into ranked access classes relative to other nodes. The new interface allows a subsystem to register relationships of varying classes if available and desired to be exported. A lower class number indicates a higher performing tier, with 0 being the best performing class.
A memory initiator may have multiple memory targets in the same access class. The initiator's memory targets in given class indicate the node's access characteristics perform better relative to other initiator nodes either unreported or in lower class numbers. The targets within an initiator's class, though, do not necessarily perform the same as each other.
A memory target node may have multiple memory initiators. All linked initiators in a target's class have the same access characteristics to that target.
The following example show the nodes' new sysfs hierarchy for a memory target node 'Y' with class 0 access from initiator node 'X':
# symlinks -v /sys/devices/system/node/nodeX/class0/ relative: /sys/devices/system/node/nodeX/class0/targetY -> ../../nodeY
# symlinks -v /sys/devices/system/node/nodeY/class0/ relative: /sys/devices/system/node/nodeY/class0/initiatorX -> ../../nodeX
And the same information is reflected in the nodelist:
# cat /sys/devices/system/node/nodeX/class0/target_nodelist Y
# cat /sys/devices/system/node/nodeY/class0/initiator_nodelist X
--- drivers/base/node.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++++++- include/linux/node.h | 6 ++- 2 files changed, 131 insertions(+), 2 deletions(-)
drivers/base/node.c +126 -1
@@ -17,6 +17,7 @@#include <linux/nodemask.h> #include <linux/cpu.h> #include <linux/device.h> +#include <linux/pm_runtime.h> #include <linux/swap.h> #include <linux/slab.h>
@@ -59,6 +60,91 @@ static inline ssize_t node_read_cpulist(struct device *dev, static DEVICE_ATTR(cpumap, S_IRUGO, node_read_cpumask, NULL); static DEVICE_ATTR(cpulist, S_IRUGO, node_read_cpulist, NULL); +struct node_class_nodes { +struct device dev; +struct list_head list_node; +unsigned class; +nodemask_t initiator_nodes; +nodemask_t target_nodes; +}; +#define to_class_nodes (dev) container_of(dev, struct node_class_nodes, dev) + +static ssize_t initiator_nodelist_show (struct device *dev, +struct device_attribute *attr,char *buf) +{ +struct node_class_nodes *c =to_class_nodes (dev); +return scnprintf (buf,PAGE_SIZE -1 ,"%*pbl\n" , +nodemask_pr_args (&c->initiator_nodes)); +} +static DEVICE_ATTR_RO (initiator_nodelist); + +static ssize_t target_nodelist_show (struct device *dev, +struct device_attribute *attr,char *buf) +{ +struct node_class_nodes *c =to_class_nodes (dev); +return scnprintf (buf,PAGE_SIZE -1 ,"%*pbl\n" , +nodemask_pr_args (&c->target_nodes)); +} +static DEVICE_ATTR_RO (target_nodelist); + +static struct attribute *node_class_node_attrs[] = { + &dev_attr_initiator_nodelist.attr, + &dev_attr_target_nodelist.attr, +NULL , +}; +ATTRIBUTE_GROUPS (node_class_node); + +static void node_remove_classes (struct node *node) +{ +struct node_class_nodes *c, *cnext; + +list_for_each_entry_safe (c, cnext, &node->class_list, list_node) { +list_del (&c->list_node); +device_unregister (&c->dev); + } +} + +static void node_class_release (struct device *dev) +{ +kfree (to_class_nodes (dev)); +} + +static struct node_class_nodes *node_init_node_class (struct device *parent, +struct list_head *list, +unsigned class) +{ +struct node_class_nodes *class_node; +struct device *dev; + +list_for_each_entry (class_node, list, list_node) +if (class_node->class == class) +return class_node; + + class_node =kzalloc (sizeof (*class_node),GFP_KERNEL ); +if (!class_node) +return NULL ; + + class_node->class = class; + dev = &class_node->dev; + dev->parent = parent; + dev->release = node_class_release; + dev->groups = node_class_node_groups; +if (dev_set_name (dev,"class%u" , class)) + goto free; + +if (device_register (dev)) + goto free_name; + +pm_runtime_no_callbacks (dev); +list_add_tail (&class_node->list_node, list); +return class_node; +free_name: +kfree_const (dev->kobj.name); +free: +kfree (class_node); +return NULL ; +} +#define K (x) ((x) << (PAGE_SHIFT - 10))static ssize_t node_read_meminfo (struct device *dev,struct device_attribute *attr,char *buf)
@@ -340,7 +426,7 @@ static int register_node(struct node *node, int num)void unregister_node (struct node *node) {hugetlb_unregister_node (node);/* no-op, if memoryless node */ - +node_remove_classes (node);device_unregister (&node->dev); }
@@ -372,6 +458,44 @@ int register_cpu_under_node(unsigned int cpu, unsigned int nid) kobject_name(&node_devices[nid]->dev.kobj)); } +int register_memory_node_under_compute_node (unsigned int m,unsigned int p, +unsigned class) +{ +struct node *init, *targ; +struct node_class_nodes *i, *t; +char initiator[20 ];/* "initiator4294967295\0" */ +char target[17 ];/* "target4294967295\0" */ +int ret; + +if (!node_online (p) || !node_online (m)) +return -ENODEV ; + + init = node_devices[p]; + targ = node_devices[m]; + i =node_init_node_class (&init->dev, &init->class_list, class); + t =node_init_node_class (&targ->dev, &targ->class_list, class); +if (!i || !t) +return -ENOMEM ; + +snprintf (initiator,sizeof (initiator),"initiator%u" , p); +snprintf (target,sizeof (target),"target%u" , m); + ret =sysfs_create_link (&i->dev.kobj, &targ->dev.kobj, target); +if (ret) +return ret; + + ret =sysfs_create_link (&t->dev.kobj, &init->dev.kobj, initiator); +if (ret) + goto err; + +node_set (m, i->target_nodes); +node_set (p, t->initiator_nodes); +return 0 ; + err: +sysfs_remove_link (&node_devices[p]->dev.kobj, +kobject_name (&node_devices[m]->dev.kobj)); +return ret; +} +int unregister_cpu_under_node (unsigned int cpu,unsigned int nid) {struct device *obj;
@@ -580,6 +704,7 @@ int __register_one_node(int nid)register_cpu_under_node (cpu, nid); } +INIT_LIST_HEAD (&node_devices[nid]->class_list);/* initialize work queue for memory hot plug */ init_node_hugetlb_work (nid);
include/linux/node.h +5 -1
@@ -17,11 +17,12 @@#include <linux/device.h> #include <linux/cpumask.h> +#include <linux/list.h> #include <linux/workqueue.h> struct node {struct device dev; - +struct list_head class_list;#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE ) && defined(CONFIG_HUGETLBFS )struct work_struct node_work;#endif
@@ -75,6 +76,9 @@ extern int register_mem_sect_under_node(struct memory_block *mem_blk,extern int unregister_mem_sect_under_nodes (struct memory_block *mem_blk,unsigned long phys_index); +extern int register_memory_node_under_compute_node (unsigned int m,unsigned int p, +unsigned class); +#ifdef CONFIG_HUGETLBFS extern void register_hugetlbfs_with_node (node_registration_func_t doregister,node_registration_func_t unregister);
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 04/13] node: Link memory nodes to their compute nodes
Quoted 31 lines · Keith Busch
Systems may be constructed with various specialized nodes. Some nodes may provide memory, some provide compute devices that access and use that memory, and others may provide both. Nodes that provide memory are referred to as memory targets, and nodes that can initiate memory access are referred to as memory initiators.
Memory targets will often have varying access characteristics from different initiators, and platforms may have ways to express those relationships. In preparation for these systems, provide interfaces for the kernel to export the memory relationship among different nodes memory targets and their initiators with symlinks to each other's nodes, and export node lists showing the same relationship.
If a system provides access locality for each initiator-target pair, nodes may be grouped into ranked access classes relative to other nodes. The new interface allows a subsystem to register relationships of varying classes if available and desired to be exported. A lower class number indicates a higher performing tier, with 0 being the best performing class.
A memory initiator may have multiple memory targets in the same access class. The initiator's memory targets in given class indicate the node's access characteristics perform better relative to other initiator nodes either unreported or in lower class numbers. The targets within an initiator's class, though, do not necessarily perform the same as each other.
A memory target node may have multiple memory initiators. All linked initiators in a target's class have the same access characteristics to that target.
Quoted 5 lines
The following example show the nodes' new sysfs hierarchy for a memory target node 'Y' with class 0 access from initiator node 'X':
# symlinks -v /sys/devices/system/node/nodeX/class0/ relative: /sys/devices/system/node/nodeX/class0/targetY -> ../../nodeY
If you added one more directory level and had "targets" and "initiators" under "class0", the names of the symlinks could be the same as the names of the nodes themselves, that is
/sys/devices/system/node/nodeX/class0/targets/nodeY -> ../../../nodeY
and the whole "nodelist" part wouldn't be necessary any more.
Also, it looks like "class0" is just a name at this point, but it will represent an access class going forward. Maybe it would be better to use the word "access" in the directory name to indicate that (so there would be "access0" instead of "class0").
Quoted 31 lines
# symlinks -v /sys/devices/system/node/nodeY/class0/ relative: /sys/devices/system/node/nodeY/class0/initiatorX -> ../../nodeXAnd the same information is reflected in the nodelist:
# cat /sys/devices/system/node/nodeX/class0/target_nodelist Y# cat /sys/devices/system/node/nodeY/class0/initiator_nodelist XSigned-off-by Keith Busch <[email protected]>--- drivers/base/node.c | 127 ++++++++++++++++++++++++++++++++++++++++++++++++++- include/linux/node.h | 6 ++- 2 files changed, 131 insertions(+), 2 deletions(-)drivers/base/node.c +1
-0@@ -17,6 +17,7 @@#include <linux/nodemask.h> #include <linux/cpu.h> #include <linux/device.h> +#include <linux/pm_runtime.h> #include <linux/swap.h> #include <linux/slab.h>
drivers/base/node.c static inline ssize_t node_read_cpulist(struct device *dev, · line 62
Quoted 3 lines
drivers/base/node.c +0
-0@@ -59,6 +60,91 @@ static inline ssize_t node_read_cpulist(struct device *dev, static DEVICE_ATTR(cpumap, S_IRUGO, node_read_cpumask, NULL); static DEVICE_ATTR(cpulist, S_IRUGO, node_read_cpulist, NULL);
A kerneldoc describing the struct type, please.
drivers/base/node.c static inline ssize_t node_read_cpulist(struct device *dev, · line 71
Quoted 9 lines
drivers/base/node.c +9
-0+struct node_class_nodes { +struct device dev; +struct list_head list_node; +unsigned class; +nodemask_t initiator_nodes; +nodemask_t target_nodes; +}; +#define to_class_nodes (dev) container_of(dev, struct node_class_nodes, dev) +
Generally speaking, your code is devoid of comments.
To a minimum, there should be kerneldoc comments for non-static functions to explain what they are for.
PATCH v4 5/13 Documentation/ABI: Add new node sysfs attributes
In reply to Keith BuschAdd entries for memory initiator and target node class attributes.
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)
Documentation/ABI/stable/sysfs-devices-node +24 -1
@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance. + +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance.
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>
I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:
Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.
This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --
Same here.
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
And, of course, the symlinks part needs to be documented as well. I guess you can follow the Documentation/ABI/testing/sysfs-devices-power_resources_D0 with that.
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 8 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Will do.
Quoted 27 lines
Quoted 27 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +13
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access
Quoted 8 lines
Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 3 lines
Documentation/ABI/stable/sysfs-devices-node +3
-0+ to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
I think it actually does make sense to use "%*pbl" format here. The type we're displaying is a bit array, so this is one value for that attribute. There are many precedents for disapling bit arrays this way. The existing node attributes that we're appending to show cpu lists, and the top loevel shows node lists for "possible", "online", "has_memory", "has_cpu". This new attribute should fit well with exisiting similar attributes from this subsystem.
Quoted 12 lines
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
I think that makes sense, I'll take try out this suggestion.
Quoted 3 lines
And, of course, the symlinks part needs to be documented as well. I guess you can follow the
Documentation/ABI/testing/sysfs-devices-power_resources_D0with that.
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
In reply to Rafael J. WysockiQuoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the /sys/devices/system hierarchy.
Greg Kroah-Hartman
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 59 lines · Dan Williams
Quoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 8 lines
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine. Just do not ever create a kobject just for a subdir, that will mess up userspace.
And I hate the "multi-value" sysfs files, where at all possible, please do not copy past bad mistakes there. If you can make them individual files, please do that, it makes it easier to maintain and code the kernel for.
thanks,
greg k-h
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 70 lines · Greg Kroah-Hartman
Quoted 59 lines · Dan Williams
Quoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 8 lines
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.
Quoted 8 lines
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine. Just do not ever create a kobject just for a subdir, that will mess up userspace.
And I hate the "multi-value" sysfs files, where at all possible, please do not copy past bad mistakes there. If you can make them individual files, please do that, it makes it easier to maintain and code the kernel for.
I agree in general about multi-value sysfs, but in this case we're talking about a mask. Masks are a single value. That said I can get on board with calling what 'cpulist' does a design mistake (human readable mask), but otherwise switching to one file per item in the mask is a mess for userspace to consume.
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 82 lines · Dan Williams
Quoted 70 lines · Greg Kroah-Hartman
Quoted 59 lines · Dan Williams
Quoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 8 lines
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.Quoted 8 lines
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine. Just do not ever create a kobject just for a subdir, that will mess up userspace.
And I hate the "multi-value" sysfs files, where at all possible, please do not copy past bad mistakes there. If you can make them individual files, please do that, it makes it easier to maintain and code the kernel for.
Quoted 5 lines
I agree in general about multi-value sysfs, but in this case we're talking about a mask. Masks are a single value. That said I can get on board with calling what 'cpulist' does a design mistake (human readable mask), but otherwise switching to one file per item in the mask is a mess for userspace to consume.
Can you please refer to my response to Keith?
If you have "initiators" and "targets" under "classX" and a list of symlinks in each of them, I don't see any kind of a mess here.
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 84 lines · Rafael J. Wysocki
Quoted 82 lines · Dan Williams
Quoted 78 lines · Greg Kroah-Hartman
Quoted 59 lines · Dan Williams
Quoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 8 lines
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine. Just do not ever create a kobject just for a subdir, that will mess up userspace.
And I hate the "multi-value" sysfs files, where at all possible, please do not copy past bad mistakes there. If you can make them individual files, please do that, it makes it easier to maintain and code the kernel for.
Quoted 7 lines
Quoted 5 lines
I agree in general about multi-value sysfs, but in this case we're talking about a mask. Masks are a single value. That said I can get on board with calling what 'cpulist' does a design mistake (human readable mask), but otherwise switching to one file per item in the mask is a mess for userspace to consume.
Can you please refer to my response to Keith?
Ah, ok I missed the patch4 comments and was reading this one in isolation... which also bolsters your comment about squashing these two patches together.
Quoted 2 lines
If you have "initiators" and "targets" under "classX" and a list of symlinks in each of them, I don't see any kind of a mess here.
In this instance, I think having symlinks at all is "messy" vs just having a mask. Yes, you're right, if we have the proposed symlinks from patch4 there is no need for these _nodelist attributes, and those symlinks would be better under "initiator" and "target" directories. However, I'm arguing going the other way, just have the 2 mask attributes and no symlinks. The HMAT erodes the concept of "numa nodes" typically being a single digit number space per platform. Given increasing numbers of memory target types and initiator devices its going to be cumbersome to have userspace walk multiple symlinks vs just reading a mask and opening the canonical path for a node directly.
This is also part of the rationale for only emitting one "class" (initiator / target performance profile) by default. There's an N-to-N initiator-target description in the HMAT. When / if we decide emit more classes the more work userspace would need to do to convert directory structures back into data.
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 101 lines · Dan Williams
Quoted 84 lines · Rafael J. Wysocki
Quoted 82 lines · Dan Williams
Quoted 78 lines · Greg Kroah-Hartman
Quoted 59 lines · Dan Williams
Quoted 58 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
Quoted 8 lines
Quoted 3 lines
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine. Just do not ever create a kobject just for a subdir, that will mess up userspace.
And I hate the "multi-value" sysfs files, where at all possible, please do not copy past bad mistakes there. If you can make them individual files, please do that, it makes it easier to maintain and code the kernel for.
Quoted 7 lines
Quoted 5 lines
I agree in general about multi-value sysfs, but in this case we're talking about a mask. Masks are a single value. That said I can get on board with calling what 'cpulist' does a design mistake (human readable mask), but otherwise switching to one file per item in the mask is a mess for userspace to consume.
Can you please refer to my response to Keith?
Ah, ok I missed the patch4 comments and was reading this one in isolation... which also bolsters your comment about squashing these two patches together.
Quoted 2 lines
If you have "initiators" and "targets" under "classX" and a list of symlinks in each of them, I don't see any kind of a mess here.
Quoted 11 lines
In this instance, I think having symlinks at all is "messy" vs just having a mask. Yes, you're right, if we have the proposed symlinks from patch4 there is no need for these
_nodelistattributes, and those symlinks would be better under "initiator" and "target" directories. However, I'm arguing going the other way, just have the 2 mask attributes and no symlinks. The HMAT erodes the concept of "numa nodes" typically being a single digit number space per platform. Given increasing numbers of memory target types and initiator devices its going to be cumbersome to have userspace walk multiple symlinks vs just reading a mask and opening the canonical path for a node directly.
The symlinks only need to be walked once, however, and after walking them (once) the user space program can simply create a mask for itself.
To me, the question here is how to represent a graph in a filesystem, and since nodes are naturally represented by directories, it is also natural to represent connections between them as symlinks.
Quoted 5 lines
This is also part of the rationale for only emitting one "class" (initiator / target performance profile) by default. There's an N-to-N initiator-target description in the HMAT. When / if we decide emit more classes the more work userspace would need to do to convert directory structures back into data.
I'm not convinced by this argument, as this conversion is a one-off exercise. Ultimately, a tool in user space would need to represent a graph anyway and how it obtains the data to do that doesn't matter too much to it.
However, IMO there is value in representing the graph in a filesystem in such a way that, say, a file manager program (without special modifications) can be used to walk it by a human.
Let alone the one-value-per-file rule of sysfs that doesn't need to be violated if symlinks are used.
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
In reply to Greg Kroah-HartmanQuoted 65 lines · Greg Kroah-Hartman
Quoted 63 lines · Dan Williams
Quoted 61 lines · Rafael J. Wysocki
Quoted 4 lines · Keith Busch
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>I would recommend combining this with the previous patch, as the way it is now I need to look at two patches at the time. :-)
Quoted 20 lines
--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +6
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 108
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in + nodes not in the list accessing this node's memory may have + different performance.This does not follow the general "one value per file" rule of sysfs (I know that there are other sysfs files with more than one value in them, but it is better to follow this rule as long as that makes sense).
Documentation/ABI/stable/sysfs-devices-node Date: December 2009
Quoted 9 lines
Documentation/ABI/stable/sysfs-devices-node +8
-1+ +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance. --Same here.
And if you follow the recommendation given in the previous message (add "initiators" and "targets" subdirs under "classX"), you won't even need the two files above.
Quoted 7 lines
Quoted 4 lines
This recommendation is in conflict with Greg's feedback about kobject usage. If these are just "vanity" subdirs I think it's better to have a multi-value sysfs file. This "list" style is already commonplace for the
/sys/devices/systemhierarchy.If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine.
Yes, that's what I was thinking about: along the lines of the "power" group under device kobjects.
Cheers,
Rafael
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 8 lines · Rafael J. Wysocki
Quoted 3 lines · Greg Kroah-Hartman
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine.
Yes, that's what I was thinking about: along the lines of the "power" group under device kobjects.
We can't append symlinks to an attribute group, though. I'd need to create a lot of struct devices just to get the desired directory hiearchy. And then each of those "devices" will have their own "power" group, which really doesn't make any sense for what we're trying to show. Is that really the right way to do this, or something else I'm missing?
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 5 lines · Keith Busch
Quoted 3 lines · Rafael J. Wysocki
Quoted 1 line · Greg Kroah-Hartman
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine.
Yes, that's what I was thinking about: along the lines of the "power" group under device kobjects.
We can't append symlinks to an attribute group, though.
That's right, unfortunately.
Quoted 1 line
I'd need to create a lot of struct devices just to get the desired directory hiearchy.
No, you don't need to do that. Kobjects can be added without registering a struct device for each of them kind of along the lines of what cpufreq does for its policy objects etc. See cpufreq_policy_alloc() and cpufreq_core_init() for examples.
Quoted 3 lines
And then each of those "devices" will have their own "power" group, which really doesn't make any sense for what we're trying to show. Is that really the right way to do this, or something else I'm missing?
Above?
Rafael J. Wysocki
maintainerRe: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 10 lines · Rafael J. Wysocki
Quoted 8 lines · Keith Busch
Quoted 6 lines · Rafael J. Wysocki
Quoted 3 lines · Greg Kroah-Hartman
If you do a subdirectory "correctly" (i.e. a name for an attribute group), that's fine.
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
Yes, that's what I was thinking about: along the lines of the "power" group under device kobjects.
We can't append symlinks to an attribute group, though.
That's right, unfortunately.
Scratch this.
You can add them using sysfs_add_link_to_group(). For example, see what acpi_power_expose_list() does.
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
In reply to Keith BuschQuoted 31 lines · On Wed, 16 Jan 2019 10:57:56 -0700 Keith Busch <[email protected]> wrote:
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +14
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators in
Documentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 116
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ nodes not in the list accessing this node's memory may have + different performance. + +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance.
Different performance from what? In the other thread we established that these target_nodelists are kind of a backwards reference, they all have their characteristics anyway. Perhaps this just needs to say:
"Memory access from this node to these targets may have different performance"?
i.e. Don't make the assumption I did that they should all be the same!
Re: [PATCHv4 05/13] Documentation/ABI: Add new node sysfs attributes
Quoted 51 lines · Jonathan Cameron
Quoted 31 lines · On Wed, 16 Jan 2019 10:57:56 -0700 Keith Busch <[email protected]> wrote:
Add entries for memory initiator and target node class attributes.
Signed-off-by Keith Busch <[email protected]>--- Documentation/ABI/stable/sysfs-devices-node | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-)Documentation/ABI/stable/sysfs-devices-node +14
-1@@ -90,4 +90,27 @@ Date: December 2009 Contact: Lee Schermerhorn <[email protected]> Description: The node's huge page size control/query attributes. - See Documentation/admin-guide/mm/hugetlbpage.rst + See Documentation/admin-guide/mm/hugetlbpage.rst + +What: /sys/devices/system/node/nodeX/classY/ +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node's relationship to other nodes for access class "Y". + +What: /sys/devices/system/node/nodeX/classY/initiator_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory initiators that have class "Y" access + to this node's memory. CPUs and other memory initiators inDocumentation/ABI/stable/sysfs-devices-node Date: December 2009 · line 116
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+ nodes not in the list accessing this node's memory may have + different performance. + +What: /sys/devices/system/node/nodeX/classY/target_nodelist +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The node list of memory targets that this initiator node has + class "Y" access. Memory accesses from this node to nodes not + in this list may have differet performance.Different performance from what? In the other thread we established that these
target_nodelistsare kind of a backwards reference, they all have their characteristics anyway. Perhaps this just needs to say:
"Memory access from this node to these targets may have different performance"?
Quoted 1 line
i.e. Don't make the assumption I did that they should all be the same!
I think a clarification of "class" is needed in this context. A "class" is the the set of initiators that have the same rated performance to a given target set. In other words "class" is a tuple of (performance profile, initiator set, target set). Different performance creates a different tuple / class.
PATCH v4 6/13 acpi/hmat: Register processor domain to its memory
In reply to Keith BuschIf the HMAT Subsystem Address Range provides a valid processor proximity domain for a memory domain, or a processor domain with the highest performing access exists, register the memory target with that initiator so this relationship will be visible under the node's sysfs directory.
Since HMAT requires valid address ranges have an equivalent SRAT entry, verify each memory target satisfies this requirement.
--- drivers/acpi/hmat/hmat.c | 143 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 136 insertions(+), 7 deletions(-)
drivers/acpi/hmat/hmat.c +136 -7
@@ -17,6 +17,43 @@#include <linux/slab.h> #include <linux/sysfs.h> +static LIST_HEAD (targets); + +struct memory_target { +struct list_head node; +unsigned int memory_pxm; +unsigned long p_nodes[BITS_TO_LONGS (MAX_NUMNODES )]; +}; + +static __init struct memory_target *find_mem_target (unsigned int m) +{ +struct memory_target *t; + +list_for_each_entry (t, &targets, node) +if (t->memory_pxm == m) +return t; +return NULL ; +} + +static __init void alloc_memory_target (unsigned int mem_pxm) +{ +struct memory_target *t; + +if (pxm_to_node (mem_pxm) ==NUMA_NO_NODE ) +return ; + + t =find_mem_target (mem_pxm); +if (t) +return ; + + t =kzalloc (sizeof (*t),GFP_KERNEL ); +if (!t) +return ; + + t->memory_pxm = mem_pxm; +list_add_tail (&t->node, &targets); +} +static __init const char *hmat_data_type (u8 type) {switch (type) {
@@ -53,11 +90,30 @@ static __init const char *hmat_data_type_suffix(u8 type) }; } +static __init void hmat_update_access (u8 type,u32 value,u32 *best) +{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : +case ACPI_HMAT_READ_LATENCY : +case ACPI_HMAT_WRITE_LATENCY : +if (!*best || *best > value) + *best = value; +break ; +case ACPI_HMAT_ACCESS_BANDWIDTH : +case ACPI_HMAT_READ_BANDWIDTH : +case ACPI_HMAT_WRITE_BANDWIDTH : +if (!*best || *best < value) + *best = value; +break ; + } +} +static __init int hmat_parse_locality (union acpi_subtable_headers *header,const unsigned long end) { +struct memory_target *t;struct acpi_hmat_locality *loc = (void *)header; -unsigned int init, targ, total_size, ipds, tpds; +unsigned int init, targ, pass, p_node, total_size, ipds, tpds;u32 *inits, *targs, value;u16 *entries;u8 type;
@@ -87,12 +143,28 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header, targs = &inits[ipds]; entries = (u16 *)(&targs[tpds]);for (targ =0 ; targ < tpds; targ++) { -for (init =0 ; init < ipds; init++) { - value = entries[init * tpds + targ]; - value = (value * loc->entry_base_unit) /10 ; -pr_info (" Initiator-Target[%d-%d]:%d%s\n" , - inits[init], targs[targ], value, -hmat_data_type_suffix (type)); +u32 best =0 ; + + t =find_mem_target (targs[targ]); +for (pass =0 ; pass <2 ; pass++) { +for (init =0 ; init < ipds; init++) { + value = entries[init * tpds + targ]; + value = (value * loc->entry_base_unit) /10 ; + +if (!pass) { +hmat_update_access (type, value, &best); +pr_info (" Initiator-Target[%d-%d]:%d%s\n" , + inits[init], targs[targ], value, +hmat_data_type_suffix (type)); +continue ; + } + +if (!t) +continue ; + p_node =pxm_to_node (inits[init]); +if (p_node !=NUMA_NO_NODE && value == best) +set_bit (p_node, t->p_nodes); + } } }return 0 ;
@@ -122,6 +194,7 @@ static int __init hmat_parse_address_range(union acpi_subtable_headers *header, const unsigned long end) {struct acpi_hmat_address_range *spa = (void *)header; +struct memory_target *t =NULL ;if (spa->header.length !=sizeof (*spa)) { pr_err("HMAT: Unexpected address range header length: %d\n",
@@ -131,6 +204,23 @@ static int __init hmat_parse_address_range(union acpi_subtable_headers *header,pr_info ("HMAT: Memory (%#llx length %#llx) Flags:%04x Processor Domain:%d Memory Domain:%d\n" , spa->physical_address_base, spa->physical_address_length, spa->flags, spa->processor_PD, spa->memory_PD); + +if (spa->flags &ACPI_HMAT_MEMORY_PD_VALID ) { + t =find_mem_target (spa->memory_PD); +if (!t) { +pr_warn ("HMAT: Memory Domain missing from SRAT\n" ); +return -EINVAL ; + } + } +if (t && spa->flags &ACPI_HMAT_PROCESSOR_PD_VALID ) { +int p_node =pxm_to_node (spa->processor_PD); + +if (p_node ==NUMA_NO_NODE ) { +pr_warn ("HMAT: Invalid Processor Domain\n" ); +return -EINVAL ; + } +set_bit (p_node, t->p_nodes); + }return 0 ; }
@@ -154,6 +244,33 @@ static int __init hmat_parse_subtable(union acpi_subtable_headers *header, } } +static __init int srat_parse_mem_affinity (union acpi_subtable_headers *header, +const unsigned long end) +{ +struct acpi_srat_mem_affinity *ma = (void *)header; + +if (!ma) +return -EINVAL ; +if (!(ma->flags &ACPI_SRAT_MEM_ENABLED )) +return 0 ; +alloc_memory_target (ma->proximity_domain); +return 0 ; +} + +static __init void hmat_register_targets (void ) +{ +struct memory_target *t, *next; +unsigned m, p; + +list_for_each_entry_safe (t, next, &targets, node) { +list_del (&t->node); + m =pxm_to_node (t->memory_pxm); +for_each_set_bit (p, t->p_nodes,MAX_NUMNODES ) +register_memory_node_under_compute_node (m, p,0 ); +kfree (t); + } +} +static __init int hmat_init (void ) {struct acpi_table_header *tbl;
@@ -163,6 +280,17 @@ static __init int hmat_init(void)if (srat_disabled ())return 0 ; + status =acpi_get_table (ACPI_SIG_SRAT ,0 , &tbl); +if (ACPI_FAILURE (status)) +return 0 ; + +if (acpi_table_parse_entries (ACPI_SIG_SRAT , +sizeof (struct acpi_table_srat ), +ACPI_SRAT_TYPE_MEMORY_AFFINITY , + srat_parse_mem_affinity,0 ) <0 ) + goto out_put; +acpi_put_table (tbl); + status =acpi_get_table (ACPI_SIG_HMAT ,0 , &tbl);if (ACPI_FAILURE (status))return 0 ;
@@ -173,6 +301,7 @@ static __init int hmat_init(void) hmat_parse_subtable, 0) < 0) goto out_put; } +hmat_register_targets (); out_put:acpi_put_table (tbl);return 0 ;
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 06/13] acpi/hmat: Register processor domain to its memory
Quoted 8 lines · Keith Busch
If the HMAT Subsystem Address Range provides a valid processor proximity domain for a memory domain, or a processor domain with the highest performing access exists, register the memory target with that initiator so this relationship will be visible under the node's sysfs directory.
Since HMAT requires valid address ranges have an equivalent SRAT entry, verify each memory target satisfies this requirement.
What exactly will happen after this patch?
There will be some new directories under /sys/devices/system/node/nodeX/ if all goes well. Anything else?
Quoted 10 lines
Signed-off-by Keith Busch <[email protected]>--- drivers/acpi/hmat/hmat.c | 143 ++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 136 insertions(+), 7 deletions(-)drivers/acpi/hmat/hmat.c +0
-0
drivers/acpi/hmat/hmat.c line 21
Quoted 5 lines
drivers/acpi/hmat/hmat.c +2
-0@@ -17,6 +17,43 @@#include <linux/slab.h> #include <linux/sysfs.h> +static LIST_HEAD (targets); +
A kerneldoc documenting the struct type here, please.
drivers/acpi/hmat/hmat.c line 28
Quoted 7 lines
drivers/acpi/hmat/hmat.c +7
-0+struct memory_target { +struct list_head node; +unsigned int memory_pxm; +unsigned long p_nodes[BITS_TO_LONGS (MAX_NUMNODES )]; +}; + +static __init struct memory_target *find_mem_target (unsigned int m)
Why don't you call the arg mem_pxm like below?
Quoted 32 lines
drivers/acpi/hmat/hmat.c +28
-0+{ +struct memory_target *t; + +list_for_each_entry (t, &targets, node) +if (t->memory_pxm == m) +return t; +return NULL ; +} + +static __init void alloc_memory_target (unsigned int mem_pxm) +{ +struct memory_target *t; + +if (pxm_to_node (mem_pxm) ==NUMA_NO_NODE ) +return ; + + t =find_mem_target (mem_pxm); +if (t) +return ; + + t =kzalloc (sizeof (*t),GFP_KERNEL ); +if (!t) +return ; + + t->memory_pxm = mem_pxm; +list_add_tail (&t->node, &targets); +} +static __init const char *hmat_data_type (u8 type) {switch (type) {
drivers/acpi/hmat/hmat.c static __init const char *hmat_data_type_suffix(u8 type) · line 93
Quoted 4 lines
drivers/acpi/hmat/hmat.c +1
-0@@ -53,11 +90,30 @@ static __init const char *hmat_data_type_suffix(u8 type) }; } +static __init void hmat_update_access (u8 type,u32 value,u32 *best)
I guess that you pass a pointer to avoid unnecessary updates, right?
But that causes you to dereference that pointer quite often. It might be better to pass the current value of 'best' and return an updated one (which may be the same as the passed one, of course).
Quoted 11 lines
drivers/acpi/hmat/hmat.c +11
-0+{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : +case ACPI_HMAT_READ_LATENCY : +case ACPI_HMAT_WRITE_LATENCY : +if (!*best || *best > value) + *best = value; +break ; +case ACPI_HMAT_ACCESS_BANDWIDTH : +case ACPI_HMAT_READ_BANDWIDTH : +case ACPI_HMAT_WRITE_BANDWIDTH :
drivers/acpi/hmat/hmat.c static __init const char *hmat_data_type_suffix(u8 type) · line 114
Quoted 10 lines
drivers/acpi/hmat/hmat.c +7
-0+if (!*best || *best < value) + *best = value; +break ; + } +} +static __init int hmat_parse_locality (union acpi_subtable_headers *header,const unsigned long end) { +struct memory_target *t;
I would call this variable mem_target. 't' is too easy to overlook IMO. [Same below]
Quoted 50 lines
drivers/acpi/hmat/hmat.c +24
-7struct acpi_hmat_locality *loc = (void *)header; -unsigned int init, targ, total_size, ipds, tpds; +unsigned int init, targ, pass, p_node, total_size, ipds, tpds;u32 *inits, *targs, value;u16 *entries;u8 type;@@ -87,12 +143,28 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header, targs = &inits[ipds]; entries = (u16 *)(&targs[tpds]);for (targ =0 ; targ < tpds; targ++) { -for (init =0 ; init < ipds; init++) { - value = entries[init * tpds + targ]; - value = (value * loc->entry_base_unit) /10 ; -pr_info (" Initiator-Target[%d-%d]:%d%s\n" , - inits[init], targs[targ], value, -hmat_data_type_suffix (type)); +u32 best =0 ; + + t =find_mem_target (targs[targ]); +for (pass =0 ; pass <2 ; pass++) { +for (init =0 ; init < ipds; init++) { + value = entries[init * tpds + targ]; + value = (value * loc->entry_base_unit) /10 ; + +if (!pass) { +hmat_update_access (type, value, &best); +pr_info (" Initiator-Target[%d-%d]:%d%s\n" , + inits[init], targs[targ], value, +hmat_data_type_suffix (type)); +continue ; + } + +if (!t) +continue ; + p_node =pxm_to_node (inits[init]); +if (p_node !=NUMA_NO_NODE && value == best) +set_bit (p_node, t->p_nodes); + } } }return 0 ;@@ -122,6 +194,7 @@ static int __init hmat_parse_address_range(union acpi_subtable_headers *header, const unsigned long end) {struct acpi_hmat_address_range *spa = (void *)header; +struct memory_target *t =NULL ;if (spa->header.length !=sizeof (*spa)) { pr_err("HMAT: Unexpected address range header length: %d\n",
drivers/acpi/hmat/hmat.c static int __init hmat_parse_address_range(union acpi_subtable_headers *header, · line 211
Quoted 8 lines
drivers/acpi/hmat/hmat.c +5
-0@@ -131,6 +204,23 @@ static int __init hmat_parse_address_range(union acpi_subtable_headers *header,pr_info ("HMAT: Memory (%#llx length %#llx) Flags:%04x Processor Domain:%d Memory Domain:%d\n" , spa->physical_address_base, spa->physical_address_length, spa->flags, spa->processor_PD, spa->memory_PD); + +if (spa->flags &ACPI_HMAT_MEMORY_PD_VALID ) { + t =find_mem_target (spa->memory_PD); +if (!t) { +pr_warn ("HMAT: Memory Domain missing from SRAT\n" );
Again, I'm wondering about the log level here. I "warning" really adequate?
drivers/acpi/hmat/hmat.c static int __init hmat_parse_address_range(union acpi_subtable_headers *header, · line 219
Quoted 8 lines
drivers/acpi/hmat/hmat.c +8
-0+return -EINVAL ; + } + } +if (t && spa->flags &ACPI_HMAT_PROCESSOR_PD_VALID ) { +int p_node =pxm_to_node (spa->processor_PD); + +if (p_node ==NUMA_NO_NODE ) { +pr_warn ("HMAT: Invalid Processor Domain\n" );
Same here.
Quoted 43 lines
drivers/acpi/hmat/hmat.c +31
-0+return -EINVAL ; + } +set_bit (p_node, t->p_nodes); + }return 0 ; }@@ -154,6 +244,33 @@ static int __init hmat_parse_subtable(union acpi_subtable_headers *header, } } +static __init int srat_parse_mem_affinity (union acpi_subtable_headers *header, +const unsigned long end) +{ +struct acpi_srat_mem_affinity *ma = (void *)header; + +if (!ma) +return -EINVAL ; +if (!(ma->flags &ACPI_SRAT_MEM_ENABLED )) +return 0 ; +alloc_memory_target (ma->proximity_domain); +return 0 ; +} + +static __init void hmat_register_targets (void ) +{ +struct memory_target *t, *next; +unsigned m, p; + +list_for_each_entry_safe (t, next, &targets, node) { +list_del (&t->node); + m =pxm_to_node (t->memory_pxm); +for_each_set_bit (p, t->p_nodes,MAX_NUMNODES ) +register_memory_node_under_compute_node (m, p,0 ); +kfree (t); + } +} +static __init int hmat_init (void ) {struct acpi_table_header *tbl;@@ -163,6 +280,17 @@ static __init int hmat_init(void)if (srat_disabled ())
drivers/acpi/hmat/hmat.c static __init int hmat_init(void) · line 290
Quoted 10 lines
drivers/acpi/hmat/hmat.c +8
-0return 0 ; + status =acpi_get_table (ACPI_SIG_SRAT ,0 , &tbl); +if (ACPI_FAILURE (status)) +return 0 ; + +if (acpi_table_parse_entries (ACPI_SIG_SRAT , +sizeof (struct acpi_table_srat ), +ACPI_SRAT_TYPE_MEMORY_AFFINITY , + srat_parse_mem_affinity,0 ) <0 )
Can you do
ret = acpi_table_parse_entries(ACPI_SIG_SRAT, sizeof(struct acpi_table_srat),
ACPI_SRAT_TYPE_MEMORY_AFFINITY,srat_parse_mem_affinity, 0);
if (ret < 0)
goto out_put;
here instead? The current one is barely readable.
Also please add a comment to explain what it means if this returns an error.
Quoted 15 lines
drivers/acpi/hmat/hmat.c +4
-1+ goto out_put; +acpi_put_table (tbl); + status =acpi_get_table (ACPI_SIG_HMAT ,0 , &tbl);if (ACPI_FAILURE (status))return 0 ;@@ -173,6 +301,7 @@ static __init int hmat_init(void) hmat_parse_subtable, 0) < 0) goto out_put; } +hmat_register_targets (); out_put:acpi_put_table (tbl);return 0 ; --
Re: [PATCHv4 06/13] acpi/hmat: Register processor domain to its memory
Quoted 8 lines · Rafael J. Wysocki
Quoted 6 lines · Keith Busch
If the HMAT Subsystem Address Range provides a valid processor proximity domain for a memory domain, or a processor domain with the highest performing access exists, register the memory target with that initiator so this relationship will be visible under the node's sysfs directory.
Quoted 7 lines
Quoted 2 lines
Since HMAT requires valid address ranges have an equivalent SRAT entry, verify each memory target satisfies this requirement.
What exactly will happen after this patch?
There will be some new directories under
/sys/devices/system/node/nodeX/if all goes well. Anything else?
When / if the memory randomization series [1] makes its way upstream there will be a follow-on patch to enable that randomization based on the presence of a memory-side cache published in the HMAT.
PATCH v4 7/13 node: Add heterogenous memory access attributes
In reply to Keith BuschHeterogeneous memory systems provide memory nodes with different latency and bandwidth performance attributes. Provide a new kernel interface for subsystems to register the attributes under the memory target node's initiator access class. If the system provides this information, applications may query these attributes when deciding which node to request memory.
The following example shows the new sysfs hierarchy for a node exporting performance attributes:
# tree -P "read*|write*" /sys/devices/system/node/nodeY/classZ/ /sys/devices/system/node/nodeY/classZ/ |-- read_bandwidth |-- read_latency |-- write_bandwidth `-- write_latency
The bandwidth is exported as MB/s and latency is reported in nanoseconds. Memory accesses from an initiator node that is not one of the memory's class "Z" initiator nodes may encounter different performance than reported here. When a subsystem makes use of this interface, initiators of a lower class number, "Z", have better performance relative to higher class numbers. When provided, class 0 is the highest performing access class.
--- drivers/base/Kconfig | 8 ++++++++ drivers/base/node.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 25 +++++++++++++++++++++++++ 3 files changed, 81 insertions(+)
drivers/base/Kconfig +8 -0
@@ -149,6 +149,14 @@ config DEBUG_TEST_DRIVER_REMOVE unusable. You should say N here unless you are explicitly looking to test this functionality. +config HMEM_REPORTING + bool + default y + depends on NUMA + help + Enable reporting for heterogenous memory access attributes under + their non-uniform memory nodes. + source "drivers/base/test/Kconfig" config SYS_HYPERVISOR
drivers/base/node.c +48 -0
60 lines not on this page · raw message
include/linux/node.h +25 -0
@@ -20,6 +20,31 @@#include <linux/list.h> #include <linux/workqueue.h> +#ifdef CONFIG_HMEM_REPORTING +/** +* struct node_hmem_attrs - heterogeneous memory performance attributes +* +* @read_bandwidth: Read bandwidth in MB/s +* @write_bandwidth: Write bandwidth in MB/s +* @read_latency: Read latency in nanoseconds +* @write_latency: Write latency in nanoseconds +*/ +struct node_hmem_attrs { +unsigned int read_bandwidth; +unsigned int write_bandwidth; +unsigned int read_latency; +unsigned int write_latency; +}; +void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs, +unsigned class); +#else +static inline void node_set_perf_attrs (unsigned int nid, +struct node_hmem_attrs *hmem_attrs, +unsigned class) +{ +} +#endif +struct node {struct device dev;struct list_head class_list;
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 07/13] node: Add heterogenous memory access attributes
Quoted 37 lines · Keith Busch
Heterogeneous memory systems provide memory nodes with different latency and bandwidth performance attributes. Provide a new kernel interface for subsystems to register the attributes under the memory target node's initiator access class. If the system provides this information, applications may query these attributes when deciding which node to request memory.
The following example shows the new sysfs hierarchy for a node exporting performance attributes:
# tree -P "read*|write*" /sys/devices/system/node/nodeY/classZ/ /sys/devices/system/node/nodeY/classZ/ |-- read_bandwidth |-- read_latency |-- write_bandwidth `-- write_latencyThe bandwidth is exported as MB/s and latency is reported in nanoseconds. Memory accesses from an initiator node that is not one of the memory's class "Z" initiator nodes may encounter different performance than reported here. When a subsystem makes use of this interface, initiators of a lower class number, "Z", have better performance relative to higher class numbers. When provided, class 0 is the highest performing access class.
Signed-off-by Keith Busch <[email protected]>--- drivers/base/Kconfig | 8 ++++++++ drivers/base/node.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 25 +++++++++++++++++++++++++ 3 files changed, 81 insertions(+)drivers/base/Kconfig +0
-0
drivers/base/Kconfig config DEBUG_TEST_DRIVER_REMOVE · line 158
Quoted 10 lines
drivers/base/Kconfig +7
-0@@ -149,6 +149,14 @@ config DEBUG_TEST_DRIVER_REMOVE unusable. You should say N here unless you are explicitly looking to test this functionality. +config HMEM_REPORTING + bool + default y + depends on NUMA + help + Enable reporting for heterogenous memory access attributes under + their non-uniform memory nodes.
Why would anyone ever want to say "no" to this?
Distros will set it anyway.
Quoted 36 lines
drivers/base/Kconfig +1
-0+ source "drivers/base/test/Kconfig" config SYS_HYPERVISORdrivers/base/node.c +17
-0@@ -66,6 +66,9 @@ struct node_class_nodes {unsigned class;nodemask_t initiator_nodes;nodemask_t target_nodes; +#ifdef CONFIG_HMEM_REPORTING +struct node_hmem_attrs hmem_attrs; +#endif };#define to_class_nodes (dev) container_of(dev, struct node_class_nodes, dev)@@ -145,6 +148,51 @@ static struct node_class_nodes *node_init_node_class(struct device *parent,return NULL ; } +#ifdef CONFIG_HMEM_REPORTING +#define ACCESS_ATTR (name) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + return sprintf(buf, "%u\n", to_class_nodes(dev)->hmem_attrs.name); \ +} \ +static DEVICE_ATTR_RO(name); + +ACCESS_ATTR(read_bandwidth) +ACCESS_ATTR(read_latency) +ACCESS_ATTR(write_bandwidth) +ACCESS_ATTR(write_latency)
drivers/base/node.c static struct node_class_nodes *node_init_node_class(struct device *parent, · line 174
Quoted 10 lines
drivers/base/node.c +10
-0+ +static struct attribute *access_attrs[] = { + &dev_attr_read_bandwidth.attr, + &dev_attr_read_latency.attr, + &dev_attr_write_bandwidth.attr, + &dev_attr_write_latency.attr, +NULL , +}; +ATTRIBUTE_GROUPS (access); +
Kerneldoc?
And who is going to call this?
Quoted 45 lines
drivers/base/node.c +21
-0+void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs, +unsigned class) +{ +struct node_class_nodes *c; +struct node *node; + +if (WARN_ON_ONCE (!node_online (nid))) +return ; + + node = node_devices[nid]; + c =node_init_node_class (&node->dev, &node->class_list, class); +if (!c) +return ; + + c->hmem_attrs = *hmem_attrs; +if (sysfs_create_groups (&c->dev.kobj, access_groups)) +pr_info ("failed to add performance attribute group to node %d\n" , + nid); +} +#endif +#define K (x) ((x) << (PAGE_SHIFT - 10))static ssize_t node_read_meminfo (struct device *dev,struct device_attribute *attr,char *buf)include/linux/node.h +13
-0@@ -20,6 +20,31 @@#include <linux/list.h> #include <linux/workqueue.h> +#ifdef CONFIG_HMEM_REPORTING +/** + * struct node_hmem_attrs - heterogeneous memory performance attributes + * + * @read_bandwidth: Read bandwidth in MB/s + * @write_bandwidth: Write bandwidth in MB/s + * @read_latency: Read latency in nanoseconds + * @write_latency: Write latency in nanoseconds + */ +struct node_hmem_attrs { + unsigned int read_bandwidth; + unsigned int write_bandwidth; + unsigned int read_latency;
include/linux/node.h line 45
Quoted 10 lines
include/linux/node.h +10
-0+ unsigned int write_latency; +}; +void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs, +unsigned class); +#else +static inline void node_set_perf_attrs (unsigned int nid, +struct node_hmem_attrs *hmem_attrs, +unsigned class) +{ +}
Have you tried to compile this with CONFIG_HMEM_REPORTING unset?
Quoted 6 lines
include/linux/node.h +2
-1+#endif +struct node {struct device dev;struct list_head class_list; --
Greg Kroah-Hartman
maintainerRe: [PATCHv4 07/13] node: Add heterogenous memory access attributes
Quoted 41 lines · Rafael J. Wysocki
Quoted 40 lines · Keith Busch
Heterogeneous memory systems provide memory nodes with different latency and bandwidth performance attributes. Provide a new kernel interface for subsystems to register the attributes under the memory target node's initiator access class. If the system provides this information, applications may query these attributes when deciding which node to request memory.
The following example shows the new sysfs hierarchy for a node exporting performance attributes:
# tree -P "read*|write*" /sys/devices/system/node/nodeY/classZ/ /sys/devices/system/node/nodeY/classZ/ |-- read_bandwidth |-- read_latency |-- write_bandwidth `-- write_latencyThe bandwidth is exported as MB/s and latency is reported in nanoseconds. Memory accesses from an initiator node that is not one of the memory's class "Z" initiator nodes may encounter different performance than reported here. When a subsystem makes use of this interface, initiators of a lower class number, "Z", have better performance relative to higher class numbers. When provided, class 0 is the highest performing access class.
Signed-off-by Keith Busch <[email protected]>--- drivers/base/Kconfig | 8 ++++++++ drivers/base/node.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 25 +++++++++++++++++++++++++ 3 files changed, 81 insertions(+)drivers/base/Kconfig +0
-0@@ -149,6 +149,14 @@ config DEBUG_TEST_DRIVER_REMOVE unusable. You should say N here unless you are explicitly looking to test this functionality.
Quoted 3 lines
drivers/base/Kconfig config DEBUG_TEST_DRIVER_REMOVE · line 154
Quoted 3 lines
drivers/base/Kconfig +3
-0+config HMEM_REPORTING + bool + default y
default y is only if the machine will not boot without it. Please never make a new option y unless you really really have to have it on all machines in the world.
Hint, not here.
greg k-h
PATCH v4 8/13 Documentation/ABI: Add node performance attributes
In reply to Keith BuschAdd descriptions for memory class initiator performance access attributes.
--- Documentation/ABI/stable/sysfs-devices-node | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)
Documentation/ABI/stable/sysfs-devices-node +28 -0
@@ -114,3 +114,31 @@ Description: The node list of memory targets that this initiator node has class "Y" access. Memory accesses from this node to nodes not in this list may have differet performance. + +What: /sys/devices/system/node/nodeX/classY/read_bandwidth +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's read bandwidth in MB/s available to memory + initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/classY/read_latency +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's read latency in nanoseconds available to memory + initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/classY/write_bandwidth +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's write bandwidth in MB/s available to memory + initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/classY/write_latency +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's write latency in nanoseconds available to memory + initiators in nodes found in this class's initiators_nodelist.
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 08/13] Documentation/ABI: Add node performance attributes
Quoted 2 lines · Keith Busch
Add descriptions for memory class initiator performance access attributes.
Again, I would combine this with the previous patch.
Quoted 17 lines
Signed-off-by Keith Busch <[email protected]>--- Documentation/ABI/stable/sysfs-devices-node | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+)Documentation/ABI/stable/sysfs-devices-node +4
-0@@ -114,3 +114,31 @@ Description: The node list of memory targets that this initiator node has class "Y" access. Memory accesses from this node to nodes not in this list may have differet performance. + +What: /sys/devices/system/node/nodeX/classY/read_bandwidth +Date: December 2018 +Contact: Keith Busch <[email protected]>
Documentation/ABI/stable/sysfs-devices-node Description: · line 130
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +10
-0+Description: + This node's read bandwidth in MB/s available to memory + initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/classY/read_latency +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's read latency in nanoseconds available to memory + initiators in nodes found in this class's initiators_nodelist.
I'm not sure if the term "read latency" is sufficient here. Is this the latency between sending a request and getting a response or between sending the request and when the data actually becomes available?
Moreover, is it the worst-case latency or the average latency?
Quoted 5 lines
Documentation/ABI/stable/sysfs-devices-node +5
-0+ +What: /sys/devices/system/node/nodeX/classY/write_bandwidth +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description:
Documentation/ABI/stable/sysfs-devices-node Description:
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +9
-1+ This node's write bandwidth in MB/s available to memory + initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/classY/write_latency +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This node's write latency in nanoseconds available to memory + initiators in nodes found in this class's initiators_nodelist. --
Same questions as for the read latency apply here.
PATCH v4 9/13 acpi/hmat: Register performance attributes
In reply to Keith BuschSave the best performace access attributes and register these with the memory's node if HMAT provides the locality table. While HMAT does make it possible to know performance for all possible initiator-target pairings, we export only the best pairings at this time.
--- drivers/acpi/hmat/Kconfig | 1 + drivers/acpi/hmat/hmat.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)
drivers/acpi/hmat/Kconfig +1 -0
@@ -2,6 +2,7 @@ config ACPI_HMAT bool "ACPI Heterogeneous Memory Attribute Table Support" depends on ACPI_NUMA + select HMEM_REPORTING help Parses representation of the ACPI Heterogeneous Memory Attributes Table (HMAT) and set the memory node relationships and access
drivers/acpi/hmat/hmat.c +34 -0
@@ -23,6 +23,8 @@ struct memory_target {struct list_head node;unsigned int memory_pxm;unsigned long p_nodes[BITS_TO_LONGS (MAX_NUMNODES )]; +bool hmem_valid; +struct node_hmem_attrs hmem; };static __init struct memory_target *find_mem_target (unsigned int m)
@@ -108,6 +110,34 @@ static __init void hmat_update_access(u8 type, u32 value, u32 *best) } } +static __init void hmat_update_target (struct memory_target *t,u8 type, +u32 value) +{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : + t->hmem.read_latency = value; + t->hmem.write_latency = value; +break ; +case ACPI_HMAT_READ_LATENCY : + t->hmem.read_latency = value; +break ; +case ACPI_HMAT_WRITE_LATENCY : + t->hmem.write_latency = value; +break ; +case ACPI_HMAT_ACCESS_BANDWIDTH : + t->hmem.read_bandwidth = value; + t->hmem.write_bandwidth = value; +break ; +case ACPI_HMAT_READ_BANDWIDTH : + t->hmem.read_bandwidth = value; +break ; +case ACPI_HMAT_WRITE_BANDWIDTH : + t->hmem.write_bandwidth = value; +break ; + } + t->hmem_valid = true; +} +static __init int hmat_parse_locality (union acpi_subtable_headers *header,const unsigned long end) {
@@ -166,6 +196,8 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,set_bit (p_node, t->p_nodes); } } +if (t && best) +hmat_update_target (t, type, best); }return 0 ; }
@@ -267,6 +299,8 @@ static __init void hmat_register_targets(void) m =pxm_to_node (t->memory_pxm);for_each_set_bit (p, t->p_nodes,MAX_NUMNODES )register_memory_node_under_compute_node (m, p,0 ); +if (t->hmem_valid) +node_set_perf_attrs (m, &t->hmem,0 );kfree (t); } }
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 09/13] acpi/hmat: Register performance attributes
Quoted 17 lines · Keith Busch
Save the best performace access attributes and register these with the memory's node if HMAT provides the locality table. While HMAT does make it possible to know performance for all possible initiator-target pairings, we export only the best pairings at this time.
Signed-off-by Keith Busch <[email protected]>--- drivers/acpi/hmat/Kconfig | 1 + drivers/acpi/hmat/hmat.c | 34 ++++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)drivers/acpi/hmat/Kconfig +0
-0
drivers/acpi/hmat/Kconfig line 5
Quoted 4 lines
drivers/acpi/hmat/Kconfig +1
-0@@ -2,6 +2,7 @@ config ACPI_HMAT bool "ACPI Heterogeneous Memory Attribute Table Support" depends on ACPI_NUMA + select HMEM_REPORTING
If you want HMEM_REPORTING to be only set when ACPI_HMAT is set, then don't make HMEM_REPORTING user-selectable.
Quoted 36 lines
drivers/acpi/hmat/Kconfig +0
-0help Parses representation of the ACPI Heterogeneous Memory Attributes Table (HMAT) and set the memory node relationships and accessdrivers/acpi/hmat/hmat.c +18
-0@@ -23,6 +23,8 @@ struct memory_target {struct list_head node;unsigned int memory_pxm;unsigned long p_nodes[BITS_TO_LONGS (MAX_NUMNODES )]; +bool hmem_valid; +struct node_hmem_attrs hmem; };static __init struct memory_target *find_mem_target (unsigned int m)@@ -108,6 +110,34 @@ static __init void hmat_update_access(u8 type, u32 value, u32 *best) } } +static __init void hmat_update_target (struct memory_target *t,u8 type, +u32 value) +{ +switch (type) { +case ACPI_HMAT_ACCESS_LATENCY : + t->hmem.read_latency = value; + t->hmem.write_latency = value; +break ; +case ACPI_HMAT_READ_LATENCY : + t->hmem.read_latency = value; +break ; +case ACPI_HMAT_WRITE_LATENCY : + t->hmem.write_latency = value; +break ; +case ACPI_HMAT_ACCESS_BANDWIDTH : + t->hmem.read_bandwidth = value;
drivers/acpi/hmat/hmat.c static __init void hmat_update_access(u8 type, u32 value, u32 *best) · line 138
Quoted 10 lines
drivers/acpi/hmat/hmat.c +10
-0+ t->hmem.write_bandwidth = value; +break ; +case ACPI_HMAT_READ_BANDWIDTH : + t->hmem.read_bandwidth = value; +break ; +case ACPI_HMAT_WRITE_BANDWIDTH : + t->hmem.write_bandwidth = value; +break ; + } + t->hmem_valid = true;
What if 'type' is none of the above? After all these values come from the firmware and that need not be correct.
Do you still want to set hmem_valid in that case?
Quoted 24 lines
drivers/acpi/hmat/hmat.c +6
-1+} +static __init int hmat_parse_locality (union acpi_subtable_headers *header,const unsigned long end) {@@ -166,6 +196,8 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,set_bit (p_node, t->p_nodes); } } +if (t && best) +hmat_update_target (t, type, best); }return 0 ; }@@ -267,6 +299,8 @@ static __init void hmat_register_targets(void) m =pxm_to_node (t->memory_pxm);for_each_set_bit (p, t->p_nodes,MAX_NUMNODES )register_memory_node_under_compute_node (m, p,0 ); +if (t->hmem_valid) +node_set_perf_attrs (m, &t->hmem,0 );kfree (t); } } --
PATCH v4 10/13 node: Add memory caching attributes
In reply to Keith BuschSystem memory may have side caches to help improve access speed to frequently requested address ranges. While the system provided cache is transparent to the software accessing these memory ranges, applications can optimize their own access based on cache attributes.
Provide a new API for the kernel to register these memory side caches under the memory node that provides it.
The new sysfs representation is modeled from the existing cpu cacheinfo attributes, as seen from /sys/devices/system/cpu/cpuX/side_cache/. Unlike CPU cacheinfo, though, the node cache level is reported from the view of the memory. A higher number is nearer to the CPU, while lower levels are closer to the backing memory. Also unlike CPU cache, it is assumed the system will handle flushing any dirty cached memory to the last level on a power failure if the range is persistent memory.
The attributes we export are the cache size, the line size, associativity, and write back policy.
--- drivers/base/node.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 39 ++++++++++++++ 2 files changed, 181 insertions(+)
drivers/base/node.c +142 -0
@@ -191,6 +191,146 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,pr_info ("failed to add performance attribute group to node %d\n" , nid); } + +struct node_cache_info { +struct device dev; +struct list_head node; +struct node_cache_attrs cache_attrs; +}; +#define to_cache_info (device) container_of(device, struct node_cache_info, dev) + +#define CACHE_ATTR (name, fmt) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + return sprintf(buf, fmt "\n", to_cache_info(dev)->cache_attrs.name);\ +} \ +DEVICE_ATTR_RO(name); + +CACHE_ATTR(size, "%llu") +CACHE_ATTR(level, "%u") +CACHE_ATTR(line_size, "%u") +CACHE_ATTR(associativity, "%u") +CACHE_ATTR(write_policy, "%u") + +static struct attribute *cache_attrs[] = { + &dev_attr_level.attr, + &dev_attr_associativity.attr, + &dev_attr_size.attr, + &dev_attr_line_size.attr, + &dev_attr_write_policy.attr, +NULL , +}; +ATTRIBUTE_GROUPS (cache); + +static void node_cache_release (struct device *dev) +{ +kfree (dev); +} + +static void node_cacheinfo_release (struct device *dev) +{ +struct node_cache_info *info =to_cache_info (dev); +kfree (info); +} + +static void node_init_cache_dev (struct node *node) +{ +struct device *dev; + + dev =kzalloc (sizeof (*dev),GFP_KERNEL ); +if (!dev) +return ; + + dev->parent = &node->dev; + dev->release = node_cache_release; +if (dev_set_name (dev,"side_cache" )) + goto free_dev; + +if (device_register (dev)) + goto free_name; + +pm_runtime_no_callbacks (dev); + node->cache_dev = dev; +return ; +free_name: +kfree_const (dev->kobj.name); +free_dev: +kfree (dev); +} + +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs) +{ +struct node_cache_info *info; +struct device *dev; +struct node *node; + +if (!node_online (nid) || !node_devices[nid]) +return ; + + node = node_devices[nid]; +list_for_each_entry (info, &node->cache_attrs, node) { +if (info->cache_attrs.level == cache_attrs->level) { +dev_warn (&node->dev, +"attempt to add duplicate cache level:%d\n" , + cache_attrs->level); +return ; + } + } + +if (!node->cache_dev) +node_init_cache_dev (node); +if (!node->cache_dev) +return ; + + info =kzalloc (sizeof (*info),GFP_KERNEL ); +if (!info) +return ; + + dev = &info->dev; + dev->parent = node->cache_dev; + dev->release = node_cacheinfo_release; + dev->groups = cache_groups; +if (dev_set_name (dev,"index%d" , cache_attrs->level)) + goto free_cache; + + info->cache_attrs = *cache_attrs; +if (device_register (dev)) { +dev_warn (&node->dev,"failed to add cache level:%d\n" , + cache_attrs->level); + goto free_name; + } +pm_runtime_no_callbacks (dev); +list_add_tail (&info->node, &node->cache_attrs); +return ; +free_name: +kfree_const (dev->kobj.name); +free_cache: +kfree (info); +} + +static void node_remove_caches (struct node *node) +{ +struct node_cache_info *info, *next; + +if (!node->cache_dev) +return ; + +list_for_each_entry_safe (info, next, &node->cache_attrs, node) { +list_del (&info->node); +device_unregister (&info->dev); + } +device_unregister (node->cache_dev); +} + +static void node_init_caches (unsigned int nid) +{ +INIT_LIST_HEAD (&node_devices[nid]->cache_attrs); +} +#else +static void node_init_caches (unsigned int nid) { } +static void node_remove_caches (struct node *node) { }#endif #define K (x) ((x) << (PAGE_SHIFT - 10))
@@ -475,6 +615,7 @@ void unregister_node(struct node *node) {hugetlb_unregister_node (node);/* no-op, if memoryless node */ node_remove_classes (node); +node_remove_caches (node);device_unregister (&node->dev); }
@@ -755,6 +896,7 @@ int __register_one_node(int nid)INIT_LIST_HEAD (&node_devices[nid]->class_list);/* initialize work queue for memory hot plug */ init_node_hugetlb_work (nid); +node_init_caches (nid);return error; }
include/linux/node.h +39 -0
@@ -37,12 +37,47 @@ struct node_hmem_attrs { };void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class); + +enum cache_associativity { +NODE_CACHE_DIRECT_MAP , +NODE_CACHE_INDEXED , +NODE_CACHE_OTHER , +}; + +enum cache_write_policy { +NODE_CACHE_WRITE_BACK , +NODE_CACHE_WRITE_THROUGH , +NODE_CACHE_WRITE_OTHER , +}; + +/** +* struct node_cache_attrs - system memory caching attributes +* +* @associativity: The ways memory blocks may be placed in cache +* @write_policy: Write back or write through policy +* @size: Total size of cache in bytes +* @line_size: Number of bytes fetched on a cache miss +* @level: Represents the cache hierarchy level +*/ +struct node_cache_attrs { +enum cache_associativity associativity; +enum cache_write_policy write_policy; +u64 size; +u16 line_size; +u8 level; +}; +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs);#else static inline void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class) { } + +static inline void node_add_cache (unsigned int nid, +struct node_cache_attrs *cache_attrs) +{ +}#endif struct node {
@@ -51,6 +86,10 @@ struct node {#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE ) && defined(CONFIG_HUGETLBFS )struct work_struct node_work;#endif +#ifdef CONFIG_HMEM_REPORTING +struct list_head cache_attrs; +struct device *cache_dev; +#endif };struct memory_block ;
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 10/13] node: Add memory caching attributes
Quoted 87 lines · Keith Busch
System memory may have side caches to help improve access speed to frequently requested address ranges. While the system provided cache is transparent to the software accessing these memory ranges, applications can optimize their own access based on cache attributes.
Provide a new API for the kernel to register these memory side caches under the memory node that provides it.
The new sysfs representation is modeled from the existing cpu cacheinfo attributes, as seen from
/sys/devices/system/cpu/cpuX/side_cache/. Unlike CPU cacheinfo, though, the node cache level is reported from the view of the memory. A higher number is nearer to the CPU, while lower levels are closer to the backing memory. Also unlike CPU cache, it is assumed the system will handle flushing any dirty cached memory to the last level on a power failure if the range is persistent memory.The attributes we export are the cache size, the line size, associativity, and write back policy.
Signed-off-by Keith Busch <[email protected]>--- drivers/base/node.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 39 ++++++++++++++ 2 files changed, 181 insertions(+)drivers/base/node.c +53
-0@@ -191,6 +191,146 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,pr_info ("failed to add performance attribute group to node %d\n" , nid); } + +struct node_cache_info { +struct device dev; +struct list_head node; +struct node_cache_attrs cache_attrs; +}; +#define to_cache_info (device) container_of(device, struct node_cache_info, dev) + +#define CACHE_ATTR (name, fmt) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + return sprintf(buf, fmt "\n", to_cache_info(dev)->cache_attrs.name);\ +} \ +DEVICE_ATTR_RO(name); + +CACHE_ATTR(size, "%llu") +CACHE_ATTR(level, "%u") +CACHE_ATTR(line_size, "%u") +CACHE_ATTR(associativity, "%u") +CACHE_ATTR(write_policy, "%u") + +static struct attribute *cache_attrs[] = { + &dev_attr_level.attr, + &dev_attr_associativity.attr, + &dev_attr_size.attr, + &dev_attr_line_size.attr, + &dev_attr_write_policy.attr, +NULL , +}; +ATTRIBUTE_GROUPS (cache); + +static void node_cache_release (struct device *dev) +{ +kfree (dev); +} + +static void node_cacheinfo_release (struct device *dev) +{ +struct node_cache_info *info =to_cache_info (dev); +kfree (info); +} + +static void node_init_cache_dev (struct node *node) +{ +struct device *dev; + + dev =kzalloc (sizeof (*dev),GFP_KERNEL ); +if (!dev) +return ; + + dev->parent = &node->dev;
drivers/base/node.c void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs, · line 256
Quoted 10 lines
drivers/base/node.c +10
-0+ dev->release = node_cache_release; +if (dev_set_name (dev,"side_cache" )) + goto free_dev; + +if (device_register (dev)) + goto free_name; + +pm_runtime_no_callbacks (dev); + node->cache_dev = dev; +return ;
I would add an empty line here.
Quoted 11 lines
drivers/base/node.c +11
-0+free_name: +kfree_const (dev->kobj.name); +free_dev: +kfree (dev); +} + +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs) +{ +struct node_cache_info *info; +struct device *dev; +struct node *node;
drivers/base/node.c void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs, · line 277
Quoted 10 lines
drivers/base/node.c +10
-0+ +if (!node_online (nid) || !node_devices[nid]) +return ; + + node = node_devices[nid]; +list_for_each_entry (info, &node->cache_attrs, node) { +if (info->cache_attrs.level == cache_attrs->level) { +dev_warn (&node->dev, +"attempt to add duplicate cache level:%d\n" , + cache_attrs->level);
I'd suggest using dev_dbg() for this and I'm not even sure if printing the message is worth the effort.
Firmware will probably give you duplicates and users cannot do much about fixing that anyway.
Quoted 19 lines
drivers/base/node.c +19
-0+return ; + } + } + +if (!node->cache_dev) +node_init_cache_dev (node); +if (!node->cache_dev) +return ; + + info =kzalloc (sizeof (*info),GFP_KERNEL ); +if (!info) +return ; + + dev = &info->dev; + dev->parent = node->cache_dev; + dev->release = node_cacheinfo_release; + dev->groups = cache_groups; +if (dev_set_name (dev,"index%d" , cache_attrs->level)) + goto free_cache;
drivers/base/node.c void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs, · line 306
Quoted 10 lines
drivers/base/node.c +10
-0+ + info->cache_attrs = *cache_attrs; +if (device_register (dev)) { +dev_warn (&node->dev,"failed to add cache level:%d\n" , + cache_attrs->level); + goto free_name; + } +pm_runtime_no_callbacks (dev); +list_add_tail (&info->node, &node->cache_attrs); +return ;
Again, I'd add an empty line here.
Quoted 85 lines
drivers/base/node.c +29
-0+free_name: +kfree_const (dev->kobj.name); +free_cache: + kfree(info); +} + +static void node_remove_caches (struct node *node) +{ +struct node_cache_info *info, *next; + +if (!node->cache_dev) +return ; + +list_for_each_entry_safe (info, next, &node->cache_attrs, node) { +list_del (&info->node); +device_unregister (&info->dev); + } +device_unregister (node->cache_dev); +} + +static void node_init_caches (unsigned int nid) +{ +INIT_LIST_HEAD (&node_devices[nid]->cache_attrs); +} +#else +static void node_init_caches (unsigned int nid) { } +static void node_remove_caches (struct node *node) { }#endif #define K (x) ((x) << (PAGE_SHIFT - 10))@@ -475,6 +615,7 @@ void unregister_node(struct node *node) {hugetlb_unregister_node (node);/* no-op, if memoryless node */ node_remove_classes (node); +node_remove_caches (node);device_unregister (&node->dev); }@@ -755,6 +896,7 @@ int __register_one_node(int nid)INIT_LIST_HEAD (&node_devices[nid]->class_list);/* initialize work queue for memory hot plug */ init_node_hugetlb_work (nid); +node_init_caches (nid);return error; }include/linux/node.h +30
-0@@ -37,12 +37,47 @@ struct node_hmem_attrs { };void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class); + +enum cache_associativity { +NODE_CACHE_DIRECT_MAP , +NODE_CACHE_INDEXED , +NODE_CACHE_OTHER , +}; + +enum cache_write_policy { +NODE_CACHE_WRITE_BACK , +NODE_CACHE_WRITE_THROUGH , +NODE_CACHE_WRITE_OTHER , +}; + +/** +* struct node_cache_attrs - system memory caching attributes +* +* @associativity: The ways memory blocks may be placed in cache +* @write_policy: Write back or write through policy +* @size: Total size of cache in bytes +* @line_size: Number of bytes fetched on a cache miss +* @level: Represents the cache hierarchy level +*/ +struct node_cache_attrs { +enum cache_associativity associativity; +enum cache_write_policy write_policy; +u64 size; +u16 line_size; +u8 level; +}; +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs);#else
include/linux/node.h struct node_hmem_attrs { · line 80
Quoted 10 lines
include/linux/node.h +5
-0static inline void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class) { } + +static inline void node_add_cache (unsigned int nid, +struct node_cache_attrs *cache_attrs) +{ +}
And does this really build with CONFIG_HMEM_REPORTING unset?
Quoted 15 lines
include/linux/node.h +4
-1#endif struct node {@@ -51,6 +86,10 @@ struct node {#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE ) && defined(CONFIG_HUGETLBFS )struct work_struct node_work;#endif +#ifdef CONFIG_HMEM_REPORTING +struct list_head cache_attrs; +struct device *cache_dev; +#endif };struct memory_block ; --
Re: [PATCHv4 10/13] node: Add memory caching attributes
In reply to Keith BuschHello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
Thanks
Brice
Le 16/01/2019 à 18:58, Keith Busch a écrit :
Quoted 255 lines
System memory may have side caches to help improve access speed to frequently requested address ranges. While the system provided cache is transparent to the software accessing these memory ranges, applications can optimize their own access based on cache attributes.
Provide a new API for the kernel to register these memory side caches under the memory node that provides it.
The new sysfs representation is modeled from the existing cpu cacheinfo attributes, as seen from
/sys/devices/system/cpu/cpuX/side_cache/. Unlike CPU cacheinfo, though, the node cache level is reported from the view of the memory. A higher number is nearer to the CPU, while lower levels are closer to the backing memory. Also unlike CPU cache, it is assumed the system will handle flushing any dirty cached memory to the last level on a power failure if the range is persistent memory.The attributes we export are the cache size, the line size, associativity, and write back policy.
Signed-off-by Keith Busch <[email protected]>--- drivers/base/node.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 39 ++++++++++++++ 2 files changed, 181 insertions(+)drivers/base/node.c +142
-0@@ -191,6 +191,146 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,pr_info ("failed to add performance attribute group to node %d\n" , nid); } + +struct node_cache_info { +struct device dev; +struct list_head node; +struct node_cache_attrs cache_attrs; +}; +#define to_cache_info (device) container_of(device, struct node_cache_info, dev) + +#define CACHE_ATTR (name, fmt) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + return sprintf(buf, fmt "\n", to_cache_info(dev)->cache_attrs.name);\ +} \ +DEVICE_ATTR_RO(name); + +CACHE_ATTR(size, "%llu") +CACHE_ATTR(level, "%u") +CACHE_ATTR(line_size, "%u") +CACHE_ATTR(associativity, "%u") +CACHE_ATTR(write_policy, "%u") + +static struct attribute *cache_attrs[] = { + &dev_attr_level.attr, + &dev_attr_associativity.attr, + &dev_attr_size.attr, + &dev_attr_line_size.attr, + &dev_attr_write_policy.attr, +NULL , +}; +ATTRIBUTE_GROUPS (cache); + +static void node_cache_release (struct device *dev) +{ +kfree (dev); +} + +static void node_cacheinfo_release (struct device *dev) +{ +struct node_cache_info *info =to_cache_info (dev); +kfree (info); +} + +static void node_init_cache_dev (struct node *node) +{ +struct device *dev; + + dev =kzalloc (sizeof (*dev),GFP_KERNEL ); +if (!dev) +return ; + + dev->parent = &node->dev; + dev->release = node_cache_release; +if (dev_set_name (dev,"side_cache" )) + goto free_dev; + +if (device_register (dev)) + goto free_name; + +pm_runtime_no_callbacks (dev); + node->cache_dev = dev; +return ; +free_name: +kfree_const (dev->kobj.name); +free_dev: +kfree (dev); +} + +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs) +{ +struct node_cache_info *info; +struct device *dev; +struct node *node; + +if (!node_online (nid) || !node_devices[nid]) +return ; + + node = node_devices[nid]; +list_for_each_entry (info, &node->cache_attrs, node) { +if (info->cache_attrs.level == cache_attrs->level) { +dev_warn (&node->dev, +"attempt to add duplicate cache level:%d\n" , + cache_attrs->level); +return ; + } + } + +if (!node->cache_dev) +node_init_cache_dev (node); +if (!node->cache_dev) +return ; + + info =kzalloc (sizeof (*info),GFP_KERNEL ); +if (!info) +return ; + + dev = &info->dev; + dev->parent = node->cache_dev; + dev->release = node_cacheinfo_release; + dev->groups = cache_groups; +if (dev_set_name (dev,"index%d" , cache_attrs->level)) + goto free_cache; + + info->cache_attrs = *cache_attrs; +if (device_register (dev)) { +dev_warn (&node->dev,"failed to add cache level:%d\n" , + cache_attrs->level); + goto free_name; + } +pm_runtime_no_callbacks (dev); +list_add_tail (&info->node, &node->cache_attrs); +return ; +free_name: +kfree_const (dev->kobj.name); +free_cache: +kfree (info); +} + +static void node_remove_caches (struct node *node) +{ +struct node_cache_info *info, *next; + +if (!node->cache_dev) +return ; + +list_for_each_entry_safe (info, next, &node->cache_attrs, node) { +list_del (&info->node); +device_unregister (&info->dev); + } +device_unregister (node->cache_dev); +} + +static void node_init_caches (unsigned int nid) +{ +INIT_LIST_HEAD (&node_devices[nid]->cache_attrs); +} +#else +static void node_init_caches (unsigned int nid) { } +static void node_remove_caches (struct node *node) { }#endif #define K (x) ((x) << (PAGE_SHIFT - 10))@@ -475,6 +615,7 @@ void unregister_node(struct node *node) {hugetlb_unregister_node (node);/* no-op, if memoryless node */ node_remove_classes (node); +node_remove_caches (node);device_unregister (&node->dev); }@@ -755,6 +896,7 @@ int __register_one_node(int nid)INIT_LIST_HEAD (&node_devices[nid]->class_list);/* initialize work queue for memory hot plug */ init_node_hugetlb_work (nid); +node_init_caches (nid);return error; }include/linux/node.h +39
-0@@ -37,12 +37,47 @@ struct node_hmem_attrs { };void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class); + +enum cache_associativity { +NODE_CACHE_DIRECT_MAP , +NODE_CACHE_INDEXED , +NODE_CACHE_OTHER , +}; + +enum cache_write_policy { +NODE_CACHE_WRITE_BACK , +NODE_CACHE_WRITE_THROUGH , +NODE_CACHE_WRITE_OTHER , +}; + +/** +* struct node_cache_attrs - system memory caching attributes +* +* @associativity: The ways memory blocks may be placed in cache +* @write_policy: Write back or write through policy +* @size: Total size of cache in bytes +* @line_size: Number of bytes fetched on a cache miss +* @level: Represents the cache hierarchy level +*/ +struct node_cache_attrs { +enum cache_associativity associativity; +enum cache_write_policy write_policy; +u64 size; +u16 line_size; +u8 level; +}; +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs);#else static inline void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class) { } + +static inline void node_add_cache (unsigned int nid, +struct node_cache_attrs *cache_attrs) +{ +}#endif struct node {@@ -51,6 +86,10 @@ struct node {#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE ) && defined(CONFIG_HUGETLBFS )struct work_struct node_work;#endif +#ifdef CONFIG_HMEM_REPORTING +struct list_head cache_attrs; +struct device *cache_dev; +#endif };struct memory_block ;
Re: [PATCHv4 10/13] node: Add memory caching attributes
Quoted 5 lines · On Sat, 9 Feb 2019 09:20:53 +0100 Brice Goglin <[email protected]> wrote:
Hello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
This is certainly a possible thing for hardware to do.
ACPI IIRC doesn't provide any means of representing that - your best option is to represent it as two different entries, one for each of the memory nodes. Interesting question of whether you would then claim they were half as big each, or the full size. Of course, there are other possible ways to get this info beyond HMAT, so perhaps the interface should allow it to be exposed if available?
Also, don't know if it's just me, but calling these sidecaches is downright confusing. In ACPI at least they are always specifically referred to as Memory Side Caches.
I'd argue there should even by a hyphen Memory-Side Caches, the point being that that they are on the memory side of the interconnected rather than the processor side. Of course an implementation choice might be to put them off to the side (as implied by sidecaches) in some sense, but it's not the only one.
</terminology rant> :)
Jonathan
Quoted 264 lines
Thanks
Brice
Le 16/01/2019 à 18:58, Keith Busch a écrit :
Quoted 255 lines
System memory may have side caches to help improve access speed to frequently requested address ranges. While the system provided cache is transparent to the software accessing these memory ranges, applications can optimize their own access based on cache attributes.
Provide a new API for the kernel to register these memory side caches under the memory node that provides it.
The new sysfs representation is modeled from the existing cpu cacheinfo attributes, as seen from
/sys/devices/system/cpu/cpuX/side_cache/. Unlike CPU cacheinfo, though, the node cache level is reported from the view of the memory. A higher number is nearer to the CPU, while lower levels are closer to the backing memory. Also unlike CPU cache, it is assumed the system will handle flushing any dirty cached memory to the last level on a power failure if the range is persistent memory.The attributes we export are the cache size, the line size, associativity, and write back policy.
Signed-off-by Keith Busch <[email protected]>--- drivers/base/node.c | 142 +++++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/node.h | 39 ++++++++++++++ 2 files changed, 181 insertions(+)drivers/base/node.c +142
-0@@ -191,6 +191,146 @@ void node_set_perf_attrs(unsigned int nid, struct node_hmem_attrs *hmem_attrs,pr_info ("failed to add performance attribute group to node %d\n" , nid); } + +struct node_cache_info { +struct device dev; +struct list_head node; +struct node_cache_attrs cache_attrs; +}; +#define to_cache_info (device) container_of(device, struct node_cache_info, dev) + +#define CACHE_ATTR (name, fmt) \ +static ssize_t name##_show(struct device *dev, \ + struct device_attribute *attr, \ + char *buf) \ +{ \ + return sprintf(buf, fmt "\n", to_cache_info(dev)->cache_attrs.name);\ +} \ +DEVICE_ATTR_RO(name); + +CACHE_ATTR(size, "%llu") +CACHE_ATTR(level, "%u") +CACHE_ATTR(line_size, "%u") +CACHE_ATTR(associativity, "%u") +CACHE_ATTR(write_policy, "%u") + +static struct attribute *cache_attrs[] = { + &dev_attr_level.attr, + &dev_attr_associativity.attr, + &dev_attr_size.attr, + &dev_attr_line_size.attr, + &dev_attr_write_policy.attr, +NULL , +}; +ATTRIBUTE_GROUPS (cache); + +static void node_cache_release (struct device *dev) +{ +kfree (dev); +} + +static void node_cacheinfo_release (struct device *dev) +{ +struct node_cache_info *info =to_cache_info (dev); +kfree (info); +} + +static void node_init_cache_dev (struct node *node) +{ +struct device *dev; + + dev =kzalloc (sizeof (*dev),GFP_KERNEL ); +if (!dev) +return ; + + dev->parent = &node->dev; + dev->release = node_cache_release; +if (dev_set_name (dev,"side_cache" )) + goto free_dev; + +if (device_register (dev)) + goto free_name; + +pm_runtime_no_callbacks (dev); + node->cache_dev = dev; +return ; +free_name: +kfree_const (dev->kobj.name); +free_dev: +kfree (dev); +} + +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs) +{ +struct node_cache_info *info; +struct device *dev; +struct node *node; + +if (!node_online (nid) || !node_devices[nid]) +return ; + + node = node_devices[nid]; +list_for_each_entry (info, &node->cache_attrs, node) { +if (info->cache_attrs.level == cache_attrs->level) { +dev_warn (&node->dev, +"attempt to add duplicate cache level:%d\n" , + cache_attrs->level); +return ; + } + } + +if (!node->cache_dev) +node_init_cache_dev (node); +if (!node->cache_dev) +return ; + + info =kzalloc (sizeof (*info),GFP_KERNEL ); +if (!info) +return ; + + dev = &info->dev; + dev->parent = node->cache_dev; + dev->release = node_cacheinfo_release; + dev->groups = cache_groups; +if (dev_set_name (dev,"index%d" , cache_attrs->level)) + goto free_cache; + + info->cache_attrs = *cache_attrs; +if (device_register (dev)) { +dev_warn (&node->dev,"failed to add cache level:%d\n" , + cache_attrs->level); + goto free_name; + } +pm_runtime_no_callbacks (dev); +list_add_tail (&info->node, &node->cache_attrs); +return ; +free_name: +kfree_const (dev->kobj.name); +free_cache: +kfree (info); +} + +static void node_remove_caches (struct node *node) +{ +struct node_cache_info *info, *next; + +if (!node->cache_dev) +return ; + +list_for_each_entry_safe (info, next, &node->cache_attrs, node) { +list_del (&info->node); +device_unregister (&info->dev); + } +device_unregister (node->cache_dev); +} + +static void node_init_caches (unsigned int nid) +{ +INIT_LIST_HEAD (&node_devices[nid]->cache_attrs); +} +#else +static void node_init_caches (unsigned int nid) { } +static void node_remove_caches (struct node *node) { }#endif #define K (x) ((x) << (PAGE_SHIFT - 10))@@ -475,6 +615,7 @@ void unregister_node(struct node *node) {hugetlb_unregister_node (node);/* no-op, if memoryless node */ node_remove_classes (node); +node_remove_caches (node);device_unregister (&node->dev); }@@ -755,6 +896,7 @@ int __register_one_node(int nid)INIT_LIST_HEAD (&node_devices[nid]->class_list);/* initialize work queue for memory hot plug */ init_node_hugetlb_work (nid); +node_init_caches (nid);return error; }include/linux/node.h +39
-0@@ -37,12 +37,47 @@ struct node_hmem_attrs { };void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class); + +enum cache_associativity { +NODE_CACHE_DIRECT_MAP , +NODE_CACHE_INDEXED , +NODE_CACHE_OTHER , +}; + +enum cache_write_policy { +NODE_CACHE_WRITE_BACK , +NODE_CACHE_WRITE_THROUGH , +NODE_CACHE_WRITE_OTHER , +}; + +/** +* struct node_cache_attrs - system memory caching attributes +* +* @associativity: The ways memory blocks may be placed in cache +* @write_policy: Write back or write through policy +* @size: Total size of cache in bytes +* @line_size: Number of bytes fetched on a cache miss +* @level: Represents the cache hierarchy level +*/ +struct node_cache_attrs { +enum cache_associativity associativity; +enum cache_write_policy write_policy; +u64 size; +u16 line_size; +u8 level; +}; +void node_add_cache (unsigned int nid,struct node_cache_attrs *cache_attrs);#else static inline void node_set_perf_attrs (unsigned int nid,struct node_hmem_attrs *hmem_attrs,unsigned class) { } + +static inline void node_add_cache (unsigned int nid, +struct node_cache_attrs *cache_attrs) +{ +}#endif struct node {@@ -51,6 +86,10 @@ struct node {#if defined(CONFIG_MEMORY_HOTPLUG_SPARSE ) && defined(CONFIG_HUGETLBFS )struct work_struct node_work;#endif +#ifdef CONFIG_HMEM_REPORTING +struct list_head cache_attrs; +struct device *cache_dev; +#endif };struct memory_block ;
Re: [PATCHv4 10/13] node: Add memory caching attributes
Quoted 9 lines · Jonathan Cameron
Quoted 5 lines · On Sat, 9 Feb 2019 09:20:53 +0100 Brice Goglin <[email protected]> wrote:
Hello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
Quoted 8 lines
This is certainly a possible thing for hardware to do.
ACPI IIRC doesn't provide any means of representing that - your best option is to represent it as two different entries, one for each of the memory nodes. Interesting question of whether you would then claim they were half as big each, or the full size. Of course, there are other possible ways to get this info beyond HMAT, so perhaps the interface should allow it to be exposed if available?
HMAT doesn't do this, but I want this interface abstracted enough from HMAT to express whatever is necessary.
The CPU cache is the closest existing exported attributes to this, and they provide "shared_cpu_list". To that end, I can export a "shared_node_list", though previous reviews strongly disliked multi-value sysfs entries. :(
Would shared-node symlinks capture the need, and more acceptable?
Quoted 10 lines
Also, don't know if it's just me, but calling these sidecaches is downright confusing. In ACPI at least they are always specifically referred to as Memory Side Caches.
I'd argue there should even by a hyphen Memory-Side Caches, the point being that that they are on the memory side of the interconnected rather than the processor side. Of course an implementation choice might be to put them off to the side (as implied by sidecaches) in some sense, but it's not the only one.</terminology rant> :)
Now that you mention it, I agree "side" is ambiguous. Maybe call it "numa_cache" or "node_cache"?
Re: [PATCHv4 10/13] node: Add memory caching attributes
Le 11/02/2019 à 16:23, Keith Busch a écrit :
Quoted 20 lines · Jonathan Cameron
Quoted 8 lines
Quoted 5 lines · On Sat, 9 Feb 2019 09:20:53 +0100 Brice Goglin <[email protected]> wrote:
Hello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
Quoted 8 lines
This is certainly a possible thing for hardware to do.
ACPI IIRC doesn't provide any means of representing that - your best option is to represent it as two different entries, one for each of the memory nodes. Interesting question of whether you would then claim they were half as big each, or the full size. Of course, there are other possible ways to get this info beyond HMAT, so perhaps the interface should allow it to be exposed if available?
HMAT doesn't do this, but I want this interface abstracted enough from HMAT to express whatever is necessary.
Quoted 6 lines
The CPU cache is the closest existing exported attributes to this, and they provide "
shared_cpu_list". To that end, I can export a "shared_node_list", though previous reviews strongly disliked multi-value sysfs entries. :(Would shared-node symlinks capture the need, and more acceptable?
As a user-space guy reading these files/symlinks, I would prefer reading a bitmask just like we do for CPU cache "cpumap" or CPU "siblings" files (or sibling_list).
Reading a directory and looking for dentries matching "foo%d" is far less convenient in C. If all these files are inside a dedicated subdirectory, it's better but still not as easy.
Brice
Re: [PATCHv4 10/13] node: Add memory caching attributes
In reply to Keith BuschQuoted 22 lines · On Mon, 11 Feb 2019 08:23:04 -0700 Keith Busch <[email protected]> wrote:
Quoted 9 lines · Jonathan Cameron
Quoted 5 lines · On Sat, 9 Feb 2019 09:20:53 +0100 Brice Goglin <[email protected]> wrote:
Hello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
Quoted 8 lines
This is certainly a possible thing for hardware to do.
ACPI IIRC doesn't provide any means of representing that - your best option is to represent it as two different entries, one for each of the memory nodes. Interesting question of whether you would then claim they were half as big each, or the full size. Of course, there are other possible ways to get this info beyond HMAT, so perhaps the interface should allow it to be exposed if available?
HMAT doesn't do this, but I want this interface abstracted enough from HMAT to express whatever is necessary.
Quoted 6 lines
The CPU cache is the closest existing exported attributes to this, and they provide "
shared_cpu_list". To that end, I can export a "shared_node_list", though previous reviews strongly disliked multi-value sysfs entries. :(Would shared-node symlinks capture the need, and more acceptable?
My inclination is that it's better to follow an existing pattern than invent a new one that breaks people's expectations.
However, don't feel that strongly about it as long as the interface is functional and intuitive.
Quoted 10 lines
Quoted 10 lines
Also, don't know if it's just me, but calling these sidecaches is downright confusing. In ACPI at least they are always specifically referred to as Memory Side Caches.
I'd argue there should even by a hyphen Memory-Side Caches, the point being that that they are on the memory side of the interconnected rather than the processor side. Of course an implementation choice might be to put them off to the side (as implied by sidecaches) in some sense, but it's not the only one.
Quoted 4 lines
Quoted 1 line
</terminology rant> :)
Now that you mention it, I agree "side" is ambiguous. Maybe call it "
numa_cache" or "node_cache"?
I'm not sure any of the options work well. My inclination would be to use the full name and keep the somewhat redundant memory there.
The other two feel like they could just as easily be coherent caches at accelerators for example...
memory_side_cache?
The fun of naming ;)
Jonathan
Re: [PATCHv4 10/13] node: Add memory caching attributes
Quoted 30 lines · Jonathan Cameron
Quoted 27 lines · On Mon, 11 Feb 2019 08:23:04 -0700 Keith Busch <[email protected]> wrote:
Quoted 9 lines · Jonathan Cameron
Quoted 5 lines · On Sat, 9 Feb 2019 09:20:53 +0100 Brice Goglin <[email protected]> wrote:
Hello Keith
Could we ever have a single side cache in front of two NUMA nodes ? I don't see a way to find that out in the current implementation. Would we have an "id" and/or "nodemap" bitmask in the sidecache structure ?
Quoted 8 lines
This is certainly a possible thing for hardware to do.
ACPI IIRC doesn't provide any means of representing that - your best option is to represent it as two different entries, one for each of the memory nodes. Interesting question of whether you would then claim they were half as big each, or the full size. Of course, there are other possible ways to get this info beyond HMAT, so perhaps the interface should allow it to be exposed if available?
HMAT doesn't do this, but I want this interface abstracted enough from HMAT to express whatever is necessary.
The CPU cache is the closest existing exported attributes to this, and they provide "
shared_cpu_list". To that end, I can export a "shared_node_list", though previous reviews strongly disliked multi-value sysfs entries. :(
Quoted 7 lines
Quoted 1 line
Would shared-node symlinks capture the need, and more acceptable?
My inclination is that it's better to follow an existing pattern than invent a new one that breaks people's expectations.
However, don't feel that strongly about it as long as the interface is functional and intuitive.
Okay, considering I'd have a difficult time testing such an interface since it doesn't apply to HMAT, and I've received only conflicting feedback on list attributes, I would prefer to leave this feature out of this series for now. I'm certainly not against adding it later.
PATCH v4 11/13 Documentation/ABI: Add node cache attributes
In reply to Keith BuschAdd the attributes for the system memory side caches.
--- Documentation/ABI/stable/sysfs-devices-node | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)
Documentation/ABI/stable/sysfs-devices-node +34 -0
@@ -142,3 +142,37 @@ Contact: Keith Busch <[email protected]> Description: This node's write latency in nanoseconds available to memory initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/associativity +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The caches associativity: 0 for direct mapped, non-zero if + indexed. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/level +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This cache's level in the memory hierarchy. Matches 'Y' in the + directory name. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/line_size +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The number of bytes accessed from the next cache level on a + cache miss. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/size +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The size of this memory side cache in bytes. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/write_policy +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The cache write policy: 0 for write-back, 1 for write-through, + 2 for other or unknown.
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 11/13] Documentation/ABI: Add node cache attributes
Quoted 2 lines · Keith Busch
Add the attributes for the system memory side caches.
I really would combine this with the previous one.
Quoted 38 lines
Signed-off-by Keith Busch <[email protected]>--- Documentation/ABI/stable/sysfs-devices-node | 34 +++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+)Documentation/ABI/stable/sysfs-devices-node +25
-0@@ -142,3 +142,37 @@ Contact: Keith Busch <[email protected]> Description: This node's write latency in nanoseconds available to memory initiators in nodes found in this class's initiators_nodelist. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/associativity +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The caches associativity: 0 for direct mapped, non-zero if + indexed. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/level +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + This cache's level in the memory hierarchy. Matches 'Y' in the + directory name. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/line_size +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The number of bytes accessed from the next cache level on a + cache miss. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/size +Date: December 2018 +Contact: Keith Busch <[email protected]>
Documentation/ABI/stable/sysfs-devices-node Contact: Keith Busch <[email protected]>
Quoted 10 lines
Documentation/ABI/stable/sysfs-devices-node +9
-1+Description: + The size of this memory side cache in bytes. + +What: /sys/devices/system/node/nodeX/side_cache/indexY/write_policy +Date: December 2018 +Contact: Keith Busch <[email protected]> +Description: + The cache write policy: 0 for write-back, 1 for write-through, + 2 for other or unknown. --
It would be good to document the meaning of indexY itself too.
PATCH v4 12/13 acpi/hmat: Register memory side cache attributes
In reply to Keith BuschRegister memory side cache attributes with the memory's node if HMAT provides the side cache iniformation table.
--- drivers/acpi/hmat/hmat.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
drivers/acpi/hmat/hmat.c +32 -0
@@ -206,6 +206,7 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, const unsigned long end) {struct acpi_hmat_cache *cache = (void *)header; +struct node_cache_attrs cache_attrs;u32 attrs;if (cache->header.length <sizeof (*cache)) {
@@ -219,6 +220,37 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, cache->memory_PD, cache->cache_size, attrs, cache->number_of_SMBIOShandles); + cache_attrs.size = cache->cache_size; + cache_attrs.level = (attrs &ACPI_HMAT_CACHE_LEVEL ) >>4 ; + cache_attrs.line_size = (attrs &ACPI_HMAT_CACHE_LINE_SIZE ) >>16 ; + +switch ((attrs &ACPI_HMAT_CACHE_ASSOCIATIVITY ) >>8 ) { +case ACPI_HMAT_CA_DIRECT_MAPPED : + cache_attrs.associativity =NODE_CACHE_DIRECT_MAP ; +break ; +case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING : + cache_attrs.associativity =NODE_CACHE_INDEXED ; +break ; +case ACPI_HMAT_CA_NONE : +default : + cache_attrs.associativity =NODE_CACHE_OTHER ; +break ; + } + +switch ((attrs &ACPI_HMAT_WRITE_POLICY ) >>12 ) { +case ACPI_HMAT_CP_WB : + cache_attrs.write_policy =NODE_CACHE_WRITE_BACK ; +break ; +case ACPI_HMAT_CP_WT : + cache_attrs.write_policy =NODE_CACHE_WRITE_THROUGH ; +break ; +case ACPI_HMAT_CP_NONE : +default : + cache_attrs.write_policy =NODE_CACHE_WRITE_OTHER ; +break ; + } + +node_add_cache (pxm_to_node (cache->memory_PD), &cache_attrs);return 0 ; }
Signature · 1 line
2.14.4
Rafael J. Wysocki
maintainerRe: [PATCHv4 12/13] acpi/hmat: Register memory side cache attributes
Quoted 28 lines · Keith Busch
Register memory side cache attributes with the memory's node if HMAT provides the side cache iniformation table.
Signed-off-by Keith Busch <[email protected]>--- drivers/acpi/hmat/hmat.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)drivers/acpi/hmat/hmat.c +4
-0@@ -206,6 +206,7 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, const unsigned long end) {struct acpi_hmat_cache *cache = (void *)header; +struct node_cache_attrs cache_attrs;u32 attrs;if (cache->header.length <sizeof (*cache)) {@@ -219,6 +220,37 @@ static __init int hmat_parse_cache(union acpi_subtable_headers *header, cache->memory_PD, cache->cache_size, attrs, cache->number_of_SMBIOShandles); + cache_attrs.size = cache->cache_size; + cache_attrs.level = (attrs &ACPI_HMAT_CACHE_LEVEL ) >>4 ; + cache_attrs.line_size = (attrs &ACPI_HMAT_CACHE_LINE_SIZE ) >>16 ;
drivers/acpi/hmat/hmat.c static __init int hmat_parse_cache(union acpi_subtable_headers *header, · line 235
Quoted 10 lines
drivers/acpi/hmat/hmat.c +10
-0+ +switch ((attrs &ACPI_HMAT_CACHE_ASSOCIATIVITY ) >>8 ) { +case ACPI_HMAT_CA_DIRECT_MAPPED : + cache_attrs.associativity =NODE_CACHE_DIRECT_MAP ; +break ; +case ACPI_HMAT_CA_COMPLEX_CACHE_INDEXING : + cache_attrs.associativity =NODE_CACHE_INDEXED ; +break ; +case ACPI_HMAT_CA_NONE : +default :
This looks slightly odd as "default" covers the other case as well. Maybe say what other case is covered by "default" in particular in a comment?
drivers/acpi/hmat/hmat.c static __init int hmat_parse_cache(union acpi_subtable_headers *header, · line 248
Quoted 13 lines
drivers/acpi/hmat/hmat.c +13
-0+ cache_attrs.associativity =NODE_CACHE_OTHER ; +break ; + } + +switch ((attrs &ACPI_HMAT_WRITE_POLICY ) >>12 ) { +case ACPI_HMAT_CP_WB : + cache_attrs.write_policy =NODE_CACHE_WRITE_BACK ; +break ; +case ACPI_HMAT_CP_WT : + cache_attrs.write_policy =NODE_CACHE_WRITE_THROUGH ; +break ; +case ACPI_HMAT_CP_NONE : +default :
And analogously here.
Quoted 9 lines
drivers/acpi/hmat/hmat.c +5
-1+ cache_attrs.write_policy =NODE_CACHE_WRITE_OTHER ; +break ; + } + +node_add_cache (pxm_to_node (cache->memory_PD), &cache_attrs);return 0 ; } --
PATCH v4 13/13 doc/mm: New documentation for memory performance
In reply to Keith BuschPlatforms may provide system memory where some physical address ranges perform differently than others, or is side cached by the system.
Add documentation describing a high level overview of such systems and the perforamnce and caching attributes the kernel provides for applications wishing to query this information.
--- Documentation/admin-guide/mm/numaperf.rst | 184 ++++++++++++++++++++++++++++++ 1 file changed, 184 insertions(+) create mode 100644 Documentation/admin-guide/mm/numaperf.rst
Documentation/admin-guide/mm/numaperf.rst new file +184 -0
@@ -0,0 +1,184 @@ +.. _numaperf: + +============= +NUMA Locality +============= + +Some platforms may have multiple types of memory attached to a single +CPU. These disparate memory ranges share some characteristics, such as +CPU cache coherence, but may have different performance. For example, +different media types and buses affect bandwidth and latency. + +A system supporting such heterogeneous memory by grouping each memory +type under different "nodes" based on similar CPU locality and performance +characteristics. Some memory may share the same node as a CPU, and others +are provided as memory only nodes. While memory only nodes do not provide +CPUs, they may still be directly accessible, or local, to one or more +compute nodes. The following diagram shows one such example of two compute +nodes with local memory and a memory only node for each of compute node: + + +------------------+ +------------------+ + | Compute Node 0 +-----+ Compute Node 1 | + | Local Node0 Mem | | Local Node1 Mem | + +--------+---------+ +--------+---------+ + | | + +--------+---------+ +--------+---------+ + | Slower Node2 Mem | | Slower Node3 Mem | + +------------------+ +--------+---------+ + +A "memory initiator" is a node containing one or more devices such as +CPUs or separate memory I/O devices that can initiate memory requests. +A "memory target" is a node containing one or more physical address +ranges accessible from one or more memory initiators. + +When multiple memory initiators exist, they may not all have the same +performance when accessing a given memory target. Each initiator-target +pair may be organized into different ranked access classes to represent +this relationship. The highest performing initiator to a given target +is considered to be one of that target's local initiators, and given +the highest access class, 0. Any given target may have one or more +local initiators, and any given initiator may have multiple local +memory targets. + +To aid applications matching memory targets with their initiators, the +kernel provides symlinks to each other. The following example lists the +relationship for the class "0" memory initiators and targets, which is +the of nodes with the highest performing access relationship:: + + # symlinks -v /sys/devices/system/node/nodeX/class0/ + relative: /sys/devices/system/node/nodeX/class0/targetY -> ../../nodeY + + # symlinks -v /sys/devices/system/node/nodeY/class0/ + relative: /sys/devices/system/node/nodeY/class0/initiatorX -> ../../nodeX + +The linked nodes will also have their node numbers set in the class's +target and initiator nodelist entries. Following the same example as +above may look like the following:: + + # cat /sys/devices/system/node/nodeX/class0/target_nodelist + Y + + # cat /sys/devices/system/node/nodeY/class0/initiator_nodelist + X + +An example showing how this may be used to run a particular task on CPUs +and memory using best class nodes for a particular PCI device can be done +using existing 'numactl' as follows:: + + # NODE=$(cat /sys/devices/pci:0000:00/.../numa_node) + # numactl --membind=$(cat /sys/devices/node/node${NODE}/class0/target_nodelist) \ + --cpunodebind=$(cat /sys/devices/node/node${NODE}/class0/initiator_nodelist) \ + -- <some-program-to-execute> + +================ +NUMA Performance +================ + +Applications may wish to consider which node they want their memory to +be allocated from based on the node's performance characteristics. If +the system provides these attributes, the kernel exports them under the +node sysfs hierarchy by appending the attributes directory under the +memory node's class 0 initiators as follows:: + + /sys/devices/system/node/nodeY/class0/ + +These attributes apply only to the memory initiator nodes that have the +same class access and are symlink under the class, and are set in the +initiators' nodelist. + +The performance characteristics the kernel provides for the local initiators +are exported are as follows:: + + # tree -P "read*|write*" /sys/devices/system/node/nodeY/class0/ + /sys/devices/system/node/nodeY/class0/ + |-- read_bandwidth + |-- read_latency + |-- write_bandwidth + `-- write_latency + +The bandwidth attributes are provided in MiB/second. + +The latency attributes are provided in nanoseconds. + +========== +NUMA Cache +========== + +System memory may be constructed in a hierarchy of elements with various +performance characteristics in order to provide large address space of +slower performing memory side-cached by a smaller higher performing +memory. The system physical addresses that initiators are aware of +are provided by the last memory level in the hierarchy. The system +meanwhile uses higher performing memory to transparently cache access +to progressively slower levels. + +The term "far memory" is used to denote the last level memory in the +hierarchy. Each increasing cache level provides higher performing +initiator access, and the term "near memory" represents the fastest +cache provided by the system. + +This numbering is different than CPU caches where the cache level (ex: +L1, L2, L3) uses a CPU centric view with each increased level is lower +performing. In contrast, the memory cache level is centric to the last +level memory, so the higher numbered cache level denotes memory nearer +to the CPU, and further from far memory. + +The memory side caches are not directly addressable by software. When +software accesses a system address, the system will return it from the +near memory cache if it is present. If it is not present, the system +accesses the next level of memory until there is either a hit in that +cache level, or it reaches far memory. + +An application does not need to know about caching attributes in order +to use the system. Software may optionally query the memory cache +attributes in order to maximize the performance out of such a setup. +If the system provides a way for the kernel to discover this information, +for example with ACPI HMAT (Heterogeneous Memory Attribute Table), +the kernel will append these attributes to the NUMA node memory target. + +When the kernel first registers a memory cache with a node, the kernel +will create the following directory:: + + /sys/devices/system/node/nodeX/side_cache/ + +If that directory is not present, the system either does not not provide +a memory side cache, or that information is not accessible to the kernel. + +The attributes for each level of cache is provided under its cache +level index:: + + /sys/devices/system/node/nodeX/side_cache/indexA/ + /sys/devices/system/node/nodeX/side_cache/indexB/ + /sys/devices/system/node/nodeX/side_cache/indexC/ + +Each cache level's directory provides its attributes. For example, the +following shows a single cache level and the attributes available for +software to query:: + + # tree sys/devices/system/node/node0/side_cache/ + /sys/devices/system/node/node0/side_cache/ + |-- index1 + | |-- associativity + | |-- level + | |-- line_size + | |-- size + | `-- write_policy + +The "associativity" will be 0 if it is a direct-mapped cache, and non-zero +for any other indexed based, multi-way associativity. + +The "level" is the distance from the far memory, and matches the number +appended to its "index" directory. + +The "line_size" is the number of bytes accessed on a cache miss. + +The "size" is the number of bytes provided by this cache level. + +The "write_policy" will be 0 for write-back, and non-zero for +write-through caching. + +======== +See Also +======== +.. [1] https://www.uefi.org/sites/default/files/resources/ACPI_6_2.pdf + Section 5.2.27
Signature · 1 line
2.14.4
Quoted 31 lines · Keith Busch
The series seems quite calm now. I've received some approvals of the on the proposal, and heard no objections on the new core interfaces.
Please let me know if there is anyone or group of people I should request and wait for a review. And if anyone reading this would like additional time as well before I post a potentially subsequent version, please let me know.
I also wanted to inquire on upstream strategy if/when all desired reviews are received. The series is spanning a few subsystems, so I'm not sure who's tree is the best candidate. I could see an argument for driver-core, acpi, or mm as possible paths. Please let me know if there's a more appropriate option or any other gating concerns.
== Changes from v3 ==
I've fixed the documentation issues that have been raised for v3
Moved the hmat files according to Rafael's recommendation
Added received Reviewed-by's
Otherwise this v4 is much the same as v3.
== Background ==
Platforms may provide multiple types of cpu attached system memory. The memory ranges for each type may have different characteristics that applications may wish to know about when considering what node they want their memory allocated from.
Quoted 5 lines
It had previously been difficult to describe these setups as memory rangers were generally lumped into the NUMA node of the CPUs. New platform attributes have been created and in use today that describe the more complex memory hierarchies that can be created.
Could you please expand on this text -- how are these attributes exposed/consumed by both the kernel and user space?
Quoted 3 lines
This series' objective is to provide the attributes from such systems that are useful for applications to know about, and readily usable with existing tools and libraries.
I presume these tools and libraries are numactl and mbind()?
Balbir Singh.
Quoted 7 lines · Balbir Singh
Quoted 5 lines · Keith Busch
It had previously been difficult to describe these setups as memory rangers were generally lumped into the NUMA node of the CPUs. New platform attributes have been created and in use today that describe the more complex memory hierarchies that can be created.
Quoted 8 lines
Could you please expand on this text -- how are these attributes exposed/consumed by both the kernel and user space?
Quoted 3 lines
This series' objective is to provide the attributes from such systems that are useful for applications to know about, and readily usable with existing tools and libraries.
I presume these tools and libraries are numactl and
mbind()?
Yes, and numactl is used the examples provided in both changelogs and documentation in this series. Do you want to see those in the cover letter as well?
Quoted 15 lines · Keith Busch
Quoted 14 lines · Balbir Singh
Quoted 5 lines · Keith Busch
It had previously been difficult to describe these setups as memory rangers were generally lumped into the NUMA node of the CPUs. New platform attributes have been created and in use today that describe the more complex memory hierarchies that can be created.
Could you please expand on this text -- how are these attributes exposed/consumed by both the kernel and user space?
Quoted 3 lines
This series' objective is to provide the attributes from such systems that are useful for applications to know about, and readily usable with existing tools and libraries.
Quoted 5 lines
Quoted 1 line
I presume these tools and libraries are numactl and
mbind()?Yes, and numactl is used the examples provided in both changelogs and documentation in this series. Do you want to see those in the cover letter as well?
Not really, I was just reading through the cover letter and was curious
Balbir Singh.
Quoted 31 lines · On Wed, 16 Jan 2019 10:57:51 -0700 Keith Busch <[email protected]> wrote:
The series seems quite calm now. I've received some approvals of the on the proposal, and heard no objections on the new core interfaces.
Please let me know if there is anyone or group of people I should request and wait for a review. And if anyone reading this would like additional time as well before I post a potentially subsequent version, please let me know.
I also wanted to inquire on upstream strategy if/when all desired reviews are received. The series is spanning a few subsystems, so I'm not sure who's tree is the best candidate. I could see an argument for driver-core, acpi, or mm as possible paths. Please let me know if there's a more appropriate option or any other gating concerns.
== Changes from v3 ==
I've fixed the documentation issues that have been raised for v3
Moved the hmat files according to Rafael's recommendation
Added received Reviewed-by's
Otherwise this v4 is much the same as v3.
== Background ==
Platforms may provide multiple types of cpu attached system memory. The memory ranges for each type may have different characteristics that applications may wish to know about when considering what node they want their memory allocated from.
Quoted 9 lines
It had previously been difficult to describe these setups as memory rangers were generally lumped into the NUMA node of the CPUs. New platform attributes have been created and in use today that describe the more complex memory hierarchies that can be created.
This series' objective is to provide the attributes from such systems that are useful for applications to know about, and readily usable with existing tools and libraries.
Hi Keith,
I've been having a play with various hand constructed HMAT tables to allow me to try breaking them in all sorts of ways.
Mostly working as expected.
Two places I am so far unsure on...
1. Concept of 'best' is not implemented in a consistent fashion.
I don't agree with the logic to match on 'best' because it can give some counter intuitive sets of target nodes.
For my simple test case we have both the latency and bandwidth specified (using access as I'm lazy and it saves typing).
Rather that matching when both are the best value, we match when _any_ of the measurements is the 'best' for the type of measurement.
A simple system with a high bandwidth interconnect between two SoCs might well have identical bandwidths to memory connected to each node, but much worse latency to the remote one. Another simple case would be DDR and SCM on roughly the same memory controller. Bandwidths likely to be equal, latencies very different.
Right now we get both nodes in the list of 'best' ones because the bandwidths are equal which is far from ideal. It also means we are presenting one value for both latency and bandwidth, misrepresenting the ones where it doesn't apply.
If we aren't going to specify that both must be "best", then I think we should separate the bandwidth and latency classes, requiring userspace to check both if they want the best combination of latency and bandwidth. I'm also happy enough (having not thought about it much) to have one class where the 'best' is the value sorted first on best latency and then on best bandwidth.
2. Handling of memory only nodes - that might have a device attached - _PXM
This is a common situation in CCIX for example where you have an accelerator with coherent memory homed at it. Looks like a pci device in a domain with
the memory. Right now you can't actually do this as _PXM is processed
for pci devices, but we'll get that fixed (broken threadripper firmwares meant it got reverted last cycle).
In my case I have 4 nodes with cpu and memory (0,1,2,3) and 2 memory only (4,5) Memory only are longer latency and lower bandwidth.
Now
ls /sys/bus/nodes/devices/node0/class0/
...
initiator0
target0
target4
target5
read_bandwidth = 15000read_latency = 10000
These two values (and their paired write values) are correct for initiator0 to target0 but completely wrong for initiator0 to target4 or target5.
This occurs because we loop over the targets looking for the best values and add set the relevant bit in t->p_nodes based on that. These memory only nodes have a best value that happens to be equal from all the initiators. The issue is it isn't the one reported in the node0/class0.
Also if we look in/sys/bus/nodes/devices/node4/class0 there are no targets listed (there are the expected 4 initiators 0-3).
I'm not sure what the intended behavior would be in this case.
I'll run some more tests tomorrow.
Jonathan
Quoted 46 lines
Keith Busch (13):
acpi: Create subtable parsing infrastructure
acpi: Add HMAT to generic parsing tables acpi/hmat: Parse and report heterogeneous memory
node: Link memory nodes to their compute nodesDocumentation/ABI: Add new node sysfs attributes acpi/hmat: Register processor domain to its memory
node: Add heterogenous memory access attributesDocumentation/ABI: Add node performance attributes acpi/hmat: Register performance attributes
node: Add memory caching attributesDocumentation/ABI: Add node cache attributes acpi/hmat: Register memory side cache attributes doc/mm: New documentation for memory performanceDocumentation/ABI/stable/sysfs-devices-node | 87 +++++- Documentation/admin-guide/mm/numaperf.rst | 184 +++++++++++++ arch/arm64/kernel/acpi_numa.c | 2 +- arch/arm64/kernel/smp.c | 4 +- arch/ia64/kernel/acpi.c | 12 +- arch/x86/kernel/acpi/boot.c | 36 +-- drivers/acpi/Kconfig | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/hmat/Kconfig | 9 + drivers/acpi/hmat/Makefile | 1 + drivers/acpi/hmat/hmat.c | 375 ++++++++++++++++++++++++++ drivers/acpi/numa.c | 16 +- drivers/acpi/scan.c | 4 +- drivers/acpi/tables.c | 76 +++++- drivers/base/Kconfig | 8 + drivers/base/node.c | 317 +++++++++++++++++++++- drivers/irqchip/irq-gic-v2m.c | 2 +- drivers/irqchip/irq-gic-v3-its-pci-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its-platform-msi.c | 2 +- drivers/irqchip/irq-gic-v3-its.c | 6 +- drivers/irqchip/irq-gic-v3.c | 10 +- drivers/irqchip/irq-gic.c | 4 +- drivers/mailbox/pcc.c | 2 +- include/linux/acpi.h | 6 +- include/linux/node.h | 70 ++++- 25 files changed, 1172 insertions(+), 65 deletions(-) create mode 100644 Documentation/admin-guide/mm/numaperf.rst create mode 100644 drivers/acpi/hmat/Kconfig create mode 100644 drivers/acpi/hmat/Makefile create mode 100644 drivers/acpi/hmat/hmat.c
Quoted 28 lines · Jonathan Cameron
I've been having a play with various hand constructed HMAT tables to allow me to try breaking them in all sorts of ways.
Mostly working as expected.
Two places I am so far unsure on...
1. Concept of 'best' is not implemented in a consistent fashion.
I don't agree with the logic to match on 'best' because it can give some counter intuitive sets of target nodes.
For my simple test case we have both the latency and bandwidth specified (using access as I'm lazy and it saves typing).
Rather that matching when both are the best value, we match when _any_ of the measurements is the 'best' for the type of measurement.
A simple system with a high bandwidth interconnect between two SoCs might well have identical bandwidths to memory connected to each node, but much worse latency to the remote one. Another simple case would be DDR and SCM on roughly the same memory controller. Bandwidths likely to be equal, latencies very different.
Right now we get both nodes in the list of 'best' ones because the bandwidths are equal which is far from ideal. It also means we are presenting one value for both latency and bandwidth, misrepresenting the ones where it doesn't apply.
Quoted 5 lines
If we aren't going to specify that both must be "best", then I think we should separate the bandwidth and latency classes, requiring userspace to check both if they want the best combination of latency and bandwidth. I'm also happy enough (having not thought about it much) to have one class where the 'best' is the value sorted first on best latency and then on best bandwidth.
Okay, I see what you mean. I must admit my test environment doesn't have nodes with the same bandwith but different latency, so we may get the wrong information with the HMAT parsing in this series. I'll look into fixing that and consider your sugggestions.
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2. Handling of memory only nodes - that might have a device attached -
_PXMThis is a common situation in CCIX for example where you have an accelerator with coherent memory homed at it. Looks like a pci device in a domain with
the memory. Right now you can't actually do this as_PXMis processed
for pci devices, but we'll get that fixed (broken threadripper firmwares meant it got reverted last cycle).In my case I have 4 nodes with cpu and memory (0,1,2,3) and 2 memory only (4,5) Memory only are longer latency and lower bandwidth.
Now
ls/sys/bus/nodes/devices/node0/class0/
...initiator0
target0
target4
target5
Quoted 5 lines
read_bandwidth= 15000read_latency= 10000These two values (and their paired write values) are correct for initiator0 to target0 but completely wrong for initiator0 to target4 or target5.
Hm, this wasn't intended to tell us performance for the initiator's targets. The performance data here is when you access node0's memory target from a node in its initiator_list, or one of the simlinked initiatorX's.
If you want to see the performance attributes for accessing initiator0->target4, you can check:
/sys/devices/system/node/node0/class0/target4/class0/read_bandwidth
Quoted 10 lines
This occurs because we loop over the targets looking for the best values and add set the relevant bit in
t->p_nodesbased on that. These memory only nodes have a best value that happens to be equal from all the initiators. The issue is it isn't the one reported in the node0/class0.Also if we look in
/sys/bus/nodes/devices/node4/class0there are no targets listed (there are the expected 4 initiators 0-3).I'm not sure what the intended behavior would be in this case.
You mentioned that node 4 is a memory-only node, so it can't have any targets, right?
Quoted 35 lines · On Thu, 17 Jan 2019 12:47:51 -0700 Keith Busch <[email protected]> wrote:
Quoted 28 lines · Jonathan Cameron
I've been having a play with various hand constructed HMAT tables to allow me to try breaking them in all sorts of ways.
Mostly working as expected.
Two places I am so far unsure on...
1. Concept of 'best' is not implemented in a consistent fashion.
I don't agree with the logic to match on 'best' because it can give some counter intuitive sets of target nodes.
For my simple test case we have both the latency and bandwidth specified (using access as I'm lazy and it saves typing).
Rather that matching when both are the best value, we match when _any_ of the measurements is the 'best' for the type of measurement.
A simple system with a high bandwidth interconnect between two SoCs might well have identical bandwidths to memory connected to each node, but much worse latency to the remote one. Another simple case would be DDR and SCM on roughly the same memory controller. Bandwidths likely to be equal, latencies very different.
Right now we get both nodes in the list of 'best' ones because the bandwidths are equal which is far from ideal. It also means we are presenting one value for both latency and bandwidth, misrepresenting the ones where it doesn't apply.
Quoted 5 lines
If we aren't going to specify that both must be "best", then I think we should separate the bandwidth and latency classes, requiring userspace to check both if they want the best combination of latency and bandwidth. I'm also happy enough (having not thought about it much) to have one class where the 'best' is the value sorted first on best latency and then on best bandwidth.
Quoted 4 lines
Okay, I see what you mean. I must admit my test environment doesn't have nodes with the same bandwith but different latency, so we may get the wrong information with the HMAT parsing in this series. I'll look into fixing that and consider your sugggestions.
Great.
Quoted 33 lines
Quoted 21 lines
2. Handling of memory only nodes - that might have a device attached -
_PXMThis is a common situation in CCIX for example where you have an accelerator with coherent memory homed at it. Looks like a pci device in a domain with
the memory. Right now you can't actually do this as_PXMis processed
for pci devices, but we'll get that fixed (broken threadripper firmwares meant it got reverted last cycle).In my case I have 4 nodes with cpu and memory (0,1,2,3) and 2 memory only (4,5) Memory only are longer latency and lower bandwidth.
Now
ls/sys/bus/nodes/devices/node0/class0/
...initiator0
target0
target4
target5Quoted 5 lines
read_bandwidth= 15000read_latency= 10000These two values (and their paired write values) are correct for initiator0 to target0 but completely wrong for initiator0 to target4 or target5.
Hm, this wasn't intended to tell us performance for the initiator's targets. The performance data here is when you access node0's memory target from a node in its
initiator_list, or one of the simlinked initiatorX's.
Quoted 4 lines
If you want to see the performance attributes for accessing
initiator0->target4, you can check:
/sys/devices/system/node/node0/class0/target4/class0/read_bandwidth
Ah. That makes sense, but does raise the question of whether this interface is rather unintuitive and that the example given in the docs for the PCI device doesn't always work. Perhaps it is that documentation that needs refining.
Having values that don't apply to particular combinations of entries in the initiator_list and target_list based on which directory we are in doesn't seem great to me.
So the presence of a target directory in a node indicates the memory in the target is 'best' accessed from this node, but is unrelated to the values provided in this node.
One thought is we are trying to combine two unrelated questions and that is what is leading to the confusion.
1) I have a process (or similar) in this node, which is the 'best' memory to use and what are it's characteristics.
2) I have data in this memory, which processor node should I schedule my processing on.
Ideally we want to avoid searching all the nodes.
To test this I disabled the memory on one of my nodes to make it even more pathological (this is valid on the real hardware as the cpus don't have to have memory attached to them). So same as before but now node 3 is initiator only.
Using bandwidth as a proxy for all the other measurements..
For question 1 (what memory)
Initiator in node 0
Need to check
node0/class0/target0/class0/read_bandwidth (can shortcut this one obviously) node0/class0/target4/class0/read_bandwidth node0/class0/target5/class0/read_bandwidth
and discover that it's smaller for node0/class0/target0
Initiator in node 3 (initiator only) node3/class0/initiator_nodelist is empty so no useful information available.
Initiator in node 4 (pci card for example) can assume node 4 as no other information and it has memory (which incidentally might have long latencies compared to memory over the interconnect.).
For question 2 (what processor)
We are on better grounds
node0/class0/initiator0 node1/class0/initiator1 node2/class0/initiator2
node3 doesn't make sense (no memory) node4/class0/initiator[0-3] node5/class0/initiator[0-3]
All the memory / bandwidth numbers are as expected.
So my conclusion is this works fine for suggesting processor to use for given memory (or accelerator or whatever, though only if they are closely coupled with the processors). Doesn't work for the what memory to use for a given processor / pci card etc. Sometimes there is no answer, sometimes you have to search to find it.
Does it make more sense to just have two classes
1) Which memory is nearest to me?
2) Which processor is nearest to me?
(3) which processor of type X is nearest to me is harder to answer but useful).
Note that case 2 is clearly covered well by the existing, but I can't actually see what benefit having the target links has for that use case.
To illustrate how I think that would work.
Class 0, existing but with target links dropped.
What processor for each memory
node0/class0/initiator_nodelist 0
node1/class0/initiator_nodelist 1
node2/class0/initiator_nodelist 2
node3/class0/initiator_nodelist ""
node4/class0/initiator_nodelist 0-3
node5/class0/initatior_nodelist 0-3
All the memory stats reflect from the value for the given initiator to access this memory.
Class 1 new one for the what memory is nearest to me - no initiator files as that's 'me'. node0/class1/target_nodelist 0
node1/class1/target_nodelist 1
node2/class1/target_nodelist 2
node3/class1/target_nodelist 0-2
node4/class1/target_nodelist "" as not specified as an initiator in hmat.
Ideally class1 wouldn't even be there.
node5/class1/target_nodelist "" same
For now we would have no information for accelerators in node4, 5 but for now ACPI doesn't provide us the info for them anyway really. I suppose you could have HMAT describing 'initiators' in those nodes without there being any processors in SRAT. Let's park that one to solve another day.
Your pci example then becomes
+ # NODE=$(cat /sys/devices/pci:0000:00/.../numa_node)
+ # numactl --membind=$(cat /sys/devices/node/node${NODE}/class1/target_nodelist) \
+ --cpunodebind=$(cat /sys/devices/node/node${NODE}/class0/initiator_nodelist) \
+ -- <some-program-to-execute>
What do you think?
Jonathan
Quoted 6 lines
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This occurs because we loop over the targets looking for the best values and add set the relevant bit in
t->p_nodesbased on that. These memory only nodes have a best value that happens to be equal from all the initiators. The issue is it isn't the one reported in the node0/class0.
Quoted 8 lines
Quoted 5 lines
Also if we look in
/sys/bus/nodes/devices/node4/class0there are no targets listed (there are the expected 4 initiators 0-3).I'm not sure what the intended behavior would be in this case.
You mentioned that node 4 is a memory-only node, so it can't have any targets, right?
Depends on what is there that ACPI 6.2 doesn't describe :) Can have PCI cards for example.
Jonathan