new engine discovery interface

RFC PATCH Superseded Andi Shyti via igt-dev 3 participants 22 messages Feb 12, 2019 – Feb 13, 2019

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Library code Arm/Amlogic Meson SoC support

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Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #0 lore raw

v8 cover new engine discovery interface

Hi,

In this patchset I propose an alternative way of engine discovery thanks to the new interfaces developed by Tvrtko and Chris[4].

It's re-architectured compared to the previous patchset because almost everything goes into the new gem_query library under lib/i915, given its dependency to the i915 gpu.

Thanks Tvrtko, Chris, Antonio and Petri for your comments in the previous RFCs.

Andi

V1 --> V2
=========
RFC v1: [1]
- added a demo test that simply queries the driver about the engines and executes a buffer (thanks Tvrtko)
- refactored the for_each_engine_ctx() macro so that what in the previous version was done by the "bind" function, now it's done in the first iteration. (Thanks Crhis)
- removed the "gem_has_ring_ctx()" because it was out of the scope.
- rename functions to more meaningful names

V2 --> V3
=========
RFC v2: [2]
- removed a standalone gem_query_engines_demo test and added the exec-ctx subtest inside gem_exec_basic (thanks Tvrtko).
- fixed most of Tvrtko's comments in [5], which consist in putting the mallocs igt_assert and ictls in igt_require and few refactoring (thanks Tvrtko).

V3 --> V4
=========
PATCH v3: [3]
- re-architectured the discovery mechanism based on Tvrtko's sugestion and reviews.. In this version the discovery is done during the device opening and stored in a NULL terminated array, which replaces the existing intel_execution_engines2 that is mainly used as a reference.

V4 --> V5
=========
RFC v4: [6]
- the engine list is now built in 'igt_require_gem()' instead of '__open_driver()' so that we keep this discovery method specific to the i915 driver (thanks Chris).
- All the query/setparam structures dynamic allocation based on the number of engines, now are politically allocated 64 times, to avoid extra ioctl calls that retrieve the engine number (thanks Chris)
- use igt_ioctl instead of ioctl (thanks Chris)
- allocate intel_execution_engines2 dynamically instead of statically (thanks Tvrtko)
- simplify the test in 'gem_exec_basic()' so that simply checks the presence of the engine instead of executing a buffer (thank Chris)
- a new patch has been added (patch 3) that extends the 'gem_has_ring()' boolean function. The new version sets the index as it's mapped in the kernel.The previous function is now a wrapper to the new function.

V5 --> V6
=========
RFC v5: [7]
- Chris implemented the getparam ioctl which allows to the test to figure otu whether the new interface has been implemented. This way the for_each_engine_ctx() is able to work with new and old kernel uapi (thanks Chris)

V6 --> V7
=========
RFC v6: [8]
- a new patch has been added (patch 3) which adds a new requirement check through the igt_require_gem_engine_list() function. (thanks Chris) This function will initialize the engine list instead of the instead of igt_require_gem() as it was in v6
- all the ioctls have been wrapped (thanks Chris and Antonio) and new library functions have been added and assert the ioctls
- gem_init_engine_list() function returns the errno from the GETPARAM ioctl in order to be used as a requirement. (thanks Chris)
- fixed few requires/asserts
- The engine list "intel_active_engines2" is allocated of the number of engines instead of a political 64 (thanks Antonio).
- some parameter renaming in gem_has_ring_by_idx(). (thanks Chris).
- the original "intel_execution_engines2" has not been renamed, because it is used to create subtests before even executing any test/ioctl. By renaming it, some subtest generations failed. (thanks Petri)

V7 --> v8
=========
RFC v7: [9]
- all functions have been moved from lib/igt_gt.{c,h} and lib/ioctl_wrappers.{c,h} to lib/i916/gem_query.{c,h}. (thanks Chris)
- 'for_each_engine_ctx' has been renamed to 'for_each_engine2' to be consistent with the '2' that indicates the new 'struct intel_execution_engine2' data structure.

Andi Shyti (5):
include/drm-uapi: import i915_drm.h header file lib/i915: add gem_query library
lib/igt_gt: use for_each_engine2 to loop through engines
lib: ioctl_wrappers: reach engines by index as well
tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

 include/drm-uapi/i915_drm.h | 292 +++++++++++++++++++++++++++---------
 lib/Makefile.sources        |   2 +
 lib/i915/gem_query.c        | 175 +++++++++++++++++++++
 lib/i915/gem_query.h        |  42 ++++++
 lib/igt_gt.c                |   2 +-
 lib/igt_gt.h                |  10 +-
 lib/ioctl_wrappers.c        |  10 +-
 lib/ioctl_wrappers.h        |   4 +-
 lib/meson.build             |   1 +
 tests/i915/gem_exec_basic.c |  15 ++
 10 files changed, 475 insertions(+), 78 deletions(-)
 create mode 100644 lib/i915/gem_query.c
 create mode 100644 lib/i915/gem_query.h

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2.20.1

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Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #1 lore raw

RFC PATCH v8 1/5 include/drm-uapi: import i915_drm.h header file

This header file is imported in order to include the two new ioctls DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM and DRM_IOCTL_I915_QUERY.

Signed-off-by Andi Shyti <[email protected]>

---
 include/drm-uapi/i915_drm.h | 292 +++++++++++++++++++++++++++---------
 1 file changed, 221 insertions(+), 71 deletions(-)

include/drm-uapi/i915_drm.h +221 ~~-71~~

index d2792ab3640b..a9f6ebfba4af 100644
@@ -62,6 +62,26 @@ extern "C" {
 #define I915_ERROR_UEVENT		"ERROR"
 #define I915_RESET_UEVENT		"RESET"
 
+/*
+ * i915_user_extension: Base class for defining a chain of extensions
+ *
+ * Many interfaces need to grow over time. In most cases we can simply
+ * extend the struct and have userspace pass in more data. Another option,
+ * as demonstrated by Vulkan's approach to providing extensions for forward
+ * and backward compatibility, is to use a list of optional structs to
+ * provide those extra details.
+ *
+ * The key advantage to using an extension chain is that it allows us to
+ * redefine the interface more easily than an ever growing struct of
+ * increasing complexity, and for large parts of that interface to be
+ * entirely optional. The downside is more pointer chasing; chasing across
+ * the boundary with pointers encapsulated inside u64.
+ */
+struct i915_user_extension {
+	__u64 next_extension;
+	__u64 name;
+};
+
 /*
  * MOCS indexes used for GPU surfaces, defining the cacheability of the
  * surface data and the coherency for this data wrt. CPU vs. GPU accesses.

@@ -102,6 +122,8 @@ enum drm_i915_gem_engine_class {
 	I915_ENGINE_CLASS_INVALID	= -1
 };
 
+#define I915_ENGINE_CLASS_INVALID_NONE -1
+
 /**
  * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  *

@@ -319,6 +341,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_PERF_ADD_CONFIG	0x37
 #define DRM_I915_PERF_REMOVE_CONFIG	0x38
 #define DRM_I915_QUERY			0x39
+#define DRM_I915_GEM_VM_CREATE		0x3a
+#define DRM_I915_GEM_VM_DESTROY		0x3b
 
 #define DRM_IOCTL_I915_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH		DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)

@@ -367,6 +391,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
 #define DRM_IOCTL_I915_GEM_WAIT		DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
 #define DRM_IOCTL_I915_REG_READ			DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
 #define DRM_IOCTL_I915_GET_RESET_STATS		DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)

@@ -377,6 +402,8 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_PERF_ADD_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
 #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG	DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
 #define DRM_IOCTL_I915_QUERY			DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
+#define DRM_IOCTL_I915_GEM_VM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
+#define DRM_IOCTL_I915_GEM_VM_DESTROY	DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.

@@ -476,6 +503,8 @@ typedef struct drm_i915_irq_wait {
 #define   I915_SCHEDULER_CAP_ENABLED	(1ul << 0)
 #define   I915_SCHEDULER_CAP_PRIORITY	(1ul << 1)
 #define   I915_SCHEDULER_CAP_PREEMPTION	(1ul << 2)
+#define   I915_SCHEDULER_CAP_PMU	(1ul << 3)
+#define   I915_SCHEDULER_CAP_SEMAPHORES	(1ul << 4)
 
 #define I915_PARAM_HUC_STATUS		 42

@@ -972,7 +1001,7 @@ struct drm_i915_gem_execbuffer2 {
 	 * struct drm_i915_gem_exec_fence *fences.
 	 */
 	__u64 cliprects_ptr;
-#define I915_EXEC_RING_MASK              (7<<0)
+#define I915_EXEC_RING_MASK              (0x3f)
 #define I915_EXEC_DEFAULT                (0<<0)
 #define I915_EXEC_RENDER                 (1<<0)
 #define I915_EXEC_BSD                    (2<<0)

@@ -1120,32 +1149,34 @@ struct drm_i915_gem_busy {
 	 * as busy may become idle before the ioctl is completed.
 	 *
 	 * Furthermore, if the object is busy, which engine is busy is only
-	 * provided as a guide. There are race conditions which prevent the
-	 * report of which engines are busy from being always accurate.
-	 * However, the converse is not true. If the object is idle, the
-	 * result of the ioctl, that all engines are idle, is accurate.
+	 * provided as a guide and only indirectly by reporting its class
+	 * (there may be more than one engine in each class). There are race
+	 * conditions which prevent the report of which engines are busy from
+	 * being always accurate.  However, the converse is not true. If the
+	 * object is idle, the result of the ioctl, that all engines are idle,
+	 * is accurate.
 	 *
 	 * The returned dword is split into two fields to indicate both
-	 * the engines on which the object is being read, and the
-	 * engine on which it is currently being written (if any).
+	 * the engine classess on which the object is being read, and the
+	 * engine class on which it is currently being written (if any).
 	 *
 	 * The low word (bits 0:15) indicate if the object is being written
 	 * to by any engine (there can only be one, as the GEM implicit
 	 * synchronisation rules force writes to be serialised). Only the
-	 * engine for the last write is reported.
+	 * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
+	 * 1 not 0 etc) for the last write is reported.
 	 *
-	 * The high word (bits 16:31) are a bitmask of which engines are
-	 * currently reading from the object. Multiple engines may be
+	 * The high word (bits 16:31) are a bitmask of which engines classes
+	 * are currently reading from the object. Multiple engines may be
 	 * reading from the object simultaneously.
 	 *
-	 * The value of each engine is the same as specified in the
-	 * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc.
-	 * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to
-	 * the I915_EXEC_RENDER engine for execution, and so it is never
+	 * The value of each engine class is the same as specified in the
+	 * I915_CONTEXT_SET_ENGINES parameter and via perf, i.e.
+	 * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
 	 * reported as active itself. Some hardware may have parallel
 	 * execution engines, e.g. multiple media engines, which are
-	 * mapped to the same identifier in the EXECBUFFER2 ioctl and
-	 * so are not separately reported for busyness.
+	 * mapped to the same class identifier and so are not separately
+	 * reported for busyness.
 	 *
 	 * Caveat emptor:
 	 * Only the boolean result of this query is reliable; that is whether

@@ -1412,65 +1443,15 @@ struct drm_i915_gem_wait {
 };
 
 struct drm_i915_gem_context_create {
-	/*  output: id of new context*/
-	__u32 ctx_id;
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 pad;
 };
 
-struct drm_i915_gem_context_destroy {
-	__u32 ctx_id;
-	__u32 pad;
-};
-
-struct drm_i915_reg_read {
-	/*
-	 * Register offset.
-	 * For 64bit wide registers where the upper 32bits don't immediately
-	 * follow the lower 32bits, the offset of the lower 32bits must
-	 * be specified
-	 */
-	__u64 offset;
-#define I915_REG_READ_8B_WA (1ul << 0)
-
-	__u64 val; /* Return value */
-};
-/* Known registers:
- *
- * Render engine timestamp - 0x2358 + 64bit - gen7+
- * - Note this register returns an invalid value if using the default
- *   single instruction 8byte read, in order to workaround that pass
- *   flag I915_REG_READ_8B_WA in offset field.
- *
- */
-
-struct drm_i915_reset_stats {
-	__u32 ctx_id;
+struct drm_i915_gem_context_create_ext {
+	__u32 ctx_id; /* output: id of new context*/
 	__u32 flags;
-
-	/* All resets since boot/module reload, for all contexts */
-	__u32 reset_count;
-
-	/* Number of batches lost when active in GPU, for this context */
-	__u32 batch_active;
-
-	/* Number of batches lost pending for execution, for this context */
-	__u32 batch_pending;
-
-	__u32 pad;
-};
-
-struct drm_i915_gem_userptr {
-	__u64 user_ptr;
-	__u64 user_size;
-	__u32 flags;
-#define I915_USERPTR_READ_ONLY 0x1
-#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
-	/**
-	 * Returned handle for the object.
-	 *
-	 * Object handles are nonzero.
-	 */
-	__u32 handle;
+#define I915_GEM_CONTEXT_SINGLE_TIMELINE	0x1
+	__u64 extensions;
 };
 
 struct drm_i915_gem_context_param {

@@ -1491,6 +1472,38 @@ struct drm_i915_gem_context_param {
 	 * drm_i915_gem_context_param_sseu.
 	 */
 #define I915_CONTEXT_PARAM_SSEU		0x7
+
+	/*
+	 * The id of the associated virtual memory address space (ppGTT) of
+	 * this context. Can be retreived and passed to another context
+	 * (on the same fd) for both to use the same ppGTT and so share
+	 * address layouts, and avoid reloading the page tables on context
+	 * switches between themselves.
+	 *
+	 * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
+	 */
+#define I915_CONTEXT_PARAM_VM		0x8
+
+/*
+ * I915_CONTEXT_PARAM_ENGINES:
+ *
+ * Bind this context to operate on this subset of available engines. Henceforth,
+ * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
+ * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
+ * and upwards. Slots 0...N are filled in using the specified (class, instance).
+ * Use
+ *	engine_class: I915_ENGINE_CLASS_INVALID,
+ *	engine_instance: I915_ENGINE_CLASS_INVALID_NONE
+ * to specify a gap in the array that can be filled in later, e.g. by a
+ * virtual engine used for load balancing.
+ *
+ * Setting the number of engines bound to the context to 0, by passing a zero
+ * sized argument, will revert back to default settings.
+ *
+ * See struct i915_context_param_engines.
+ */
+#define I915_CONTEXT_PARAM_ENGINES	0x9
+
 	__u64 value;
 };

@@ -1553,6 +1566,98 @@ struct drm_i915_gem_context_param_sseu {
 	__u32 rsvd;
 };
 
+struct i915_context_param_engines {
+	__u64 extensions; /* linked chain of extension blocks, 0 terminates */
+
+	struct {
+		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
+		__u16 engine_instance;
+	} class_instance[0];
+};
+
+struct drm_i915_gem_context_create_ext_setparam {
+#define I915_CONTEXT_CREATE_EXT_SETPARAM 0
+	struct i915_user_extension base;
+	struct drm_i915_gem_context_param setparam;
+};
+
+struct drm_i915_gem_context_destroy {
+	__u32 ctx_id;
+	__u32 pad;
+};
+
+/*
+ * DRM_I915_GEM_VM_CREATE -
+ *
+ * Create a new virtual memory address space (ppGTT) for use within a context
+ * on the same file. Extensions can be provided to configure exactly how the
+ * address space is setup upon creation.
+ *
+ * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
+ * returned.
+ *
+ * DRM_I915_GEM_VM_DESTROY -
+ *
+ * Destroys a previously created VM id.
+ */
+struct drm_i915_gem_vm_control {
+	__u64 extensions;
+	__u32 flags;
+	__u32 id;
+};
+
+struct drm_i915_reg_read {
+	/*
+	 * Register offset.
+	 * For 64bit wide registers where the upper 32bits don't immediately
+	 * follow the lower 32bits, the offset of the lower 32bits must
+	 * be specified
+	 */
+	__u64 offset;
+#define I915_REG_READ_8B_WA (1ul << 0)
+
+	__u64 val; /* Return value */
+};
+
+/* Known registers:
+ *
+ * Render engine timestamp - 0x2358 + 64bit - gen7+
+ * - Note this register returns an invalid value if using the default
+ *   single instruction 8byte read, in order to workaround that pass
+ *   flag I915_REG_READ_8B_WA in offset field.
+ *
+ */
+
+struct drm_i915_reset_stats {
+	__u32 ctx_id;
+	__u32 flags;
+
+	/* All resets since boot/module reload, for all contexts */
+	__u32 reset_count;
+
+	/* Number of batches lost when active in GPU, for this context */
+	__u32 batch_active;
+
+	/* Number of batches lost pending for execution, for this context */
+	__u32 batch_pending;
+
+	__u32 pad;
+};
+
+struct drm_i915_gem_userptr {
+	__u64 user_ptr;
+	__u64 user_size;
+	__u32 flags;
+#define I915_USERPTR_READ_ONLY 0x1
+#define I915_USERPTR_UNSYNCHRONIZED 0x80000000
+	/**
+	 * Returned handle for the object.
+	 *
+	 * Object handles are nonzero.
+	 */
+	__u32 handle;
+};
+
 enum drm_i915_oa_format {
 	I915_OA_FORMAT_A13 = 1,	    /* HSW only */
 	I915_OA_FORMAT_A29,	    /* HSW only */

@@ -1714,6 +1819,7 @@ struct drm_i915_perf_oa_config {
 struct drm_i915_query_item {
 	__u64 query_id;
 #define DRM_I915_QUERY_TOPOLOGY_INFO    1
+#define DRM_I915_QUERY_ENGINE_INFO	2
 
 	/*
 	 * When set to zero by userspace, this is filled with the size of the

@@ -1811,6 +1917,50 @@ struct drm_i915_query_topology_info {
 	__u8 data[];
 };
 
+/**
+ * struct drm_i915_engine_info
+ *
+ * Describes one engine and it's capabilities as known to the driver.
+ */
+struct drm_i915_engine_info {
+	/** Engine class as in enum drm_i915_gem_engine_class. */
+	__u16 class;
+
+	/** Engine instance number. */
+	__u16 instance;
+
+	/** Reserved field. */
+	__u32 rsvd0;
+
+	/** Engine flags. */
+	__u64 flags;
+
+	/** Capabilities of this engine. */
+	__u64 capabilities;
+#define I915_VIDEO_CLASS_CAPABILITY_HEVC		(1 << 0)
+#define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC	(1 << 1)
+
+	/** Reserved fields. */
+	__u64 rsvd1[4];
+};
+
+/**
+ * struct drm_i915_query_engine_info
+ *
+ * Engine info query enumerates all engines known to the driver by filling in
+ * an array of struct drm_i915_engine_info structures.
+ */
+struct drm_i915_query_engine_info {
+	/** Number of struct drm_i915_engine_info structs following. */
+	__u32 num_engines;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	/** Marker for drm_i915_engine_info structures. */
+	struct drm_i915_engine_info engines[];
+};
+
 #if defined(__cplusplus)
 }
 #endif

Signature · 6 lines

2.20.1

_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #2 lore raw

RFC PATCH v8 2/5 lib/i915: add gem_query library

In reply to Andi Shyti via igt-dev

The gem_query library is a set of functions that interface with the query and getparam/setparam ioctls.

The entry point of the library is the igt_require_gem_engine_list() which checks whether the ioctls are implemented in the running kernel. If not the function skips the test with -EINVAL.
On the other hand, if the interfaces are implemented, then, at the first call it initializes an array of active engines (either physical or virtual).

The global '*intel_active_engines2' points to the active engines array or to the existing 'intel_execution_engines2'. The latter is in preparation to the next patch.

The value of the 'intel_active_engines2' will be used in further calls to check whether the above mentioned ioctls are implemented without the need to call getparam().

Signed-off-by Andi Shyti <[email protected]>

---
 lib/Makefile.sources |   2 +
 lib/i915/gem_query.c | 175 +++++++++++++++++++++++++++++++++++++++++++
 lib/i915/gem_query.h |  42 +++++++++++
 lib/igt_gt.c         |   2 +-
 lib/igt_gt.h         |   2 +-
 lib/meson.build      |   1 +
 6 files changed, 222 insertions(+), 2 deletions(-)
 create mode 100644 lib/i915/gem_query.c
 create mode 100644 lib/i915/gem_query.h

lib/Makefile.sources +2 -0

index 808b9617eca2..9dd5e9242ae4 100644
@@ -11,6 +11,8 @@ lib_source_list =	 	\
 	i915/gem_submission.h	\
 	i915/gem_ring.h	\
 	i915/gem_ring.c	\
+	i915/gem_query.c	\
+	i915/gem_query.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\

lib/i915/gem_query.c new file +175 -0

175 lines not on this page · raw message

lib/i915/gem_query.h new file +42 -0

42 lines not on this page · raw message

lib/igt_gt.c +1 -1

index 646696727ee4..2bfd6417b5e5 100644
@@ -577,7 +577,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)
 	return true;
 }
 
-const struct intel_execution_engine2 intel_execution_engines2[] = {
+struct intel_execution_engine2 intel_execution_engines2[] = {
 	{ "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
 	{ "bcs0", I915_ENGINE_CLASS_COPY, 0 },
 	{ "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },

lib/igt_gt.h +1 -1

index 54e95da98084..f4bd6c22a81a 100644
@@ -91,7 +91,7 @@ bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
 bool gem_can_store_dword(int fd, unsigned int engine);
 
-extern const struct intel_execution_engine2 {
+extern struct intel_execution_engine2 {
 	const char *name;
 	int class;
 	int instance;

lib/meson.build +1 -0

index dd36f818033c..a703da2fb0d2 100644
@@ -4,6 +4,7 @@ lib_sources = [
 	'i915/gem_scheduler.c',
 	'i915/gem_submission.c',
 	'i915/gem_ring.c',
+	'i915/gem_query.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',

Signature · 6 lines

2.20.1

_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Chris Wilson

2019-02-13 00:13 UTC #3 lore raw

Re: [igt-dev] [RFC PATCH v8 2/5] lib/i915: add gem_query library

Quoting Andi Shyti (2019-02-12 23:54:33)

Quoted 78 lines

The gem_query library is a set of functions that interface with the query and getparam/setparam ioctls.

The global '*intel_active_engines2' points to the active engines array or to the existing 'intel_execution_engines2'. The latter is in preparation to the next patch.

The value of the 'intel_active_engines2' will be used in further calls to check whether the above mentioned ioctls are implemented without the need to call getparam().

Signed-off-by Andi Shyti <[email protected]>

---
 lib/Makefile.sources |   2 +
 lib/i915/gem_query.c | 175 +++++++++++++++++++++++++++++++++++++++++++
 lib/i915/gem_query.h |  42 +++++++++++
 lib/igt_gt.c         |   2 +-
 lib/igt_gt.h         |   2 +-
 lib/meson.build      |   1 +
 6 files changed, 222 insertions(+), 2 deletions(-)
 create mode 100644 lib/i915/gem_query.c
 create mode 100644 lib/i915/gem_query.h

lib/Makefile.sources +2 -0

index 808b9617eca2..9dd5e9242ae4 100644
@@ -11,6 +11,8 @@ lib_source_list =             \
        i915/gem_submission.h   \
        i915/gem_ring.h \
        i915/gem_ring.c \
+       i915/gem_query.c        \
+       i915/gem_query.h        \
        i915_3d.h               \
        i915_reg.h              \
        i915_pciids.h           \

lib/i915/gem_query.c new file +28 -0

new file mode 100644
index 000000000000..2b7bb713c70a
@@ -0,0 +1,175 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "ioctl_wrappers.h"
+#include "drmtest.h"
+
+#include "i915/gem_query.h"
+

lib/i915/gem_query.c line 38

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+struct intel_execution_engine2 *intel_active_engines2;
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+       return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q) ? -errno : 0;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+       igt_assert(!__gem_query(fd, q));

For extra tidy asserts:

static int __gem_query(int fd, struct drm_i915_query *q)

{
	int err;

	err = 0;
	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
		err = -errno;

	errno = 0;
	return er;
}

void gem_query(int fd, struct drm_i915_query *q)

{
       igt_assert_eq(__gem_query(fd, q), 0);
}

lib/i915/gem_query.c line 48

Quoted 9 lines

lib/i915/gem_query.c new file +9 -0

+
+static int __gem_get_set_param(int fd, unsigned long request,
+                              struct drm_i915_gem_context_param *p)
+{
+       return igt_ioctl(fd, request, p) ?  -errno : 0;
+}
+
+void gem_get_set_param(int fd, unsigned long request,
+                      struct drm_i915_gem_context_param *p)

gem_context_set_param! It exists!

lib/i915/gem_query.c line 53

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+{
+       igt_assert(!__gem_get_set_param(fd, request, p));
+}
+
+bool gem_has_get_set_param(void)

Has what?

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+{
+       return intel_active_engines2 != intel_execution_engines2;
+}
+
+static struct drm_i915_query_engine_info *query_engines(int fd)

lib/i915/gem_query.c line 68

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+{
+       struct drm_i915_query query = { };
+       struct drm_i915_query_item item = { };
+       struct drm_i915_query_engine_info *query_engines;
+
+       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+       query.items_ptr = to_user_pointer(&item);
+       query.num_items = 1;
+       item.length = sizeof(*query_engines) +
+                     64 * sizeof(struct drm_i915_engine_info);

You are betting we are not going to exceed 64 engines? A common bet for sure...

lib/i915/gem_query.c line 73

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+
+       igt_assert((query_engines = calloc(1, item.length)));
+       item.data_ptr = to_user_pointer(query_engines);
+
+       gem_query(fd, &query);

If we did have move than 64 engines, this fails with -EINVAL. I just feel it's a failure mode we can handle. I tend to only make the assumption for stack allocations, but for heap use an accurate double pass.

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+       return query_engines;
+}
+
+void __set_ctx_engine_map(int fd, uint32_t ctx_id)
+{
+       int i;
+       const struct intel_execution_engine2 *e2;
+       struct drm_i915_gem_context_param ctx_param;
+       struct i915_context_param_engines *ctx_engine;
+

lib/i915/gem_query.c line 94

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+       if (!gem_has_get_set_param())
+               return;
+
+       ctx_param.ctx_id = ctx_id;
+       ctx_param.param = I915_CONTEXT_PARAM_ENGINES;
+       ctx_param.size = sizeof(*ctx_engine) +
+                        (I915_EXEC_RING_MASK - 1) *
+                        sizeof(*ctx_engine->class_instance);
+
+       igt_assert((ctx_engine = calloc(1, ctx_param.size)));

Here you know the size better than this estimate and can put it on the stack.

Quoted 18 lines

lib/i915/gem_query.c new file +18 -0

+
+       ctx_engine->extensions = 0;
+       for (i = 0, e2 = intel_active_engines2; e2->name; i++, e2++) {
+               ctx_engine->class_instance[i].engine_class = e2->class;
+               ctx_engine->class_instance[i].engine_instance = e2->instance;
+       }
+
+       ctx_param.value = to_user_pointer(ctx_engine);
+
+       gem_setparam(fd, &ctx_param);
+
+       free(ctx_engine);
+}
+
+/*
+ * Initializes the list of engines.
+ *
+ * Returns:

lib/i915/gem_query.c line 122

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+ *
+ *  - 0 in case of success and the get/setparam ioctls are implemented
+ *  - -EINVAL in case of success but get/setparam ioctls are not implemented
+ *  - errno in case of failure
+ */
+static int gem_init_engine_list(int fd)
+{
+       int i, ret;
+       struct drm_i915_query_engine_info *query_engine = query_engines(fd);
+       const char *engine_names[] = { "rcs", "bcs", "vcs", "vecs" };

class, not engine, names. And deserves its own mapping table with api.

lib/i915/gem_query.c line 129

Quoted 7 lines

lib/i915/gem_query.c new file +7 -0

+       struct drm_i915_gem_context_param ctx_param = {
+               .param = I915_CONTEXT_PARAM_ENGINES,
+       };
+
+       /* the list is already initialized */
+       if (intel_active_engines2)
+               return gem_has_get_set_param() ? 0 : -EINVAL;

We would use -ENODEV? Leaks query_engine, probably should reorder.

lib/i915/gem_query.c line 142

Quoted 12 lines

lib/i915/gem_query.c new file +12 -0

+       /*
+        * we check first whether the new engine discovery uapi
+        * is in the current kernel, if not, the
+        * DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM will fail with
+        * errno = EINVAL. In this case, we fall back to using
+        * the previous engine discovery way
+        */
+       ret = __gem_get_set_param(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
+                                 &ctx_param);
+       if (ret) {
+               if (ret == -EINVAL)
+                       intel_active_engines2 = intel_execution_engines2;

Leaks

lib/i915/gem_query.c line 148

Quoted 6 lines

lib/i915/gem_query.c new file +6 -0

+               return ret;
+       }
+
+       igt_assert((intel_active_engines2 =
+                   calloc(query_engine->num_engines + 1,
+                          sizeof(*intel_active_engines2))));

Don't be afraid of using two lines for different effects.

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+       for (i = 0; i < query_engine->num_engines; i++) {
+               char *name;
+               int class = query_engine->engines[i].class;
+               int instance = query_engine->engines[i].instance;
+

lib/i915/gem_query.c line 164

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+               igt_assert(class < ARRAY_SIZE(engine_names) && class >= 0);
+               igt_assert(engine_names[class]);
+
+               intel_active_engines2[i].class = class;
+               intel_active_engines2[i].instance = instance;
+
+               igt_assert(asprintf(&name, "%s%d",
+                                   engine_names[class], instance) > 0);
+               intel_active_engines2[i].name = name;
+       }

+1 because you want to terminate with a sentinel?

Use malloc and make it explicit.

lib/i915/gem_query.c line 173

Quoted 9 lines

lib/i915/gem_query.c new file +9 -0

+
+       free(query_engine);
+
+       return 0;
+}
+
+void igt_require_gem_engine_list(int fd)
+{
+       igt_require_intel(fd);

Redundant.

Quoted 91 lines

lib/i915/gem_query.c new file +2 -0

+       igt_require(!gem_init_engine_list(fd));
+}

lib/i915/gem_query.h new file +42 -0

new file mode 100644
index 000000000000..d927269c8aa9
@@ -0,0 +1,42 @@
+/*
+ * Copyright © 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_QUERY_H
+#define GEM_QUERY_H
+
+#include "igt_gt.h"
+
+void __set_ctx_engine_map(int fd, uint32_t ctx_id);
+
+bool gem_has_get_set_param(void);
+void gem_query(int fd, struct drm_i915_query *q);
+
+void gem_get_set_param(int fd, unsigned long request, struct drm_i915_gem_context_param *p);
+#define gem_setparam(f, p) gem_get_set_param(f, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, p)
+#define gem_getparam(f, p) gem_get_set_param(f, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, p)
+
+void igt_require_gem_engine_list(int fd);
+
+extern struct intel_execution_engine2 *intel_active_engines2;
+
+#endif /* GEM_QUEY_H */

lib/igt_gt.c +1 -1

index 646696727ee4..2bfd6417b5e5 100644
@@ -577,7 +577,7 @@ bool gem_can_store_dword(int fd, unsigned int engine)
        return true;
 }
 
-const struct intel_execution_engine2 intel_execution_engines2[] = {
+struct intel_execution_engine2 intel_execution_engines2[] = {
        { "rcs0", I915_ENGINE_CLASS_RENDER, 0 },
        { "bcs0", I915_ENGINE_CLASS_COPY, 0 },
        { "vcs0", I915_ENGINE_CLASS_VIDEO, 0 },

lib/igt_gt.h +1 -1

index 54e95da98084..f4bd6c22a81a 100644
@@ -91,7 +91,7 @@ bool gem_ring_has_physical_engine(int fd, unsigned int ring);
 
 bool gem_can_store_dword(int fd, unsigned int engine);
 
-extern const struct intel_execution_engine2 {
+extern struct intel_execution_engine2 {
        const char *name;
        int class;
        int instance;

lib/meson.build +1 -0

index dd36f818033c..a703da2fb0d2 100644
@@ -4,6 +4,7 @@ lib_sources = [
        'i915/gem_scheduler.c',
        'i915/gem_submission.c',
        'i915/gem_ring.c',
+       'i915/gem_query.c',
        'igt_color_encoding.c',
        'igt_debugfs.c',
        'igt_device.c',

Signature · 1 line

2.20.1

_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Andi Shyti via igt-dev

author

2019-02-13 00:55 UTC #4 lore raw

Re: [igt-dev] [RFC PATCH v8 2/5] lib/i915: add gem_query library

Hi Chris,

Quoted 12 lines

lib/i915/gem_query.c line 38
Quoted 8 lines
lib/i915/gem_query.c new file +8 -0
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+       return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q) ? -errno : 0;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+       igt_assert(!__gem_query(fd, q));
For extra tidy asserts:
static int __gem_query(int fd, struct drm_i915_query *q)

Quoted 10 lines

{
	int err;

	err = 0;
	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
		err = -errno;

	errno = 0;
	return er;
}

Yes, I've seen this around, although it looks a bit redundant to me, I'll keep the style.

Quoted 10 lines

lib/i915/gem_query.c line 48

Quoted 8 lines

lib/i915/gem_query.c new file +8 -0

+static int __gem_get_set_param(int fd, unsigned long request,
+                              struct drm_i915_gem_context_param *p)
+{
+       return igt_ioctl(fd, request, p) ?  -errno : 0;
+}
+
+void gem_get_set_param(int fd, unsigned long request,
+                      struct drm_i915_gem_context_param *p)

gem_context_set_param! It exists!

Oh! I didn't know! That's a great discovery :)

Quoted 7 lines

lib/i915/gem_query.c line 53
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+{
+       igt_assert(!__gem_get_set_param(fd, request, p));
+}
+
+bool gem_has_get_set_param(void)
Has what?

has get/setparam. I couldn't come out with a better name. I'll think harder.

Quoted 8 lines

lib/i915/gem_query.c line 68
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+       query.items_ptr = to_user_pointer(&item);
+       query.num_items = 1;
+       item.length = sizeof(*query_engines) +
+                     64 * sizeof(struct drm_i915_engine_info);
You are betting we are not going to exceed 64 engines? A common bet for sure...

We've been discussing about this in v4 and we agreed that 64 is big enough[*]. Am I missing anything?
Besides, I thought that we won't have more engines than I915_EXEC_RING_MASK.

[*] https://lists.freedesktop.org/archives/igt-dev/2019-January/008034.html

Quoted 7 lines

lib/i915/gem_query.c line 122
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+static int gem_init_engine_list(int fd)
+{
+       int i, ret;
+       struct drm_i915_query_engine_info *query_engine = query_engines(fd);
+       const char *engine_names[] = { "rcs", "bcs", "vcs", "vecs" };
class, not engine, names. And deserves its own mapping table with api.

I can make a new API in a next patch and remove it from here, as it is a bit out of the scope if the series.

Quoted 9 lines

lib/i915/gem_query.c line 129

Quoted 7 lines

lib/i915/gem_query.c new file +7 -0

+       struct drm_i915_gem_context_param ctx_param = {
+               .param = I915_CONTEXT_PARAM_ENGINES,
+       };
+
+       /* the list is already initialized */
+       if (intel_active_engines2)
+               return gem_has_get_set_param() ? 0 : -EINVAL;

We would use -ENODEV? Leaks query_engine, probably should reorder.

I wanted here to be consistent with the failure value... (continues)

Quoted 4 lines

lib/i915/gem_query.c new file +4 -0

+       /*
+        * we check first whether the new engine discovery uapi
+        * is in the current kernel, if not, the
+        * DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM will fail with

Quoted 8 lines

lib/i915/gem_query.c line 142

Quoted 8 lines

lib/i915/gem_query.c new file +8 -0

+        * errno = EINVAL. In this case, we fall back to using
+        * the previous engine discovery way
+        */
+       ret = __gem_get_set_param(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
+                                 &ctx_param);
+       if (ret) {
+               if (ret == -EINVAL)
+                       intel_active_engines2 = intel_execution_engines2;

... here we return -EINVAL to indicate that the get/setparam we need is not implemented. If I return -ENODEV before, I should return -ENODEV here as well (but that's not what the ioctl returns).

Quoted 1 line

Leaks

Right!

Quoted 5 lines

lib/i915/gem_query.c line 148
Quoted 3 lines
lib/i915/gem_query.c new file +3 -0
+       igt_assert((intel_active_engines2 =
+                   calloc(query_engine->num_engines + 1,
+                          sizeof(*intel_active_engines2))));
Don't be afraid of using two lines for different effects.

You mean 2 instead of 3? I just wanted to keep it under 80.

Quoted 18 lines

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+       for (i = 0; i < query_engine->num_engines; i++) {
+               char *name;
+               int class = query_engine->engines[i].class;
+               int instance = query_engine->engines[i].instance;
+

lib/i915/gem_query.c line 164

Quoted 10 lines

lib/i915/gem_query.c new file +10 -0

+               igt_assert(class < ARRAY_SIZE(engine_names) && class >= 0);
+               igt_assert(engine_names[class]);
+
+               intel_active_engines2[i].class = class;
+               intel_active_engines2[i].instance = instance;
+
+               igt_assert(asprintf(&name, "%s%d",
+                                   engine_names[class], instance) > 0);
+               intel_active_engines2[i].name = name;
+       }

+1 because you want to terminate with a sentinel?

Quoted 1 line

Use malloc and make it explicit.

OK.

Quoted 5 lines

lib/i915/gem_query.c line 173
Quoted 3 lines
lib/i915/gem_query.c new file +3 -0
+void igt_require_gem_engine_list(int fd)
+{
+       igt_require_intel(fd);
Redundant.

OK.

Thanks again, Chris!

Andi
_______________________________________________
igt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/igt-dev

Chris Wilson

2019-02-13 09:20 UTC #5 lore raw

Re: [igt-dev] [RFC PATCH v8 2/5] lib/i915: add gem_query library

Quoting Andi Shyti (2019-02-13 00:55:03)

Quoted 21 lines

Hi Chris,

Quoted 19 lines

lib/i915/gem_query.c line 38

Quoted 8 lines

lib/i915/gem_query.c new file +8 -0

+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+       return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q) ? -errno : 0;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+       igt_assert(!__gem_query(fd, q));

For extra tidy asserts:

static int __gem_query(int fd, struct drm_i915_query *q)

{
      int err;

      err = 0;
      if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
              err = -errno;

Quoted 6 lines

Quoted 3 lines
      errno = 0;
      return er;
}
Yes, I've seen this around, although it looks a bit redundant to me, I'll keep the style.

Wait until you read the igt_assert output.

Quoted 30 lines

Quoted 10 lines

lib/i915/gem_query.c line 48

Quoted 8 lines

lib/i915/gem_query.c new file +8 -0

+static int __gem_get_set_param(int fd, unsigned long request,
+                              struct drm_i915_gem_context_param *p)
+{
+       return igt_ioctl(fd, request, p) ?  -errno : 0;
+}
+
+void gem_get_set_param(int fd, unsigned long request,
+                      struct drm_i915_gem_context_param *p)

gem_context_set_param! It exists!

Oh! I didn't know! That's a great discovery :)

Quoted 7 lines

lib/i915/gem_query.c line 53
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+{
+       igt_assert(!__gem_get_set_param(fd, request, p));
+}
+
+bool gem_has_get_set_param(void)
Has what?

has get/setparam. I couldn't come out with a better name. I'll think harder.

Quoted 6 lines

Quoted 5 lines

lib/i915/gem_query.c new file +5 -0

+       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+       query.items_ptr = to_user_pointer(&item);
+       query.num_items = 1;
+       item.length = sizeof(*query_engines) +
+                     64 * sizeof(struct drm_i915_engine_info);

Quoted 7 lines

Quoted 2 lines
You are betting we are not going to exceed 64 engines? A common bet for sure...
We've been discussing about this in v4 and we agreed that 64 is big enough[*]. Am I missing anything?
Besides, I thought that we won't have more engines than I915_EXEC_RING_MASK.

Do you think that execbuf2 is our final form? Besides the argument about heap vs stack is more appropriate here; using the stack is more appropriate later.

Quoted 39 lines

[*] https://lists.freedesktop.org/archives/igt-dev/2019-January/008034.html
Quoted 7 lines
lib/i915/gem_query.c line 122
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+static int gem_init_engine_list(int fd)
+{
+       int i, ret;
+       struct drm_i915_query_engine_info *query_engine = query_engines(fd);
+       const char *engine_names[] = { "rcs", "bcs", "vcs", "vecs" };
class, not engine, names. And deserves its own mapping table with api.
I can make a new API in a next patch and remove it from here, as it is a bit out of the scope if the series.
Quoted 9 lines
lib/i915/gem_query.c line 129
Quoted 7 lines
lib/i915/gem_query.c new file +7 -0
+       struct drm_i915_gem_context_param ctx_param = {
+               .param = I915_CONTEXT_PARAM_ENGINES,
+       };
+
+       /* the list is already initialized */
+       if (intel_active_engines2)
+               return gem_has_get_set_param() ? 0 : -EINVAL;
We would use -ENODEV? Leaks query_engine, probably should reorder.
I wanted here to be consistent with the failure value... (continues)
Quoted 4 lines
Quoted 4 lines
lib/i915/gem_query.c new file +4 -0
+       /*
+        * we check first whether the new engine discovery uapi
+        * is in the current kernel, if not, the
+        * DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM will fail with
Quoted 8 lines
lib/i915/gem_query.c line 142
Quoted 8 lines
lib/i915/gem_query.c new file +8 -0
+        * errno = EINVAL. In this case, we fall back to using
+        * the previous engine discovery way
+        */
+       ret = __gem_get_set_param(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
+                                 &ctx_param);
+       if (ret) {
+               if (ret == -EINVAL)
+                       intel_active_engines2 = intel_execution_engines2;

Quoted 4 lines

... here we return -EINVAL to indicate that the get/setparam we need is not implemented. If I return -ENODEV before, I should return -ENODEV here as well (but that's not what the ioctl returns).

-ENODEV is generally for unsupported the platforms, which the former tests. An unrecognised param is -EINVAL. ~o~

Quoted 5 lines

Quoted 2 lines
Leaks
Right!

Quoted 7 lines

Quoted 5 lines
lib/i915/gem_query.c line 148
Quoted 3 lines
lib/i915/gem_query.c new file +3 -0
+       igt_assert((intel_active_engines2 =
+                   calloc(query_engine->num_engines + 1,
+                          sizeof(*intel_active_engines2))));
Don't be afraid of using two lines for different effects.
You mean 2 instead of 3? I just wanted to keep it under 80.

engines = calloc(...).
igt_assert(engines);

I sometimes wish we distinguished between igt_assert() and just plain old assert, so that we know that igt_assert() actually is significant for testing.
-Chris
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Andi Shyti via igt-dev

author

2019-02-13 09:55 UTC #6 lore raw

Re: [igt-dev] [RFC PATCH v8 2/5] lib/i915: add gem_query library

Hi Chris,

Quoted 19 lines

Quoted 19 lines
Quoted 19 lines
lib/i915/gem_query.c line 38
Quoted 8 lines
lib/i915/gem_query.c new file +8 -0
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+       return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q) ? -errno : 0;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+       igt_assert(!__gem_query(fd, q));
For extra tidy asserts:
static int __gem_query(int fd, struct drm_i915_query *q)
{
      int err;

      err = 0;
      if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
              err = -errno;

Quoted 8 lines

Quoted 6 lines
Quoted 3 lines
      errno = 0;
      return er;
}
Yes, I've seen this around, although it looks a bit redundant to me, I'll keep the style.
Wait until you read the igt_assert output.

OK, didn't think about it, I'm definitely missing some history here.

Quoted 9 lines

Quoted 9 lines
Quoted 8 lines
lib/i915/gem_query.c line 68
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+       query.items_ptr = to_user_pointer(&item);
+       query.num_items = 1;
+       item.length = sizeof(*query_engines) +
+                     64 * sizeof(struct drm_i915_engine_info);
You are betting we are not going to exceed 64 engines? A common bet for sure...

Quoted 8 lines

Quoted 4 lines
We've been discussing about this in v4 and we agreed that 64 is big enough[*]. Am I missing anything?
Besides, I thought that we won't have more engines than I915_EXEC_RING_MASK.
Do you think that execbuf2 is our final form? Besides the argument about heap vs stack is more appropriate here; using the stack is more appropriate later.

I can do that in case of 'drm_i915_query_engine_info' because the flexible structure has a name (struct drm_i915_engine_info engines[];).

But here the choices are less pleasant. Because I either do in the kernel something like:

+ struct whatever_name {
- struct {
__u16 engine_class; /* see enum drm_i915_gem_engine_class */ __u16 engine_instance;
} class_instance[0];

Or I define some ugly unflexible array in __set_ctx_engine_map():

	struct {
		__u16 ngine_class;
		__u16 engine_instance;
	} class_instance[I915_EXEC_RING_MASK];

which looks to me quite strict (if we are considering that we might subvert everyting).

Or, even worse, some "__u32 engine_stuff[I915_EXEC_RING_MASK]" and cast it.

Allocating it everywhere it looked cleaner.

Whatever you like :)

Quoted 25 lines

Quoted 9 lines

lib/i915/gem_query.c line 129

Quoted 7 lines

lib/i915/gem_query.c new file +7 -0

+       struct drm_i915_gem_context_param ctx_param = {
+               .param = I915_CONTEXT_PARAM_ENGINES,
+       };
+
+       /* the list is already initialized */
+       if (intel_active_engines2)
+               return gem_has_get_set_param() ? 0 : -EINVAL;

We would use -ENODEV? Leaks query_engine, probably should reorder.

I wanted here to be consistent with the failure value... (continues)

Quoted 12 lines

lib/i915/gem_query.c new file +12 -0

+       /*
+        * we check first whether the new engine discovery uapi
+        * is in the current kernel, if not, the
+        * DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM will fail with
+        * errno = EINVAL. In this case, we fall back to using
+        * the previous engine discovery way
+        */
+       ret = __gem_get_set_param(fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM,
+                                 &ctx_param);
+       if (ret) {
+               if (ret == -EINVAL)
+                       intel_active_engines2 = intel_execution_engines2;

Quoted 7 lines

Quoted 4 lines
... here we return -EINVAL to indicate that the get/setparam we need is not implemented. If I return -ENODEV before, I should return -ENODEV here as well (but that's not what the ioctl returns).
-ENODEV is generally for unsupported the platforms, which the former tests. An unrecognised param is -EINVAL. ~o~

Yes, makes sense, while I was writing this I also thought that -EINVAL is not correct, but I kept it for consistency with the ioctl. I will return in both cases -ENODEV, then.

Quoted 6 lines

Quoted 6 lines
Quoted 5 lines
lib/i915/gem_query.c line 148
Quoted 3 lines
lib/i915/gem_query.c new file +3 -0
+       igt_assert((intel_active_engines2 =
+                   calloc(query_engine->num_engines + 1,
+                          sizeof(*intel_active_engines2))));
Don't be afraid of using two lines for different effects.

Quoted 8 lines

Quoted 1 line
You mean 2 instead of 3? I just wanted to keep it under 80.
engines = calloc(...).
igt_assert(engines);
I sometimes wish we distinguished between igt_assert() and just plain old assert, so that we know that igt_assert() actually is significant for testing.

It's a cultural thing :)

Andi
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Chris Wilson

2019-02-13 10:00 UTC #7 lore raw

Re: [igt-dev] [RFC PATCH v8 2/5] lib/i915: add gem_query library

Quoting Andi Shyti (2019-02-13 09:55:26)

Quoted 65 lines

Hi Chris,
Quoted 19 lines
Quoted 19 lines
Quoted 19 lines
lib/i915/gem_query.c line 38
Quoted 8 lines
lib/i915/gem_query.c new file +8 -0
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+       return igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q) ? -errno : 0;
+}
+
+void gem_query(int fd, struct drm_i915_query *q)
+{
+       igt_assert(!__gem_query(fd, q));
For extra tidy asserts:
static int __gem_query(int fd, struct drm_i915_query *q)
{
      int err;

      err = 0;
      if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
              err = -errno;
Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
      errno = 0;
      return er;
}
Yes, I've seen this around, although it looks a bit redundant to me, I'll keep the style.
Wait until you read the igt_assert output.
OK, didn't think about it, I'm definitely missing some history here.
Quoted 9 lines
Quoted 9 lines
Quoted 8 lines
lib/i915/gem_query.c line 68
Quoted 5 lines
lib/i915/gem_query.c new file +5 -0
+       item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+       query.items_ptr = to_user_pointer(&item);
+       query.num_items = 1;
+       item.length = sizeof(*query_engines) +
+                     64 * sizeof(struct drm_i915_engine_info);
You are betting we are not going to exceed 64 engines? A common bet for sure...
Quoted 8 lines
Quoted 4 lines
We've been discussing about this in v4 and we agreed that 64 is big enough[*]. Am I missing anything?
Besides, I thought that we won't have more engines than I915_EXEC_RING_MASK.
Do you think that execbuf2 is our final form? Besides the argument about heap vs stack is more appropriate here; using the stack is more appropriate later.
I can do that in case of 'drm_i915_query_engine_info' because the flexible structure has a name (struct drm_i915_engine_info engines[];).
But here the choices are less pleasant. Because I either do in the kernel something like:
(quoted diff) +1 -1
+       struct whatever_name {
-       struct {
                __u16 engine_class; /* see enum drm_i915_gem_engine_class */
                __u16 engine_instance;
        } class_instance[0];
Or I define some ugly unflexible array in __set_ctx_engine_map():

Quoted 7 lines

        struct {
                __u16 ngine_class;
                __u16 engine_instance;
        } class_instance[I915_EXEC_RING_MASK];
which looks to me quite strict (if we are considering that we might subvert everyting).

You can have an on-stack and off-stack buffer. But in this case since you are returning a heap pointer, just create the heap pointer the right size.

Quoted 6 lines

Or, even worse, some "__u32 engine_stuff[I915_EXEC_RING_MASK]" and cast it.
Allocating it everywhere it looked cleaner.
Whatever you like :)

Around here, I'd rather see what people come up with to see how robust the interface is, and if it's horrible tidy up the iface to prevent that. But for the moment, returning a fixed size heap block when you're being told the correct size, seems silly.
-Chris
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Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #8 lore raw

RFC PATCH v8 3/5 lib/igt_gt: use for_each_engine2 to loop through engines

In reply to Andi Shyti via igt-dev

'for_each_engine2()' defines a loop through the gpu engines.

It can work with both active and pre-defined engines.

In case we are looping through active engines (i.e. the running kernel has the query and get/setparam ioctls), the intel_active_engines2 points to an array that contains only the list engines dynamically allocated after having interrogated the driver.

While, if we are looping through pre-defined engines, intel_active_engines2 points to the 'intel_execution_engines2' array and works exactly as for_each_engine() but using the new 'struct intel_execution_engine2' data type.

Signed-off-by Andi Shyti <[email protected]>

---
 lib/igt_gt.h | 8 ++++++++
 1 file changed, 8 insertions(+)

lib/igt_gt.h +8 -0

index f4bd6c22a81a..7aba4b4e37f1 100644
@@ -30,6 +30,8 @@
 
 #include "i915_drm.h"
 
+#include "i915/gem_query.h"
+
 void igt_require_hang_ring(int fd, int ring);
 
 typedef struct igt_hang {

@@ -86,6 +88,12 @@ extern const struct intel_execution_engine {
 	     e__++) \
 		for_if (gem_ring_has_physical_engine(fd__, flags__ = e__->exec_id | e__->flags))
 
+#define for_each_engine2(fd, ctx, e) \
+		for (__set_ctx_engine_map(fd, ctx_id), \
+		     e = intel_active_engines2; e->name; e++) \
+			for_if (gem_has_get_set_param() || \
+				gem_has_engine(fd, e->class, e->instance))
+
 bool gem_ring_is_physical_engine(int fd, unsigned int ring);
 bool gem_ring_has_physical_engine(int fd, unsigned int ring);

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Chris Wilson

2019-02-13 00:16 UTC #9 lore raw

Re: [igt-dev] [RFC PATCH v8 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

Quoting Andi Shyti (2019-02-12 23:54:34)

Quoted 34 lines

'for_each_engine2()' defines a loop through the gpu engines.
It can work with both active and pre-defined engines.
In case we are looping through active engines (i.e. the running kernel has the query and get/setparam ioctls), the intel_active_engines2 points to an array that contains only the list engines dynamically allocated after having interrogated the driver.
While, if we are looping through pre-defined engines, intel_active_engines2 points to the 'intel_execution_engines2' array and works exactly as for_each_engine() but using the new 'struct intel_execution_engine2' data type.
Signed-off-by Andi Shyti <[email protected]>
---
 lib/igt_gt.h | 8 ++++++++
 1 file changed, 8 insertions(+)
lib/igt_gt.h +2 -0
index f4bd6c22a81a..7aba4b4e37f1 100644
@@ -30,6 +30,8 @@
 
 #include "i915_drm.h"
 
+#include "i915/gem_query.h"
+
 void igt_require_hang_ring(int fd, int ring);
 
 typedef struct igt_hang {

lib/igt_gt.h extern const struct intel_execution_engine { · line 95

Quoted 8 lines

lib/igt_gt.h +5 -0

@@ -86,6 +88,12 @@ extern const struct intel_execution_engine {
             e__++) \
                for_if (gem_ring_has_physical_engine(fd__, flags__ = e__->exec_id | e__->flags))
 
+#define for_each_engine2(fd, ctx, e) \
+               for (__set_ctx_engine_map(fd, ctx_id), \
+                    e = intel_active_engines2; e->name; e++) \
+                       for_if (gem_has_get_set_param() || \
+                               gem_has_engine(fd, e->class, e->instance))

intel_active_engines2 can define e->flags, and then you can just use gem_has_ring(fd, e->flags) for both ctx->engines[] and legacy.

That's one for test/gem_query.c, making sure that set_ctx_engine_map() is fully iterable by gem_has_ring(fd, id).
-Chris
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Andi Shyti via igt-dev

author

2019-02-13 01:20 UTC #10 lore raw

Re: [igt-dev] [RFC PATCH v8 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

Hi Chris,

Quoted 8 lines

lib/igt_gt.h extern const struct intel_execution_engine { · line 95
Quoted 5 lines
lib/igt_gt.h +5 -0
+#define for_each_engine2(fd, ctx, e) \
+               for (__set_ctx_engine_map(fd, ctx_id), \
+                    e = intel_active_engines2; e->name; e++) \
+                       for_if (gem_has_get_set_param() || \
+                               gem_has_engine(fd, e->class, e->instance))
intel_active_engines2 can define e->flags, and then you can just use gem_has_ring(fd, e->flags) for both ctx->engines[] and legacy.

Sorry, I haven't understood: 'e' is 'intel_execution_engine2' and doesn't have flags. Indeed I call it as:

[...]
struct intel_execution_engine2 *e2;

   for_each_engine2(fd, ctx_id, e2) {
      /* whatever */
   }

Thanks,
Andi

Quoted 3 lines

That's one for test/gem_query.c, making sure that set_ctx_engine_map() is fully iterable by gem_has_ring(fd, id).
-Chris

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Chris Wilson

2019-02-13 09:21 UTC #11 lore raw

Re: [igt-dev] [RFC PATCH v8 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

Quoting Andi Shyti (2019-02-13 01:19:56)

Quoted 8 lines

Hi Chris,

Quoted 6 lines

Quoted 5 lines

lib/igt_gt.h +5 -0

+#define for_each_engine2(fd, ctx, e) \
+               for (__set_ctx_engine_map(fd, ctx_id), \
+                    e = intel_active_engines2; e->name; e++) \
+                       for_if (gem_has_get_set_param() || \
+                               gem_has_engine(fd, e->class, e->instance))

Quoted 5 lines

Quoted 2 lines
intel_active_engines2 can define e->flags, and then you can just use gem_has_ring(fd, e->flags) for both ctx->engines[] and legacy.
Sorry, I haven't understood: 'e' is 'intel_execution_engine2' and doesn't have flags. Indeed I call it as:

Then fix it.
-Chris
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Andi Shyti via igt-dev

author

2019-02-13 11:07 UTC #12 lore raw

Re: [igt-dev] [RFC PATCH v8 3/5] lib/igt_gt: use for_each_engine2 to loop through engines

Hi Chris,

Quoted 6 lines

Quoted 5 lines

lib/igt_gt.h +5 -0

+#define for_each_engine2(fd, ctx, e) \
+               for (__set_ctx_engine_map(fd, ctx_id), \
+                    e = intel_active_engines2; e->name; e++) \
+                       for_if (gem_has_get_set_param() || \
+                               gem_has_engine(fd, e->class, e->instance))

Quoted 7 lines

Quoted 5 lines
Quoted 2 lines
intel_active_engines2 can define e->flags, and then you can just use gem_has_ring(fd, e->flags) for both ctx->engines[] and legacy.
Sorry, I haven't understood: 'e' is 'intel_execution_engine2' and doesn't have flags. Indeed I call it as:
Then fix it.

If we want to add flags in 'intel_execution_engine2' (I tried to minimize the amount of changes outside of my part), then the whole thing can come out nicer and I guess could get rid of the 'gem_class_instance_to_eb_flags()' function.

But I think this is a bit off-topic from this patch series and I can add it in my to-do list (which would this way have already two items) for the next days.

Andi
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Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #13 lore raw

RFC PATCH v8 4/5 lib: ioctl_wrappers: reach engines by index as well

In reply to Andi Shyti via igt-dev

With the new engine query method engines are reachable through an index and context they are combined with.

The 'gem_has_ring()' becomes 'gem_has_ring_by_idx()' that requires the index that the engine is mapped with in the driver.

The previous function becomes a wrapper to the new 'gem_has_ring_by_idx()'.

Signed-off-by Andi Shyti <[email protected]>

---
 lib/ioctl_wrappers.c | 10 ++++++----
 lib/ioctl_wrappers.h |  4 +++-
 2 files changed, 9 insertions(+), 5 deletions(-)

lib/ioctl_wrappers.c +6 -4

index 404c2fbf9355..2dd860dbd9d6 100644
@@ -1465,14 +1465,14 @@ void igt_require_gem(int fd)
 	igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_has_ring_by_idx(int fd, unsigned idx, unsigned rsvd1)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
 
 	/* silly ABI, the kernel thinks everyone who has BSD also has BSD2 */
-	if ((ring & ~(3<<13)) == I915_EXEC_BSD) {
-		if (ring & (3 << 13) && !gem_has_bsd2(fd))
+	if ((idx & ~(3<<13)) == I915_EXEC_BSD) {
+		if (idx & (3 << 13) && !gem_has_bsd2(fd))
 			return false;
 	}

@@ -1480,7 +1480,9 @@ bool gem_has_ring(int fd, unsigned ring)
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&exec);
 	execbuf.buffer_count = 1;
-	execbuf.flags = ring;
+	execbuf.flags = idx;
+	execbuf.rsvd1 = rsvd1;
+
 	return __gem_execbuf(fd, &execbuf) == -ENOENT;
 }

lib/ioctl_wrappers.h +3 -1

index b22b36b0b2dd..edf8337faef9 100644
@@ -164,11 +164,13 @@ bool gem_has_exec_fence(int fd);
 
 /* check functions which auto-skip tests by calling igt_skip() */
 void gem_require_caching(int fd);
-bool gem_has_ring(int fd, unsigned ring);
+bool gem_has_ring_by_idx(int fd, unsigned idx, unsigned rsvd1);
 void gem_require_ring(int fd, unsigned ring);
 bool gem_has_mocs_registers(int fd);
 void gem_require_mocs_registers(int fd);
 
+#define gem_has_ring(fd, ring) gem_has_ring_by_idx(fd, ring, 0)
+
 /* prime */
 struct local_dma_buf_sync {
 	uint64_t flags;

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Chris Wilson

2019-02-13 00:19 UTC #14 lore raw

Re: [igt-dev] [RFC PATCH v8 4/5] lib: ioctl_wrappers: reach engines by index as well

Quoting Andi Shyti (2019-02-12 23:54:35)

Quoted 20 lines

With the new engine query method engines are reachable through an index and context they are combined with.
The 'gem_has_ring()' becomes 'gem_has_ring_by_idx()' that requires the index that the engine is mapped with in the driver.
The previous function becomes a wrapper to the new 'gem_has_ring_by_idx()'.
Signed-off-by Andi Shyti <[email protected]>
---
 lib/ioctl_wrappers.c | 10 ++++++----
 lib/ioctl_wrappers.h |  4 +++-
 2 files changed, 9 insertions(+), 5 deletions(-)
lib/ioctl_wrappers.c +0 -0
index 404c2fbf9355..2dd860dbd9d6 100644

lib/ioctl_wrappers.c void igt_require_gem(int fd) · line 1468

Quoted 5 lines

lib/ioctl_wrappers.c +1 -1

@@ -1465,14 +1465,14 @@ void igt_require_gem(int fd)
        igt_require_f(err == 0, "Unresponsive i915/GEM device\n");
 }
 
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_has_ring_by_idx(int fd, unsigned idx, unsigned rsvd1)

__gem_has_ring(int fd, uint32_t ctx, unsigned int ring)

#define gem_has_ring(fd, ring) __gem_has_ring(fd, 0, ring)

* mutters rsvd1!
-Chris
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Andi Shyti via igt-dev

author

2019-02-13 01:11 UTC #15 lore raw

Re: [igt-dev] [RFC PATCH v8 4/5] lib: ioctl_wrappers: reach engines by index as well

Hi Chris,

Quoted 8 lines

lib/ioctl_wrappers.c void igt_require_gem(int fd) · line 1468
Quoted 2 lines
lib/ioctl_wrappers.c +1 -1
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_has_ring_by_idx(int fd, unsigned idx, unsigned rsvd1)
__gem_has_ring(int fd, uint32_t ctx, unsigned int ring)
#define gem_has_ring(fd, ring) __gem_has_ring(fd, 0, ring)
* mutters rsvd1!

Yes, that's quite a controversy: the concept of 'ring' is swapped depending on whether you call 'gem_has_ring' or 'gem_has_ring_by_idx' and I bet there is no naming choice that would please both callers. Unless I use neutral names, like 'a' and 'b', or 'x' and 'y'.

That's why originally I called it 'flags' and 'rsvd1' as they are called in the 'drm_i915_gem_execbuffer2' structure, in order to minimize confusion.

Andi
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Chris Wilson

2019-02-13 09:22 UTC #16 lore raw

Re: [igt-dev] [RFC PATCH v8 4/5] lib: ioctl_wrappers: reach engines by index as well

Quoting Andi Shyti (2019-02-13 01:11:03)

Quoted 17 lines

Hi Chris,
Quoted 8 lines
lib/ioctl_wrappers.c void igt_require_gem(int fd) · line 1468
Quoted 2 lines
lib/ioctl_wrappers.c +1 -1
-bool gem_has_ring(int fd, unsigned ring)
+bool gem_has_ring_by_idx(int fd, unsigned idx, unsigned rsvd1)
__gem_has_ring(int fd, uint32_t ctx, unsigned int ring)
#define gem_has_ring(fd, ring) __gem_has_ring(fd, 0, ring)
* mutters rsvd1!
Yes, that's quite a controversy: the concept of 'ring' is swapped depending on whether you call 'gem_has_ring' or 'gem_has_ring_by_idx' and I bet there is no naming choice that would please both callers. Unless I use neutral names, like 'a' and 'b', or 'x' and 'y'.

Quoted 3 lines

That's why originally I called it 'flags' and 'rsvd1' as they are called in the 'drm_i915_gem_execbuffer2' structure, in order to minimize confusion.

rsvd1 is the ctx id.

This should be gem_context_has_engine() and
#define gem_has_ring(fd, ring) gem_context_has_engine(fd, 0, ring)

The whole designed is that the flags/index should be transparent to the caller, so _by_idx is anathema.
-Chris
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Andi Shyti via igt-dev

author

2019-02-12 23:54 UTC #17 lore raw

RFC PATCH v8 5/5 tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

In reply to Andi Shyti via igt-dev

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic test. The main goal of the test is to get to the engines by using the new API as implemented in in commit 87079e04 ("lib: implement new engine discovery interface").

The "exec-ctx" subtest simply gets the list of engines, binds them to a context and executes a buffer. This is done through a new "for_each_engine_ctx" loop which iterates through the engines.

Signed-off-by Andi Shyti <[email protected]>

---
 tests/i915/gem_exec_basic.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

tests/i915/gem_exec_basic.c +15 -0

index dcb83864b1c1..dc2d79a0c73b 100644
@@ -135,6 +135,21 @@ igt_main
 			gtt(fd, e->exec_id | e->flags);
 	}
 
+	igt_subtest("exec-ctx") {
+		uint32_t ctx_id;
+		struct intel_execution_engine2 *e2;
+		int index_map = 0;
+
+		igt_require_gem_engine_list(fd);
+		ctx_id = gem_context_create(fd);
+
+		for_each_engine2(fd, ctx_id, e2)
+			igt_assert(gem_has_ring_by_idx(fd, ++index_map,
+						       ctx_id));
+
+		gem_context_destroy(fd, ctx_id);
+	}
+
 	igt_fixture {
 		igt_stop_hang_detector();
 		close(fd);

Signature · 6 lines

2.20.1

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Chris Wilson

2019-02-13 00:23 UTC #18 lore raw

Re: [igt-dev] [RFC PATCH v8 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

Quoting Andi Shyti (2019-02-12 23:54:36)

Quoted 24 lines

The "exec-ctx" is a demo subtest inserted in the gem_exec_basic test. The main goal of the test is to get to the engines by using the new API as implemented in in commit 87079e04 ("lib: implement new engine discovery interface").
The "exec-ctx" subtest simply gets the list of engines, binds them to a context and executes a buffer. This is done through a new "for_each_engine_ctx" loop which iterates through the engines.
Signed-off-by Andi Shyti <[email protected]>
---
 tests/i915/gem_exec_basic.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
tests/i915/gem_exec_basic.c +1 -0
index dcb83864b1c1..dc2d79a0c73b 100644
@@ -135,6 +135,21 @@ igt_main
                        gtt(fd, e->exec_id | e->flags);
        }
 
+       igt_subtest("exec-ctx") {

tests/i915/gem_exec_basic.c igt_main · line 148

Quoted 10 lines

tests/i915/gem_exec_basic.c +10 -0

+               uint32_t ctx_id;
+               struct intel_execution_engine2 *e2;
+               int index_map = 0;
+
+               igt_require_gem_engine_list(fd);
+               ctx_id = gem_context_create(fd);
+
+               for_each_engine2(fd, ctx_id, e2)
+                       igt_assert(gem_has_ring_by_idx(fd, ++index_map,
+                                                      ctx_id));

Since the iterator here is e2, it looks quite abusive not to use the iterator... I don't think this serves as a good example of for_each_engine2().
-Chris
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Andi Shyti via igt-dev

author

2019-02-13 01:02 UTC #19 lore raw

Re: [igt-dev] [RFC PATCH v8 5/5] tests: gem_exec_basic: add "exec-ctx" buffer execution demo test

Hi Chris,

Quoted 7 lines

tests/i915/gem_exec_basic.c +7 -0

+       igt_subtest("exec-ctx") {
+               uint32_t ctx_id;
+               struct intel_execution_engine2 *e2;
+               int index_map = 0;
+
+               igt_require_gem_engine_list(fd);
+               ctx_id = gem_context_create(fd);

Quoted 8 lines

tests/i915/gem_exec_basic.c igt_main · line 148
Quoted 4 lines
tests/i915/gem_exec_basic.c +4 -0
+
+               for_each_engine2(fd, ctx_id, e2)
+                       igt_assert(gem_has_ring_by_idx(fd, ++index_map,
+                                                      ctx_id));
Since the iterator here is e2, it looks quite abusive not to use the iterator... I don't think this serves as a good example of for_each_engine2().

I thought about hiding e2 inside for_each_engine2, but I also thought the user might want to use it, e.g.:

  for_each_engine2(fd, ctx_id, e2)
    printf("%s\n", e2->name);

if I keep it hidden then, although it's there, it's not visible. But, yes, I can hide it inside the for_each_engine2 and perhaps have another iterator where e2 is meant to be used.

Thanks,
Andi
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Patchwork

2019-02-13 00:28 UTC #20 lore raw

[igt-dev] ✓ Fi.CI.BAT: success for new engine discovery interface

In reply to Andi Shyti via igt-dev

== Series Details ==

Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/56585/
State : success

== Summary ==

CI Bug Log - changes from IGT_4820 -> IGTPW_2389
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/56585/revisions/1/mbox/

Known issues
------------

Here are the changes found in IGTPW_2389 that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: PASS -> INCOMPLETE [fdo#107718]

* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927]

* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#107362]

* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362]

#### Possible fixes ####

* igt@kms_busy@basic-flip-b:
- fi-gdg-551: FAIL [fdo#103182] -> PASS

* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: FAIL [fdo#109485] -> PASS

* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
- fi-byt-clapper: FAIL [fdo#107362] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (42 -> 37)
------------------------------

Missing (5): fi-ilk-m540 fi-bdw-5557u fi-byt-squawks fi-bsw-cyan fi-pnv-d510

Build changes
-------------

* IGT: IGT_4820 -> IGTPW_2389

CI_DRM_5595: 159160c4276fdbf738e5c19549f07e0c7f0f27a8 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_2389: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2389/
IGT_4820: 368237db1149033d8274248489ffec671ea1f7d8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Testlist changes ==

+igt@gem_exec_basic@exec-ctx

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_2389/
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Patchwork

2019-02-13 02:44 UTC #21 lore raw

[igt-dev] ✓ Fi.CI.IGT: success for new engine discovery interface

In reply to Andi Shyti via igt-dev

== Series Details ==

Series: new engine discovery interface
URL : https://patchwork.freedesktop.org/series/56585/
State : success

== Summary ==

CI Bug Log - changes from IGT_4820_full -> IGTPW_2389_full
====================================================

Summary
-------

**SUCCESS**

No regressions found.

External URL: https://patchwork.freedesktop.org/api/1.0/series/56585/revisions/1/mbox/

New tests
---------

New tests have been introduced between IGT_4820_full and IGTPW_2389_full:
Known issues
------------

Here are the changes found in IGTPW_2389_full that come from known issues:

### IGT changes ###

#### Issues hit ####

* igt@gem_eio@unwedge-stress:
- shard-snb: PASS -> FAIL [fdo#107799]

* igt@i915_suspend@forcewake:
- shard-snb: NOTRUN -> FAIL [fdo#103375]

* igt@kms_cursor_crc@cursor-128x42-onscreen:
- shard-glk: NOTRUN -> FAIL [fdo#103232] +2

* igt@kms_cursor_crc@cursor-size-change:
- shard-glk: PASS -> FAIL [fdo#103232]

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-apl: PASS -> FAIL [fdo#103167] +2

* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-glk: PASS -> FAIL [fdo#108145] +2

* igt@kms_plane_multiple@atomic-pipe-a-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +1

* igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
- shard-glk: NOTRUN -> FAIL [fdo#103166]

* igt@kms_plane_multiple@atomic-pipe-c-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]

* igt@kms_setmode@basic:
- shard-apl: PASS -> FAIL [fdo#99912]

#### Possible fixes ####

* igt@gem_eio@in-flight-internal-10ms:
- shard-glk: FAIL [fdo#107799] -> PASS

* igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
- shard-glk: FAIL [fdo#108145] -> PASS +2

* igt@kms_color@pipe-c-legacy-gamma:
- shard-apl: FAIL [fdo#104782] -> PASS

* igt@kms_cursor_crc@cursor-256x85-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +2

* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
- shard-apl: FAIL [fdo#103167] -> PASS +3

* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-glk: FAIL [fdo#103167] -> PASS +8

* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-apl: FAIL [fdo#108948] -> PASS

* igt@kms_plane@pixel-format-pipe-c-planes-source-clamping:
- shard-glk: FAIL [fdo#108948] -> PASS

* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: FAIL [fdo#108145] -> PASS

* igt@kms_plane_multiple@atomic-pipe-a-tiling-y:
- shard-apl: FAIL [fdo#103166] -> PASS +2

* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-glk: FAIL [fdo#103166] -> PASS +6

* igt@pm_rps@min-max-config-loaded:
- shard-apl: FAIL [fdo#102250] -> PASS

{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).

Participating hosts (6 -> 4)
------------------------------

Missing (2): shard-skl shard-iclb

Build changes
-------------

* IGT: IGT_4820 -> IGTPW_2389

== Logs ==