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arm64: dts: allwinner: h6: Enable CPU DVFS(cpufreq)

PATCH New Yangtao Li 1 participant 5 messages Feb 15, 2019

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Device tree bindings Arm/Allwinner sunXi SoC support
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Yangtao Li

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#0 lore raw

v3 cover arm64: dts: allwinner: h6: Enable CPU DVFS(cpufreq)

Add the cpufreq information of h6 to dts, source of information is as follows.

h6 cpu opp info:
https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi

axp805 spec:
http://linux-sunxi.org/images/b/bc/AXP805_Datasheet_V1.0_en.pdf

Yangtao Li (4):
arm64: dts: allwinner: h6: orangepi: Add CPU supply regulator
arm64: dts: allwinner: h6: pine: Add CPU supply regulator
arm64: dts: allwinner: h6: Add clock to CPU cores
arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

---
v3:
-only update changelog between version
v2:
-remove the opp of 1.8GHz
-update changelog

I tested the opp table on two H6 boards(with the same axp805 pmu), but not the pine board or orangepi board.
---

 .../dts/allwinner/sun50i-h6-orangepi.dtsi     |  8 ++-
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |  8 ++-
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 63 +++++++++++++++++++
 3 files changed, 75 insertions(+), 4 deletions(-)
Signature · 1 line
2.17.0
author
#1 lore raw

PATCH v3 1/4 arm64: dts: allwinner: h6: orangepi: Add CPU supply regulator

The original orangepi use the dcdca to supply the CPU cores. According to the axp805 spec, the range of dcdca is 0.6 to 1.1v, 1.12 to 1.52v. In order to support more CPU frequency, slightly increase the voltage maximum and minimum.

In fact, in sunxi's sdk, the actual minimum and maximum voltage of the cpu is smaller or larger than the datasheet.

For some better quality ic, the minimum voltage can be smaller. For some poor quality ic, the maximum voltage needs to be increased a little.

Signed-off-by Yangtao Li <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi +6 -2
index b2526dac2fcf..e7aebaf91ede 100644
@@ -159,8 +159,8 @@
 
 			reg_dcdca: dcdca {
 				regulator-always-on;
-				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1160000>;
 				regulator-name = "vdd-cpu";
 			};
 

@@ -191,6 +191,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_ph_pins>;
Signature · 1 line
2.17.0
author
#2 lore raw

PATCH v3 2/4 arm64: dts: allwinner: h6: pine: Add CPU supply regulator

In reply to Yangtao Li

The original pine use the dcdca to supply the CPU cores. According to the axp805 spec, the range of dcdca is 0.6 to 1.1v, 1.12 to 1.52v. In order to support more CPU frequency, slightly increase the voltage maximum and minimum.

In fact, in sunxi's sdk, the actual minimum and maximum voltage of the cpu is smaller or larger than the datasheet.

For some better quality ic, the minimum voltage can be smaller. For some poor quality ic, the maximum voltage needs to be increased a little.

Signed-off-by Yangtao Li <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts +6 -2
index bdb8470fc8dc..95c81250c2b3 100644
@@ -213,8 +213,8 @@
 
 			reg_dcdca: dcdca {
 				regulator-always-on;
-				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1160000>;
 				regulator-name = "vdd-cpu";
 			};
 

@@ -251,6 +251,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_ph_pins>;
Signature · 1 line
2.17.0
author
#3 lore raw

PATCH v3 3/4 arm64: dts: allwinner: h6: Add clock to CPU cores

In reply to Yangtao Li

The ARM CPU cores are fed by the CPU clock from the CCU. Add a reference to the clock for each CPU core, along with the clock transition latency.

Signed-off-by Yangtao Li <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +8 -0
index d93a7add67e7..723f5d991a74 100644
@@ -26,6 +26,8 @@
 			device_type = "cpu";
 			reg = <0>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu1: cpu@1 {

@@ -33,6 +35,8 @@
 			device_type = "cpu";
 			reg = <1>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu2: cpu@2 {

@@ -40,6 +44,8 @@
 			device_type = "cpu";
 			reg = <2>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 
 		cpu3: cpu@3 {

@@ -47,6 +53,8 @@
 			device_type = "cpu";
 			reg = <3>;
 			enable-method = "psci";
+			clocks = <&ccu CLK_CPUX>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};
Signature · 1 line
2.17.0
author
#4 lore raw

PATCH v3 4/4 arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

In reply to Yangtao Li

Add an OPP (Operating Performance Points) table for the CPU cores to enable DVFS (Dynamic Voltage & Frequency Scaling) on the H6. This information comes from github.

When the four CPUs are running at 1.8 GHz, 100% busy, it is easy to heat up and make the system restart. And currently H6 does not support the thermal driver, can not get the temperature information of the cpu to control the highest frequency. So temporarily remove the opp of 1.8GHz.

When the four CPUs operate at 1.4 GHz, 100% busy, the temperature is stable at about 90 degrees, and the system can still operate normally.

Signed-off-by Yangtao Li <[email protected]>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 55 ++++++++++++++++++++
 1 file changed, 55 insertions(+)
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +55 -0
index 723f5d991a74..84fb47062fe6 100644
@@ -28,6 +28,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu1: cpu@1 {

@@ -37,6 +39,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu2: cpu@2 {

@@ -46,6 +50,8 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
 		};
 
 		cpu3: cpu@3 {

@@ -55,6 +61,55 @@
 			enable-method = "psci";
 			clocks = <&ccu CLK_CPUX>;
 			clock-latency-ns = <244144>; /* 8 32k periods */
+			operating-points-v2 = <&cpu_opp_table>;
+			#cooling-cells = <2>;
+		};
+	};
+
+	cpu_opp_table: opp_table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp@480000000 {
+			opp-hz = /bits/ 64 <480000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@816000000 {
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <800000 800000 880000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@888000000 {
+			opp-hz = /bits/ 64 <888000000>;
+			opp-microvolt = <800000 800000 940000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1080000000 {
+			opp-hz = /bits/ 64 <1080000000>;
+			opp-microvolt = <840000 840000 1060000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1320000000 {
+			opp-hz = /bits/ 64 <1320000000>;
+			opp-microvolt = <900000 900000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
+		};
+
+		opp@1488000000 {
+			opp-hz = /bits/ 64 <1488000000>;
+			opp-microvolt = <960000 960000 1160000>;
+			clock-latency-ns = <244144>; /* 8 32k periods */
 		};
 	};
Signature · 1 line
2.17.0