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parisc: Add memory barrier to asm pdc and sync instructions

PATCH New Helge Deller 1 participant 1 message Apr 27, 2019 PA-RISC architecture

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Helge Deller

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PATCH 1/1 parisc: Add memory barrier to asm pdc and sync instructions

Add compiler memory barriers to ensure the compiler doesn't reorder memory operations around these instructions.

Cc [email protected] # v4.20+
Fixes 3847dab77421 ("parisc: Add alternative coding infrastructure")
Signed-off-by Helge Deller <[email protected]>
arch/parisc/include/asm/cache.h +2 -2
index c18351cf5876..4016fe1c65a9 100644
@@ -56,10 +56,10 @@ void parisc_setup_cache_timing(void);
 #define asm_io_fdc(addr) asm volatile("fdc %%r0(%0)" \
 			ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
 			ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) \
-			: : "r" (addr))
+			: : "r" (addr) : "memory")
 #define asm_io_sync()	asm volatile("sync" \
 			ALTERNATIVE(ALT_COND_NO_DCACHE, INSN_NOP) \
-			ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :: )
+			ALTERNATIVE(ALT_COND_NO_IOC_FDC, INSN_NOP) :::"memory")
 
 #endif /* ! __ASSEMBLY__ */