parisc: Drop LDCW barrier in CAS code when running UP

PATCH New Helge Deller 1 participant 1 message May 7, 2019 PA-RISC architecture

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Helge Deller

author maintainer

2019-05-07 18:19 UTC #0 lore raw

PATCH 1/1 parisc: Drop LDCW barrier in CAS code when running UP

When running an SMP kernel on a single-CPU machine, we can speed up the CAS code by replacing the LDCW sync barrier with NOP.

Signed-off-by Helge Deller <[email protected]>

arch/parisc/kernel/syscall.S +8 -4

index e54d5e4d3489..97ac707c6bff 100644
@@ -641,7 +641,8 @@ cas_action:
 2:	stw	%r24, 0(%r26)
 	/* Free lock */
 #ifdef CONFIG_SMP
-	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
 	stw	%r20, 0(%sr2,%r20)
 #if ENABLE_LWS_DEBUG

@@ -658,7 +659,8 @@ cas_action:
 	/* Error occurred on load or store */
 	/* Free lock */
 #ifdef CONFIG_SMP
-	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
 	stw	%r20, 0(%sr2,%r20)
 #if ENABLE_LWS_DEBUG

@@ -862,7 +864,8 @@ cas2_action:
 cas2_end:
 	/* Free lock */
 #ifdef CONFIG_SMP
-	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
 	stw	%r20, 0(%sr2,%r20)
 	/* Enable interrupts */

@@ -875,7 +878,8 @@ cas2_end:
 	/* Error occurred on load or store */
 	/* Free lock */
 #ifdef CONFIG_SMP
-	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+98:	LDCW	0(%sr2,%r20), %r1			/* Barrier */
+99:	ALTERNATIVE(98b, 99b, ALT_COND_NO_SMP, INSN_NOP)
 #endif
 	stw	%r20, 0(%sr2,%r20)
 	ssm	PSW_SM_I, %r0