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arm64: dts: rockchip: Add missing configuration pwr amd rst for PCIe

PATCH In review Anand Moon 2 participants 3 messages May 31, 2019 – Jun 2, 2019

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Anand Moon

author
#0 lore raw

PATCH v2 1/1 arm64: dts: rockchip: Add missing configuration pwr amd rst for PCIe

This patch add missing PCIe gpio pin (#PCIE_PWR) for vcc3v3_pcie power regulator node also add missing reset pinctrl (#PCIE_PERST_L) for PCIe node.

Signed-off-by Anand Moon <[email protected]>

---
using schematics: thanks for suggested by Manivannan
[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf

Changes from prevoius patch:
[2] https://patchwork.kernel.org/patch/10968695/

Fix the suject and commit message and corrected the PWR and PERST configuration as per shematics and dts nodes.

---
 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts    | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts  | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 3 +--
 3 files changed, 15 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +7 -0
index 6b059bd7a04f..94e2a59bc1c7 100644
@@ -89,6 +89,8 @@
 
 &pcie0 {
 	ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
 			rockchip,pins =
 				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
+
+		pcie_perst_l: pcie-perst-l {
+			rockchip,pins =
+				<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +7 -0
index 12285c51cceb..665fe09c7c74 100644
@@ -64,6 +64,8 @@
 
 &pcie0 {
 	ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
 			rockchip,pins =
 				<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
+
+		pcie_perst_l: pcie-perst-l {
+			rockchip,pins =
+				<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +1 -2
index c7d48d41e184..3df0cd67b4b2 100644
@@ -55,6 +55,7 @@
 
 	vcc3v3_pcie: vcc3v3-pcie-regulator {
 		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pcie_drv>;

@@ -382,8 +383,6 @@
 
 &pcie0 {
 	num-lanes = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_clkreqn_cpm>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };
Signature · 1 line
2.21.0
#1 lore raw

Hi,

Quoted 24 lines · Anand Moon

This patch add missing PCIe gpio pin (#PCIE_PWR) for vcc3v3_pcie power regulator node also add missing reset pinctrl (#PCIE_PERST_L) for PCIe node.

Signed-off-by Anand Moon <[email protected]>

---
using schematics: thanks for suggested by Manivannan
[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf

Changes from prevoius patch:
[2] https://patchwork.kernel.org/patch/10968695/

Fix the suject and commit message and corrected the PWR and PERST configuration as per shematics and dts nodes.

---
 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts    | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts  | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 3 +--
 3 files changed, 15 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +0 -0
index 6b059bd7a04f..94e2a59bc1c7 100644

arch/arm64/boot/dts/rockchip/rk3399-ficus.dts line 93

Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +2 -0
@@ -89,6 +89,8 @@
 
 &pcie0 {
 	ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;

Looks like ep-gpio is wrong here :/ I probably referred old schematics at that time. Correct pin mapping is,

ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;

And this should be fixed in a separate patch with "Fixes" tag!

Quoted 45 lines
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +5 -0
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
 			rockchip,pins =
 				<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
+
+		pcie_perst_l: pcie-perst-l {
+			rockchip,pins =
+				<4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +7 -0
index 12285c51cceb..665fe09c7c74 100644
@@ -64,6 +64,8 @@
 
 &pcie0 {
 	ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
 			rockchip,pins =
 				<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
 			};
+
+		pcie_perst_l: pcie-perst-l {
+			rockchip,pins =
+				<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 
 	usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +0 -0
index c7d48d41e184..3df0cd67b4b2 100644

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi line 58

Quoted 4 lines
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +1 -0
@@ -55,6 +55,7 @@
 
 	vcc3v3_pcie: vcc3v3-pcie-regulator {
 		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;

Actually the PWR pin mapping is defined in a separate node for both Rock960 and Ficus in respective dts. So defining it here would be wrong as the PWR pin mapping is different for both boards.

Thanks,
Mani

Quoted 15 lines
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +0 -2
 		enable-active-high;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pcie_drv>;

@@ -382,8 +383,6 @@
 
 &pcie0 {
 	num-lanes = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_clkreqn_cpm>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };
Signature · 1 line
2.21.0
author
#2 lore raw

Hi Manivannan,

Thanks for your review comment.

Quoted 37 lines · Manivannan Sadhasivam

Hi,

Quoted 24 lines · Anand Moon

This patch add missing PCIe gpio pin (#PCIE_PWR) for vcc3v3_pcie power regulator node also add missing reset pinctrl (#PCIE_PERST_L) for PCIe node.

Signed-off-by Anand Moon <[email protected]>

---
using schematics: thanks for suggested by Manivannan
[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf

Changes from prevoius patch:
[2] https://patchwork.kernel.org/patch/10968695/

Fix the suject and commit message and corrected the PWR and PERST configuration as per shematics and dts nodes.

---
 arch/arm64/boot/dts/rockchip/rk3399-ficus.dts    | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dts  | 7 +++++++
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 3 +--
 3 files changed, 15 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +0 -0
index 6b059bd7a04f..94e2a59bc1c7 100644

arch/arm64/boot/dts/rockchip/rk3399-ficus.dts line 93

Quoted 5 lines
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +2 -0
@@ -89,6 +89,8 @@
 
 &pcie0 {
      ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;

Looks like ep-gpio is wrong here :/ I probably referred old schematics at that time. Correct pin mapping is,

Quoted 4 lines

ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;

And this should be fixed in a separate patch with "Fixes" tag!

Ok I will changes per the above. I have also check this with the u-boot changes .

Quoted 46 lines
Quoted 46 lines
arch/arm64/boot/dts/rockchip/rk3399-ficus.dts +5 -0
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
                      rockchip,pins =
                              <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
                      };
+
+             pcie_perst_l: pcie-perst-l {
+                     rockchip,pins =
+                             <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+             };
      };
 
      usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dts +7 -0
index 12285c51cceb..665fe09c7c74 100644
@@ -64,6 +64,8 @@
 
 &pcie0 {
      ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
+     pinctrl-names = "default";
+     pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 };
 
 &pinctrl {

@@ -104,6 +106,11 @@
                      rockchip,pins =
                              <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
                      };
+
+             pcie_perst_l: pcie-perst-l {
+                     rockchip,pins =
+                             <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+             };
      };
 
      usb2 {
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +0 -0
index c7d48d41e184..3df0cd67b4b2 100644
@@ -55,6 +55,7 @@
Quoted 8 lines

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi line 58

Quoted 3 lines
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +1 -0
      vcc3v3_pcie: vcc3v3-pcie-regulator {
              compatible = "regulator-fixed";
+             gpio = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>;

Actually the PWR pin mapping is defined in a separate node for both Rock960 and Ficus in respective dts. So defining it here would be wrong as the PWR pin mapping is different for both boards.

Ok Thanks, so I will move the PWR pin nodes the respective dts files.

PCIE_PERST PCIE_PWR
Rock960 GPIO2_A2 GPIO2_A5
Ficus GPIO2_D4 GPIO1_D0 /* reference u-boot */

Pls confirm this is correct.

Best Regards
-Anand

Quoted 2 lines

Thanks,
Mani