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clk: socfpga: stratix10: fix divider entry for the emac clocks

PATCH RESEND Applied Dinh Nguyen 2 participants 2 messages Jun 25, 2019

Subsystems (2)
Common clk Arm/socfpga clock framework support
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Dinh Nguyen

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PATCH RESEND 1/1 clk: socfpga: stratix10: fix divider entry for the emac clocks

The fixed dividers for the emac clocks should be 2 not 4.

Signed-off-by Dinh Nguyen <[email protected]>
---
 drivers/clk/socfpga/clk-s10.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/socfpga/clk-s10.c +2 -2
index 8281dfbf38c2..5bed36e12951 100644
@@ -103,9 +103,9 @@ static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
 	{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
 	  0, 0, 0, 0x3C, 1},
 	{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
-	  0, 0, 4, 0xB0, 0},
+	  0, 0, 2, 0xB0, 0},
 	{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
-	  0, 0, 4, 0xB0, 1},
+	  0, 0, 2, 0xB0, 1},
 	{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
 	  ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 4, 0xB0, 2},
 	{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
Signature · 1 line
2.20.0