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ram: rk3399: Add LPDDR4 support

PATCH In review Jagan Teki 6 participants 122 messages Jul 16, 2019 – Oct 12, 2019 58 messages not in the archive Page 1 of 2

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Arm (32-bit) Arm sub-architectures Common clk Arm Rockchip
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Jagan Teki

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#0 lore raw

v3 cover ram: rk3399: Add LPDDR4 support

This is next revison of lpddr4 support on rk3399 compared to previous set[1]. It has some changes based on the commit orders and squashing few patches together and rest is same.

Thanks to
- YouMin Chen
- Akash Gajjar
- Kever Yang
for supporting all the help on this work.

Changes for v3:
- squash set_rate code in one patch
- tested in Rockpro64 and Rock-PI-4
- order them in proper way
- rebase on master
Changes for v2:
- handle LPDDR4 code as part of CONFIG_RAM_RK3399_LPDDR4
- support data_training and set_rate via sdram_rk3399_ops
- add proper sys_reg_enc macros
- add new patch to rename variable sdram_params with params
- fix few commit messages.

patch 0001 - 0018: add dram config enc macro

patch 0019: configure phy IO in ds odt

patch 0020: add LPDDR4 config

patch 0021 - 0043: lpddr4 data training changes

patch 0044 - 0046: syscon pmu support

patch 0047: set 50MHz ddr clock

patch 0048: set 400MHz ddr clock

patch 0049: LPDDR4-400 timings

patch 0050: LPDDR4-800 timings

patch 0051 - 0052: lpddr4 set rate

patch 0053: enable lpddr4 support on Rockpro64

patch 0054: enable lpddr4 support on Rock-PI 4

patch 0055: add LPDDR-100 timings via dts

patch 0056: use LPDDR-100 timings on Rockpro64

patch 0057: use LPDDR-100 timings on Rock-PI 4

[1] https://patchwork.ozlabs.org/cover/1116734/

Any inputs?
Jagan.

Jagan Teki (57):
ram: rk3399: Add ddrtype enc macro
ram: rk3399: Add channel number encoder macro
ram: rk3399: Add row_3_4 enc macro
ram: rk3399: Add chipinfo macro
ram: rk3399: Add rank enc macro
ram: rk3399: Add column enc macro
ram: rk3399: Add bk enc macro
ram: rk3399: Add dbw enc macro
ram: rk3399: Add cs0_rw macro
ram: rk3399: Add cs1_rw macro
ram: rk3399: Add bw enc macro
ram: rk3399: Rename sys_reg with sys_reg2
ram: rk3399: Update cs0_row to use sys_reg3
ram: rk3399: Update cs1_row to use sys_reg3
ram: rk3399: Add cs1_col enc macro
ram: rk3399: Add ddr version enc macro
ram: rk3399: Add ddrtimingC0
ram: rk3399: Add DdrMode
ram: rk3399: Configure phy IO in ds odt
ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry
ram: rk3399: Add lpddr4 rank mask for ca training
ram: rk3399: Add lpddr4 rank mask for wdql training
ram: rk3399: Move mode_sel assignment
ram: rk3399: Don't wait for PLL lock in lpddr4
ram: rk3399: Avoid two channel ZQ Cal Start at the same time
ram: rk3399: Configure PHY_898, PHY_919 for lpddr4
ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4
ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4
ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4
ram: rk3399: Map chipselect for lpddr4
ram: rk3399: Configure tsel write ca for lpddr4
ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1
ram: rk3399: Add IO settings
ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings
ram: rk3399: Add tsel control clock drive
ram: rk3399: Configure soc odt support
ram: rk3399: Get lpddr4 tsel_rd_en from io settings
ram: rk3399: Update lpddr4 vref based on io settings
ram: rk3399: Update lpddr4 mode_sel based on io settings
ram: rk3399: Update lpddr4 vref_mode_ac
ram: rk3399: Simplify data training first argument
ram: rk3399: Handle data training via ops
ram: rk3399: Add LPPDR4 mr detection
arm: include: rockchip: Add rk3399 pmu file
rockchip: rk3399: syscon: Add pmu support
rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu
clk: rockchip: rk3399: Set 50MHz ddr clock
clk: rockchip: rk3399: Set 400MHz ddr clock
ram: rk3399: Add LPPDDR4-400 timings inc
ram: rk3399: Add LPPDDR4-800 timings inc
ram: rk3399: Add set_rate sdram rk3399 ops
ram: rk3399: Add lpddr4 set rate support
configs: rockpro64: Enable LPDDR4 support
configs: rock-pi-4: Enable LPDDR4 support
rockchip: dts: rk3399: Add LPDDR4-100 timings
rockchip: dts: rk3399: rockpro64: Use LPDDR4-100 dtsi
rockchip: dts: rk3399: rock-pi-4: Use LPDDR4-100 dtsi

 arch/arm/dts/rk3399-rock-pi-4-u-boot.dtsi     |    1 +
 arch/arm/dts/rk3399-rockpro64-u-boot.dtsi     |    1 +
 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi     | 1537 +++++++++++++++
 arch/arm/dts/rk3399-u-boot.dtsi               |    4 +
 .../include/asm/arch-rockchip/pmu_rk3399.h    |   72 +
 .../include/asm/arch-rockchip/sdram_common.h  |   31 +
 .../include/asm/arch-rockchip/sdram_rk3399.h  |   29 +-
 arch/arm/mach-rockchip/rk3399/syscon_rk3399.c |    8 +
 configs/rock-pi-4-rk3399_defconfig            |    1 +
 configs/rockpro64-rk3399_defconfig            |    1 +
 drivers/clk/rockchip/clk_rk3399.c             |    8 +
 drivers/ram/rockchip/Kconfig                  |    7 +
 .../ram/rockchip/sdram-rk3399-lpddr4-400.inc  | 1570 +++++++++++++++
 .../ram/rockchip/sdram-rk3399-lpddr4-800.inc  | 1570 +++++++++++++++
 drivers/ram/rockchip/sdram_rk3399.c           | 1726 ++++++++++++++---
 15 files changed, 6317 insertions(+), 249 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
 create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
 create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
 create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
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author
#1 lore raw

PATCH v3 1/57 ram: rk3399: Add ddrtype enc macro

Add simplified and meaningful macro for ddrtype macro.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index b7549f5d8a..92a4c485c2 100644
@@ -72,6 +72,7 @@ struct sdram_base_params {
 #define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
 #define SYS_REG_ROW_3_4_MASK		1
 #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
 #define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
 #define SYS_REG_RANK_MASK		1
 #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index 9a60c24135..f58836c037 100644
@@ -1076,7 +1076,7 @@ static void dram_all_config(struct dram_info *dram,
 	u32 sys_reg = 0;
 	unsigned int channel, idx;
 
-	sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+	sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
 	sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 
 	for (channel = 0, idx = 0;
Signature · 6 lines
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Reviewed-by on v3 1/57
#2 lore raw

Re: [PATCH v3 01/57] ram: rk3399: Add ddrtype enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for ddrtype macro.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
  2 files changed, 2 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index b7549f5d8a..92a4c485c2 100644
@@ -72,6 +72,7 @@ struct sdram_base_params {
  #define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
  #define SYS_REG_ROW_3_4_MASK		1
  #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
  #define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
  #define SYS_REG_RANK_MASK		1
  #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 9a60c24135..f58836c037 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1082

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -1076,7 +1076,7 @@ static void dram_all_config(struct dram_info *dram,
  	u32 sys_reg = 0;
  	unsigned int channel, idx;
 
-	sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+	sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
  	sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 
  	for (channel = 0, idx = 0;

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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

#4 lore raw

PATCH v3 2/57 ram: rk3399: Add channel number encoder macro

Add simplified and meaningful macro for channel number.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
 drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index 92a4c485c2..076afe2ae3 100644
@@ -73,6 +73,8 @@ struct sdram_base_params {
 #define SYS_REG_ROW_3_4_MASK		1
 #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
 #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
+					SYS_REG_NUM_CH_SHIFT)
 #define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
 #define SYS_REG_RANK_MASK		1
 #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index f58836c037..830311ffa9 100644
@@ -1077,7 +1077,7 @@ static void dram_all_config(struct dram_info *dram,
 	unsigned int channel, idx;
 
 	sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
-	sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
+	sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
 
 	for (channel = 0, idx = 0;
 	     (idx < params->base.num_channels) && (channel < 2);
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-3-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#6 lore raw

Re: [PATCH v3 02/57] ram: rk3399: Add channel number encoder macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for channel number.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 23 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
  drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
  2 files changed, 3 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index 92a4c485c2..076afe2ae3 100644
@@ -73,6 +73,8 @@ struct sdram_base_params {
  #define SYS_REG_ROW_3_4_MASK		1
  #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
  #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
+#define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
+					SYS_REG_NUM_CH_SHIFT)
  #define SYS_REG_RANK_SHIFT(ch)		(11 + (ch) * 16)
  #define SYS_REG_RANK_MASK		1
  #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index f58836c037..830311ffa9 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1083

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -1077,7 +1077,7 @@ static void dram_all_config(struct dram_info *dram,
  	unsigned int channel, idx;
 
  	sys_reg |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);
-	sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
+	sys_reg |= SYS_REG_ENC_NUM_CH(params->base.num_channels);
 
  	for (channel = 0, idx = 0;
  	     (idx < params->base.num_channels) && (channel < 2);

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#7 lore raw

PATCH v3 3/57 ram: rk3399: Add row_3_4 enc macro

In reply to a message not in the archive

Add simplified and meaningful macro for row_3_4.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 076afe2ae3..e5af3eab7e 100644
@@ -71,6 +71,7 @@ struct sdram_base_params {
 #define SYS_REG_NUM_CH_MASK		1
 #define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
 #define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
 #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
 #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
 #define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index 830311ffa9..d97efb6996 100644
@@ -1089,8 +1089,7 @@ static void dram_all_config(struct dram_info *dram,
 		if (params->ch[channel].cap_info.col == 0)
 			continue;
 		idx++;
-		sys_reg |= info->cap_info.row_3_4 <<
-			   SYS_REG_ROW_3_4_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
 		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
 		sys_reg |= (info->cap_info.rank - 1) <<
 			   SYS_REG_RANK_SHIFT(channel);
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-4-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#9 lore raw

Re: [PATCH v3 03/57] ram: rk3399: Add row_3_4 enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for row_3_4.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 076afe2ae3..e5af3eab7e 100644
@@ -71,6 +71,7 @@ struct sdram_base_params {
  #define SYS_REG_NUM_CH_MASK		1
  #define SYS_REG_ROW_3_4_SHIFT(ch)	(30 + (ch))
  #define SYS_REG_ROW_3_4_MASK		1
+#define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
  #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
  #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
  #define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 830311ffa9..d97efb6996 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1095

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1089,8 +1089,7 @@ static void dram_all_config(struct dram_info *dram,
  		if (params->ch[channel].cap_info.col == 0)
  			continue;
  		idx++;
-		sys_reg |= info->cap_info.row_3_4 <<
-			   SYS_REG_ROW_3_4_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
  		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
  		sys_reg |= (info->cap_info.rank - 1) <<
  			   SYS_REG_RANK_SHIFT(channel);

_______________________________________________
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#10 lore raw

PATCH v3 4/57 ram: rk3399: Add chipinfo macro

In reply to a message not in the archive

Add simplified and meaningful macro for chip info.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index e5af3eab7e..2d0be920d9 100644
@@ -73,6 +73,7 @@ struct sdram_base_params {
 #define SYS_REG_ROW_3_4_MASK		1
 #define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
 #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch)		(1 << SYS_REG_CHINFO_SHIFT(ch))
 #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
 #define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
 					SYS_REG_NUM_CH_SHIFT)
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index d97efb6996..874e896369 100644
@@ -1090,7 +1090,7 @@ static void dram_all_config(struct dram_info *dram,
 			continue;
 		idx++;
 		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
-		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CHINFO(channel);
 		sys_reg |= (info->cap_info.rank - 1) <<
 			   SYS_REG_RANK_SHIFT(channel);
 		sys_reg |= (info->cap_info.col - 9) <<
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-5-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#12 lore raw

Re: [PATCH v3 04/57] ram: rk3399: Add chipinfo macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for chip info.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 2 +-
  2 files changed, 2 insertions(+), 1 deletion(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index e5af3eab7e..2d0be920d9 100644
@@ -73,6 +73,7 @@ struct sdram_base_params {
  #define SYS_REG_ROW_3_4_MASK		1
  #define SYS_REG_ENC_ROW_3_4(n, ch)	((n) << (30 + (ch)))
  #define SYS_REG_CHINFO_SHIFT(ch)	(28 + (ch))
+#define SYS_REG_ENC_CHINFO(ch)		(1 << SYS_REG_CHINFO_SHIFT(ch))
  #define SYS_REG_ENC_DDRTYPE(n)		((n) << SYS_REG_DDRTYPE_SHIFT)
  #define SYS_REG_ENC_NUM_CH(n)		(((n) - SYS_REG_NUM_CH_MASK) << \
  					SYS_REG_NUM_CH_SHIFT)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index d97efb6996..874e896369 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1096

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -1090,7 +1090,7 @@ static void dram_all_config(struct dram_info *dram,
  			continue;
  		idx++;
  		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
-		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CHINFO(channel);
  		sys_reg |= (info->cap_info.rank - 1) <<
  			   SYS_REG_RANK_SHIFT(channel);
  		sys_reg |= (info->cap_info.col - 9) <<

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#13 lore raw

PATCH v3 6/57 ram: rk3399: Add column enc macro

In reply to a message not in the archive

Add simplified and meaningful macro for column.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index db9e30126f..e7f15a7cf9 100644
@@ -83,6 +83,7 @@ struct sdram_base_params {
 					 SYS_REG_RANK_SHIFT(ch))
 #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
 #define SYS_REG_COL_MASK		3
+#define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
 #define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
 #define SYS_REG_BK_MASK			1
 #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index c2390a771c..f6a83f2acf 100644
@@ -1092,8 +1092,7 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
 		sys_reg |= SYS_REG_ENC_CHINFO(channel);
 		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
-		sys_reg |= (info->cap_info.col - 9) <<
-			   SYS_REG_COL_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
 			   SYS_REG_BK_SHIFT(channel);
 		sys_reg |= (info->cap_info.cs0_row - 13) <<
Signature · 1 line
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Reviewed-by
#15 lore raw

Re: [PATCH v3 06/57] ram: rk3399: Add column enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for column.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index db9e30126f..e7f15a7cf9 100644
@@ -83,6 +83,7 @@ struct sdram_base_params {
  					 SYS_REG_RANK_SHIFT(ch))
  #define SYS_REG_COL_SHIFT(ch)		(9 + (ch) * 16)
  #define SYS_REG_COL_MASK		3
+#define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
  #define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
  #define SYS_REG_BK_MASK			1
  #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index c2390a771c..f6a83f2acf 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1098

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1092,8 +1092,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= SYS_REG_ENC_ROW_3_4(info->cap_info.row_3_4, channel);
  		sys_reg |= SYS_REG_ENC_CHINFO(channel);
  		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
-		sys_reg |= (info->cap_info.col - 9) <<
-			   SYS_REG_COL_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
  		sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
  			   SYS_REG_BK_SHIFT(channel);
  		sys_reg |= (info->cap_info.cs0_row - 13) <<

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#16 lore raw

PATCH v3 7/57 ram: rk3399: Add bk enc macro

In reply to a message not in the archive

Add simplified and meaningful macro for bk.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index e7f15a7cf9..71062e3e71 100644
@@ -86,6 +86,8 @@ struct sdram_base_params {
 #define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
 #define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
 #define SYS_REG_BK_MASK			1
+#define SYS_REG_ENC_BK(n, ch)		(((n) == 3 ? 0 : 1) << \
+					SYS_REG_BK_SHIFT(ch))
 #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
 #define SYS_REG_CS0_ROW_MASK		3
 #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index f6a83f2acf..b93a6c6c44 100644
@@ -1093,8 +1093,7 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg |= SYS_REG_ENC_CHINFO(channel);
 		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
 		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
-		sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
-			   SYS_REG_BK_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
 		sys_reg |= (info->cap_info.cs0_row - 13) <<
 			    SYS_REG_CS0_ROW_SHIFT(channel);
 		sys_reg |= (info->cap_info.cs1_row - 13) <<
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-8-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#18 lore raw

Re: [PATCH v3 07/57] ram: rk3399: Add bk enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for bk.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 23 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index e7f15a7cf9..71062e3e71 100644
@@ -86,6 +86,8 @@ struct sdram_base_params {
  #define SYS_REG_ENC_COL(n, ch)		(((n) - 9) << SYS_REG_COL_SHIFT(ch))
  #define SYS_REG_BK_SHIFT(ch)		(8 + (ch) * 16)
  #define SYS_REG_BK_MASK			1
+#define SYS_REG_ENC_BK(n, ch)		(((n) == 3 ? 0 : 1) << \
+					SYS_REG_BK_SHIFT(ch))
  #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
  #define SYS_REG_CS0_ROW_MASK		3
  #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index f6a83f2acf..b93a6c6c44 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1099

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1093,8 +1093,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= SYS_REG_ENC_CHINFO(channel);
  		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
  		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
-		sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
-			   SYS_REG_BK_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
  		sys_reg |= (info->cap_info.cs0_row - 13) <<
  			    SYS_REG_CS0_ROW_SHIFT(channel);
  		sys_reg |= (info->cap_info.cs1_row - 13) <<

_______________________________________________
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#19 lore raw

PATCH v3 8/57 ram: rk3399: Add dbw enc macro

In reply to a message not in the archive

Add simplified and meaningful macro for dbw.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 71062e3e71..338f4043e1 100644
@@ -96,6 +96,7 @@ struct sdram_base_params {
 #define SYS_REG_BW_MASK			3
 #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
 #define SYS_REG_DBW_MASK		3
+#define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index b93a6c6c44..b994134fdb 100644
@@ -1100,8 +1100,7 @@ static void dram_all_config(struct dram_info *dram,
 			    SYS_REG_CS1_ROW_SHIFT(channel);
 		sys_reg |= (2 >> info->cap_info.bw) <<
 			   SYS_REG_BW_SHIFT(channel);
-		sys_reg |= (2 >> info->cap_info.dbw) <<
-			   SYS_REG_DBW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-9-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#21 lore raw

Re: [PATCH v3 08/57] ram: rk3399: Add dbw enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for dbw.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 71062e3e71..338f4043e1 100644
@@ -96,6 +96,7 @@ struct sdram_base_params {
  #define SYS_REG_BW_MASK			3
  #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
  #define SYS_REG_DBW_MASK		3
+#define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
  /* Get sdram size decode from reg */
  size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index b93a6c6c44..b994134fdb 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1106

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1100,8 +1100,7 @@ static void dram_all_config(struct dram_info *dram,
  			    SYS_REG_CS1_ROW_SHIFT(channel);
  		sys_reg |= (2 >> info->cap_info.bw) <<
  			   SYS_REG_BW_SHIFT(channel);
-		sys_reg |= (2 >> info->cap_info.dbw) <<
-			   SYS_REG_DBW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

_______________________________________________
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#22 lore raw

PATCH v3 9/57 ram: rk3399: Add cs0_rw macro

In reply to a message not in the archive

Add simplified and meaningful macro for cs0_rw.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index 338f4043e1..ad9726a57c 100644
@@ -90,6 +90,8 @@ struct sdram_base_params {
 					SYS_REG_BK_SHIFT(ch))
 #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
 #define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_ENC_CS0_ROW(n, ch)	(((n) - 13) << \
+					SYS_REG_CS0_ROW_SHIFT(ch))
 #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
 #define SYS_REG_CS1_ROW_MASK		3
 #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index b994134fdb..43cf597828 100644
@@ -1094,8 +1094,7 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
 		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg |= (info->cap_info.cs0_row - 13) <<
-			    SYS_REG_CS0_ROW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
 		sys_reg |= (info->cap_info.cs1_row - 13) <<
 			    SYS_REG_CS1_ROW_SHIFT(channel);
 		sys_reg |= (2 >> info->cap_info.bw) <<
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-10-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#24 lore raw

Re: [PATCH v3 09/57] ram: rk3399: Add cs0_rw macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for cs0_rw.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 23 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index 338f4043e1..ad9726a57c 100644
@@ -90,6 +90,8 @@ struct sdram_base_params {
  					SYS_REG_BK_SHIFT(ch))
  #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
  #define SYS_REG_CS0_ROW_MASK		3
+#define SYS_REG_ENC_CS0_ROW(n, ch)	(((n) - 13) << \
+					SYS_REG_CS0_ROW_SHIFT(ch))
  #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
  #define SYS_REG_CS1_ROW_MASK		3
  #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index b994134fdb..43cf597828 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1100

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1094,8 +1094,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
  		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
  		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg |= (info->cap_info.cs0_row - 13) <<
-			    SYS_REG_CS0_ROW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
  		sys_reg |= (info->cap_info.cs1_row - 13) <<
  			    SYS_REG_CS1_ROW_SHIFT(channel);
  		sys_reg |= (2 >> info->cap_info.bw) <<

_______________________________________________
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#25 lore raw

PATCH v3 10/57 ram: rk3399: Add cs1_rw macro

In reply to a message not in the archive

Add simplified and meaningful macro for cs1_rw.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index ad9726a57c..578db90241 100644
@@ -94,6 +94,8 @@ struct sdram_base_params {
 					SYS_REG_CS0_ROW_SHIFT(ch))
 #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
 #define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \
+					SYS_REG_CS1_ROW_SHIFT(ch))
 #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
 #define SYS_REG_BW_MASK			3
 #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index 43cf597828..a83709f271 100644
@@ -1095,8 +1095,7 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
 		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
-		sys_reg |= (info->cap_info.cs1_row - 13) <<
-			    SYS_REG_CS1_ROW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
 		sys_reg |= (2 >> info->cap_info.bw) <<
 			   SYS_REG_BW_SHIFT(channel);
 		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-11-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#27 lore raw

Re: [PATCH v3 10/57] ram: rk3399: Add cs1_rw macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for cs1_rw.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 23 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index ad9726a57c..578db90241 100644
@@ -94,6 +94,8 @@ struct sdram_base_params {
  					SYS_REG_CS0_ROW_SHIFT(ch))
  #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
  #define SYS_REG_CS1_ROW_MASK		3
+#define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \
+					SYS_REG_CS1_ROW_SHIFT(ch))
  #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
  #define SYS_REG_BW_MASK			3
  #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 43cf597828..a83709f271 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1101

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1095,8 +1095,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= SYS_REG_ENC_COL(info->cap_info.col, channel);
  		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
  		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
-		sys_reg |= (info->cap_info.cs1_row - 13) <<
-			    SYS_REG_CS1_ROW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
  		sys_reg |= (2 >> info->cap_info.bw) <<
  			   SYS_REG_BW_SHIFT(channel);
  		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);

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#28 lore raw

PATCH v3 11/57 ram: rk3399: Add bw enc macro

In reply to a message not in the archive

Add simplified and meaningful macro for bw.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
 drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
 2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 578db90241..4749233226 100644
@@ -98,6 +98,7 @@ struct sdram_base_params {
 					SYS_REG_CS1_ROW_SHIFT(ch))
 #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
 #define SYS_REG_BW_MASK			3
+#define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
 #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
 #define SYS_REG_DBW_MASK		3
 #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
drivers/ram/rockchip/sdram_rk3399.c +1 -2
index a83709f271..2d3f0f6902 100644
@@ -1096,8 +1096,7 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
 		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
 		sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
-		sys_reg |= (2 >> info->cap_info.bw) <<
-			   SYS_REG_BW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
 		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-12-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#30 lore raw

Re: [PATCH v3 11/57] ram: rk3399: Add bw enc macro

Quoted 4 lines · Jagan Teki

Add simplified and meaningful macro for bw.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 22 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 1 +
  drivers/ram/rockchip/sdram_rk3399.c               | 3 +--
  2 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +1 -0
index 578db90241..4749233226 100644
@@ -98,6 +98,7 @@ struct sdram_base_params {
  					SYS_REG_CS1_ROW_SHIFT(ch))
  #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
  #define SYS_REG_BW_MASK			3
+#define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))
  #define SYS_REG_DBW_SHIFT(ch)		((ch) * 16)
  #define SYS_REG_DBW_MASK		3
  #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index a83709f271..2d3f0f6902 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1102

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1096,8 +1096,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
  		sys_reg |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
  		sys_reg |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
-		sys_reg |= (2 >> info->cap_info.bw) <<
-			   SYS_REG_BW_SHIFT(channel);
+		sys_reg |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
  		sys_reg |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;

_______________________________________________
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#31 lore raw

PATCH v3 13/57 ram: rk3399: Update cs0_row to use sys_reg3

In reply to a message not in the archive

cs0_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.

So, update cs0_row macro to make use of both sys_reg2, sys_reg3.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++--
 drivers/ram/rockchip/sdram_rk3399.c               | 4 +++-
 2 files changed, 9 insertions(+), 3 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +6 -2
index 4749233226..f74377225c 100644
@@ -90,8 +90,6 @@ struct sdram_base_params {
 					SYS_REG_BK_SHIFT(ch))
 #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
 #define SYS_REG_CS0_ROW_MASK		3
-#define SYS_REG_ENC_CS0_ROW(n, ch)	(((n) - 13) << \
-					SYS_REG_CS0_ROW_SHIFT(ch))
 #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
 #define SYS_REG_CS1_ROW_MASK		3
 #define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \

@@ -103,6 +101,12 @@ struct sdram_base_params {
 #define SYS_REG_DBW_MASK		3
 #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (5 + 2 * (ch)); \
+		} while (0)
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +3 -1
index 2ef969c07b..70867cbd5f 100644
@@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram,
 			    const struct rk3399_sdram_params *params)
 {
 	u32 sys_reg2 = 0;
+	u32 sys_reg3 = 0;
 	unsigned int channel, idx;
 
 	sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);

@@ -1094,10 +1095,10 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
 		sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
 		sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
 		sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
 		sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+		SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;

@@ -1119,6 +1120,7 @@ static void dram_all_config(struct dram_info *dram,
 	}
 
 	writel(sys_reg2, &dram->pmugrf->os_reg2);
+	writel(sys_reg3, &dram->pmugrf->os_reg3);
 	rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
 		     params->base.stride << 10);
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-14-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#33 lore raw

Re: [PATCH v3 13/57] ram: rk3399: Update cs0_row to use sys_reg3

Quoted 8 lines · Jagan Teki

cs0_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.

So, update cs0_row macro to make use of both sys_reg2, sys_reg3.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 56 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++--
  drivers/ram/rockchip/sdram_rk3399.c               | 4 +++-
  2 files changed, 9 insertions(+), 3 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +6 -2
index 4749233226..f74377225c 100644
@@ -90,8 +90,6 @@ struct sdram_base_params {
  					SYS_REG_BK_SHIFT(ch))
  #define SYS_REG_CS0_ROW_SHIFT(ch)	(6 + (ch) * 16)
  #define SYS_REG_CS0_ROW_MASK		3
-#define SYS_REG_ENC_CS0_ROW(n, ch)	(((n) - 13) << \
-					SYS_REG_CS0_ROW_SHIFT(ch))
  #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
  #define SYS_REG_CS1_ROW_MASK		3
  #define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \

@@ -103,6 +101,12 @@ struct sdram_base_params {
  #define SYS_REG_DBW_MASK		3
  #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
+#define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (5 + 2 * (ch)); \
+		} while (0)
+
  /* Get sdram size decode from reg */
  size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +2 -1
index 2ef969c07b..70867cbd5f 100644
@@ -1074,6 +1074,7 @@ static void dram_all_config(struct dram_info *dram,
  			    const struct rk3399_sdram_params *params)
  {
  	u32 sys_reg2 = 0;
+	u32 sys_reg3 = 0;
  	unsigned int channel, idx;
 
  	sys_reg2 |= SYS_REG_ENC_DDRTYPE(params->base.dramtype);

@@ -1094,10 +1095,10 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
  		sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
  		sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg2 |= SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, channel);
  		sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
  		sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
  		sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
+		SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1126

Quoted 7 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -0
@@ -1119,6 +1120,7 @@ static void dram_all_config(struct dram_info *dram,
  	}
 
  	writel(sys_reg2, &dram->pmugrf->os_reg2);
+	writel(sys_reg3, &dram->pmugrf->os_reg3);
  	rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
  		     params->base.stride << 10);

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#34 lore raw

PATCH v3 14/57 ram: rk3399: Update cs1_row to use sys_reg3

In reply to a message not in the archive

cs1_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.

So, update cs1_row macro to make use of both sys_reg2, sys_reg3.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 10 ++++++++--
 drivers/ram/rockchip/sdram_rk3399.c               |  4 +++-
 2 files changed, 11 insertions(+), 3 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +8 -2
index f74377225c..9cd9f3b969 100644
@@ -92,8 +92,6 @@ struct sdram_base_params {
 #define SYS_REG_CS0_ROW_MASK		3
 #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
 #define SYS_REG_CS1_ROW_MASK		3
-#define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \
-					SYS_REG_CS1_ROW_SHIFT(ch))
 #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
 #define SYS_REG_BW_MASK			3
 #define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))

@@ -107,6 +105,14 @@ struct sdram_base_params {
 				     (5 + 2 * (ch)); \
 		} while (0)
 
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+			(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+			(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (4 + 2 * (ch)); \
+		} while (0)
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +3 -1
index 70867cbd5f..1222da39c2 100644
@@ -1095,10 +1095,12 @@ static void dram_all_config(struct dram_info *dram,
 		sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
 		sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
 		sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);
-		sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
 		sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
 		sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
 		SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+		if (info->cap_info.cs1_row)
+			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
+					    sys_reg3, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;
Signature · 1 line
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Reviewed-by
#36 lore raw

Re: [PATCH v3 14/57] ram: rk3399: Update cs1_row to use sys_reg3

Quoted 8 lines · Jagan Teki

cs1_row can handle the pmu via sys_reg2 and sys_reg3 while configuring the dram instead of just sys_reg2.

So, update cs1_row macro to make use of both sys_reg2, sys_reg3.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 41 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 10 ++++++++--
  drivers/ram/rockchip/sdram_rk3399.c               |  4 +++-
  2 files changed, 11 insertions(+), 3 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_common.h +8 -2
index f74377225c..9cd9f3b969 100644
@@ -92,8 +92,6 @@ struct sdram_base_params {
  #define SYS_REG_CS0_ROW_MASK		3
  #define SYS_REG_CS1_ROW_SHIFT(ch)	(4 + (ch) * 16)
  #define SYS_REG_CS1_ROW_MASK		3
-#define SYS_REG_ENC_CS1_ROW(n, ch)	(((n) - 13) << \
-					SYS_REG_CS1_ROW_SHIFT(ch))
  #define SYS_REG_BW_SHIFT(ch)		(2 + (ch) * 16)
  #define SYS_REG_BW_MASK			3
  #define SYS_REG_ENC_BW(n, ch)		((2 >> (n)) << SYS_REG_BW_SHIFT(ch))

@@ -107,6 +105,14 @@ struct sdram_base_params {
  				     (5 + 2 * (ch)); \
  		} while (0)
 
+#define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
+			(os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
+			(os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
+			(os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
+			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
+				     (4 + 2 * (ch)); \
+		} while (0)
+
  /* Get sdram size decode from reg */
  size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 70867cbd5f..1222da39c2 100644
@@ -1095,10 +1095,12 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg2 |= SYS_REG_ENC_RANK(info->cap_info.rank, channel);
  		sys_reg2 |= SYS_REG_ENC_COL(info->cap_info.col, channel);
  		sys_reg2 |= SYS_REG_ENC_BK(info->cap_info.bk, channel);

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1106

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +3 -1
-		sys_reg2 |= SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, channel);
  		sys_reg2 |= SYS_REG_ENC_BW(info->cap_info.bw, channel);
  		sys_reg2 |= SYS_REG_ENC_DBW(info->cap_info.dbw, channel);
  		SYS_REG_ENC_CS0_ROW(info->cap_info.cs0_row, sys_reg2, sys_reg3, channel);
+		if (info->cap_info.cs1_row)
+			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
+					    sys_reg3, channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

_______________________________________________
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[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#37 lore raw

PATCH v3 15/57 ram: rk3399: Add cs1_col enc macro

In reply to a message not in the archive

Add dram config macro for handling cs1 column.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++
 drivers/ram/rockchip/sdram_rk3399.c               | 1 +
 2 files changed, 4 insertions(+)
arch/arm/include/asm/arch-rockchip/sdram_common.h +3 -0
index 9cd9f3b969..f5c99fea8b 100644
@@ -113,6 +113,9 @@ struct sdram_base_params {
 				     (4 + 2 * (ch)); \
 		} while (0)
 
+#define SYS_REG_CS1_COL_SHIFT(ch)	(0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +1 -0
index 1222da39c2..0f28163d6e 100644
@@ -1101,6 +1101,7 @@ static void dram_all_config(struct dram_info *dram,
 		if (info->cap_info.cs1_row)
 			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
 					    sys_reg3, channel);
+		sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;
Signature · 1 line
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Reviewed-by
#39 lore raw

Re: [PATCH v3 15/57] ram: rk3399: Add cs1_col enc macro

Quoted 4 lines · Jagan Teki

Add dram config macro for handling cs1 column.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 24 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++
  drivers/ram/rockchip/sdram_rk3399.c               | 1 +
  2 files changed, 4 insertions(+)
arch/arm/include/asm/arch-rockchip/sdram_common.h +3 -0
index 9cd9f3b969..f5c99fea8b 100644
@@ -113,6 +113,9 @@ struct sdram_base_params {
  				     (4 + 2 * (ch)); \
  		} while (0)
 
+#define SYS_REG_CS1_COL_SHIFT(ch)	(0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << SYS_REG_CS1_COL_SHIFT(ch))
+
  /* Get sdram size decode from reg */
  size_t rockchip_sdram_size(phys_addr_t reg);
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 1222da39c2..0f28163d6e 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1107

Quoted 7 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -0
@@ -1101,6 +1101,7 @@ static void dram_all_config(struct dram_info *dram,
  		if (info->cap_info.cs1_row)
  			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
  					    sys_reg3, channel);
+		sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

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#40 lore raw

PATCH v3 16/57 ram: rk3399: Add ddr version enc macro

In reply to a message not in the archive

Add dram config macro for handling ddr version number.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
 drivers/ram/rockchip/sdram_rk3399.c               | 1 +
 2 files changed, 3 insertions(+)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index f5c99fea8b..8027b53636 100644
@@ -66,6 +66,7 @@ struct sdram_base_params {
  * [1:0]	dbw_ch0
 */
 #define SYS_REG_DDRTYPE_SHIFT		13
+#define DDR_SYS_REG_VERSION		2
 #define SYS_REG_DDRTYPE_MASK		7
 #define SYS_REG_NUM_CH_SHIFT		12
 #define SYS_REG_NUM_CH_MASK		1

@@ -99,6 +100,7 @@ struct sdram_base_params {
 #define SYS_REG_DBW_MASK		3
 #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
+#define SYS_REG_ENC_VERSION(n)		((n) << 28)
 #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
 			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
 			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
drivers/ram/rockchip/sdram_rk3399.c +1 -0
index 0f28163d6e..7f6f7d8a9a 100644
@@ -1102,6 +1102,7 @@ static void dram_all_config(struct dram_info *dram,
 			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
 					    sys_reg3, channel);
 		sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
+		sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
 
 		ddr_msch_regs = dram->chan[channel].msch;
 		noc_timing = &params->ch[channel].noc_timings;
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-17-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#42 lore raw

Re: [PATCH v3 16/57] ram: rk3399: Add ddr version enc macro

Quoted 4 lines · Jagan Teki

Add dram config macro for handling ddr version number.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 30 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 2 ++
  drivers/ram/rockchip/sdram_rk3399.c               | 1 +
  2 files changed, 3 insertions(+)
arch/arm/include/asm/arch-rockchip/sdram_common.h +2 -0
index f5c99fea8b..8027b53636 100644
@@ -66,6 +66,7 @@ struct sdram_base_params {
   * [1:0]	dbw_ch0
  */
  #define SYS_REG_DDRTYPE_SHIFT		13
+#define DDR_SYS_REG_VERSION		2
  #define SYS_REG_DDRTYPE_MASK		7
  #define SYS_REG_NUM_CH_SHIFT		12
  #define SYS_REG_NUM_CH_MASK		1

@@ -99,6 +100,7 @@ struct sdram_base_params {
  #define SYS_REG_DBW_MASK		3
  #define SYS_REG_ENC_DBW(n, ch)		((2 >> (n)) << SYS_REG_DBW_SHIFT(ch))
 
+#define SYS_REG_ENC_VERSION(n)		((n) << 28)
  #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
  			(os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
  			(os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 0f28163d6e..7f6f7d8a9a 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1108

Quoted 7 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -0
@@ -1102,6 +1102,7 @@ static void dram_all_config(struct dram_info *dram,
  			SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
  					    sys_reg3, channel);
  		sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
+		sys_reg3 |= SYS_REG_ENC_VERSION(DDR_SYS_REG_VERSION);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

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#43 lore raw

PATCH v3 17/57 ram: rk3399: Add ddrtimingC0

In reply to a message not in the archive

Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during lpddr4 setup related configs.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 12 +++++++++++-
 drivers/ram/rockchip/sdram_rk3399.c               |  2 +-
 2 files changed, 12 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +11 -1
index 471702f935..7f41a67242 100644
@@ -18,6 +18,16 @@ struct rk3399_ddr_pi_regs {
 	u32 denali_pi[200];
 };
 
+union noc_ddrtimingc0 {
+	u32 d32;
+	struct {
+		unsigned burstpenalty : 4;
+		unsigned reserved0 : 4;
+		unsigned wrtomwr : 6;
+		unsigned reserved1 : 18;
+	} b;
+};
+
 struct rk3399_msch_regs {
 	u32 coreid;
 	u32 revisionid;

@@ -36,7 +46,7 @@ struct rk3399_msch_regs {
 struct rk3399_msch_timings {
 	u32 ddrtiminga0;
 	u32 ddrtimingb0;
-	u32 ddrtimingc0;
+	union noc_ddrtimingc0 ddrtimingc0;
 	u32 devtodev0;
 	u32 ddrmode;
 	u32 agingx0;
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index 7f6f7d8a9a..e916448fc0 100644
@@ -1110,7 +1110,7 @@ static void dram_all_config(struct dram_info *dram,
 		       &ddr_msch_regs->ddrtiminga0);
 		writel(noc_timing->ddrtimingb0,
 		       &ddr_msch_regs->ddrtimingb0);
-		writel(noc_timing->ddrtimingc0,
+		writel(noc_timing->ddrtimingc0.d32,
 		       &ddr_msch_regs->ddrtimingc0);
 		writel(noc_timing->devtodev0,
 		       &ddr_msch_regs->devtodev0);
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-18-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#45 lore raw

Re: [PATCH v3 17/57] ram: rk3399: Add ddrtimingC0

Quoted 6 lines · Jagan Teki

Add DdrTimingC0 structure with associated bit fields.

These would help to reconfigure sdram capabilities during lpddr4 setup related configs.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 40 lines
---
  arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 12 +++++++++++-
  drivers/ram/rockchip/sdram_rk3399.c               |  2 +-
  2 files changed, 12 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +11 -1
index 471702f935..7f41a67242 100644
@@ -18,6 +18,16 @@ struct rk3399_ddr_pi_regs {
  	u32 denali_pi[200];
  };
 
+union noc_ddrtimingc0 {
+	u32 d32;
+	struct {
+		unsigned burstpenalty : 4;
+		unsigned reserved0 : 4;
+		unsigned wrtomwr : 6;
+		unsigned reserved1 : 18;
+	} b;
+};
+
  struct rk3399_msch_regs {
  	u32 coreid;
  	u32 revisionid;

@@ -36,7 +46,7 @@ struct rk3399_msch_regs {
  struct rk3399_msch_timings {
  	u32 ddrtiminga0;
  	u32 ddrtimingb0;
-	u32 ddrtimingc0;
+	union noc_ddrtimingc0 ddrtimingc0;
  	u32 devtodev0;
  	u32 ddrmode;
  	u32 agingx0;
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 7f6f7d8a9a..e916448fc0 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1116

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -1110,7 +1110,7 @@ static void dram_all_config(struct dram_info *dram,
  		       &ddr_msch_regs->ddrtiminga0);
  		writel(noc_timing->ddrtimingb0,
  		       &ddr_msch_regs->ddrtimingb0);
-		writel(noc_timing->ddrtimingc0,
+		writel(noc_timing->ddrtimingc0.d32,
  		       &ddr_msch_regs->ddrtimingc0);
  		writel(noc_timing->devtodev0,
  		       &ddr_msch_regs->devtodev0);

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#46 lore raw

PATCH v3 18/57 ram: rk3399: Add DdrMode

In reply to a message not in the archive

Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during lpddr4 setup related configs.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 .../include/asm/arch-rockchip/sdram_rk3399.h    | 17 ++++++++++++++++-
 drivers/ram/rockchip/sdram_rk3399.c             |  2 +-
 2 files changed, 17 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +16 -1
index 7f41a67242..dc65ae7924 100644
@@ -28,6 +28,21 @@ union noc_ddrtimingc0 {
 	} b;
 };
 
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge : 1;
+		unsigned bypassfiltering : 1;
+		unsigned fawbank : 1;
+		unsigned burstsize : 2;
+		unsigned mwrsize : 2;
+		unsigned reserved2 : 1;
+		unsigned forceorder : 8;
+		unsigned forceorderstate : 8;
+		unsigned reserved3 : 8;
+	} b;
+};
+
 struct rk3399_msch_regs {
 	u32 coreid;
 	u32 revisionid;

@@ -48,7 +63,7 @@ struct rk3399_msch_timings {
 	u32 ddrtimingb0;
 	union noc_ddrtimingc0 ddrtimingc0;
 	u32 devtodev0;
-	u32 ddrmode;
+	union noc_ddrmode ddrmode;
 	u32 agingx0;
 };
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index e916448fc0..e4723c7d59 100644
@@ -1114,7 +1114,7 @@ static void dram_all_config(struct dram_info *dram,
 		       &ddr_msch_regs->ddrtimingc0);
 		writel(noc_timing->devtodev0,
 		       &ddr_msch_regs->devtodev0);
-		writel(noc_timing->ddrmode,
+		writel(noc_timing->ddrmode.d32,
 		       &ddr_msch_regs->ddrmode);
 
 		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-19-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#48 lore raw

Re: [PATCH v3 18/57] ram: rk3399: Add DdrMode

Quoted 6 lines · Jagan Teki

Add DdrMode structure with associated bit fields.

These would help to reconfigure sdram capabilities during lpddr4 setup related configs.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 45 lines
---
  .../include/asm/arch-rockchip/sdram_rk3399.h    | 17 ++++++++++++++++-
  drivers/ram/rockchip/sdram_rk3399.c             |  2 +-
  2 files changed, 17 insertions(+), 2 deletions(-)
arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +16 -1
index 7f41a67242..dc65ae7924 100644
@@ -28,6 +28,21 @@ union noc_ddrtimingc0 {
  	} b;
  };
 
+union noc_ddrmode {
+	u32 d32;
+	struct {
+		unsigned autoprecharge : 1;
+		unsigned bypassfiltering : 1;
+		unsigned fawbank : 1;
+		unsigned burstsize : 2;
+		unsigned mwrsize : 2;
+		unsigned reserved2 : 1;
+		unsigned forceorder : 8;
+		unsigned forceorderstate : 8;
+		unsigned reserved3 : 8;
+	} b;
+};
+
  struct rk3399_msch_regs {
  	u32 coreid;
  	u32 revisionid;

@@ -48,7 +63,7 @@ struct rk3399_msch_timings {
  	u32 ddrtimingb0;
  	union noc_ddrtimingc0 ddrtimingc0;
  	u32 devtodev0;
-	u32 ddrmode;
+	union noc_ddrmode ddrmode;
  	u32 agingx0;
  };
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index e916448fc0..e4723c7d59 100644

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1120

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -1114,7 +1114,7 @@ static void dram_all_config(struct dram_info *dram,
  		       &ddr_msch_regs->ddrtimingc0);
  		writel(noc_timing->devtodev0,
  		       &ddr_msch_regs->devtodev0);
-		writel(noc_timing->ddrmode,
+		writel(noc_timing->ddrmode.d32,
  		       &ddr_msch_regs->ddrmode);
 
  		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */

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#49 lore raw

PATCH v3 19/57 ram: rk3399: Configure phy IO in ds odt

In reply to a message not in the archive

Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt.

For those cases the set_ds_odt would be an initial call to setup the phy.

To satisfy all the cases, trigger phy IO from set_ds_odt.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------
 1 file changed, 162 insertions(+), 165 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +162 -165
index e4723c7d59..a49677285d 100644
@@ -188,6 +188,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
 		writel(0x2EC7FFFF, &denali_pi[34]);
 }
 
+static int phy_io_config(const struct chan_info *chan,
+			 const struct rk3399_sdram_params *params)
+{
+	u32 *denali_phy = chan->publ->denali_phy;
+	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
+	u32 mode_sel;
+	u32 reg_value;
+	u32 drv_value, odt_value;
+	u32 speed;
+
+	/* vref setting */
+	if (params->base.dramtype == LPDDR4) {
+		/* LPDDR4 */
+		vref_mode_dq = 0x6;
+		vref_value_dq = 0x1f;
+		vref_mode_ac = 0x6;
+		vref_value_ac = 0x1f;
+	} else if (params->base.dramtype == LPDDR3) {
+		if (params->base.odt == 1) {
+			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
+			drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+			odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+			if (drv_value == PHY_DRV_ODT_48) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x16;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x26;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x36;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else if (drv_value == PHY_DRV_ODT_40) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x19;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x23;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x31;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else if (drv_value == PHY_DRV_ODT_34_3) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x17;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x20;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x2e;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else {
+				debug("Invalid DRV value.\n");
+				return -EINVAL;
+			}
+		} else {
+			vref_mode_dq = 0x2;  /* LPDDR3 */
+			vref_value_dq = 0x1f;
+		}
+		vref_mode_ac = 0x2;
+		vref_value_ac = 0x1f;
+	} else if (params->base.dramtype == DDR3) {
+		/* DDR3L */
+		vref_mode_dq = 0x1;
+		vref_value_dq = 0x1f;
+		vref_mode_ac = 0x1;
+		vref_value_ac = 0x1f;
+	} else {
+		debug("Unknown DRAM type.\n");
+		return -EINVAL;
+	}
+
+	reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+	/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+	clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+	clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+	clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+	/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+	clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+	reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+	if (params->base.dramtype == LPDDR4)
+		mode_sel = 0x6;
+	else if (params->base.dramtype == LPDDR3)
+		mode_sel = 0x0;
+	else if (params->base.dramtype == DDR3)
+		mode_sel = 0x1;
+	else
+		return -EINVAL;
+
+	/* PHY_924 PHY_PAD_FDBK_DRIVE */
+	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+	/* PHY_926 PHY_PAD_DATA_DRIVE */
+	clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+	/* PHY_927 PHY_PAD_DQS_DRIVE */
+	clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+	/* PHY_928 PHY_PAD_ADDR_DRIVE */
+	clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+	/* PHY_929 PHY_PAD_CLK_DRIVE */
+	clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+	/* PHY_935 PHY_PAD_CKE_DRIVE */
+	clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+	/* PHY_937 PHY_PAD_RST_DRIVE */
+	clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+	/* PHY_939 PHY_PAD_CS_DRIVE */
+	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+	/* speed setting */
+	if (params->base.ddr_freq < 400)
+		speed = 0x0;
+	else if (params->base.ddr_freq < 800)
+		speed = 0x1;
+	else if (params->base.ddr_freq < 1200)
+		speed = 0x2;
+	else
+		speed = 0x3;
+
+	/* PHY_924 PHY_PAD_FDBK_DRIVE */
+	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+	/* PHY_926 PHY_PAD_DATA_DRIVE */
+	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+	/* PHY_927 PHY_PAD_DQS_DRIVE */
+	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+	/* PHY_928 PHY_PAD_ADDR_DRIVE */
+	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+	/* PHY_929 PHY_PAD_CLK_DRIVE */
+	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+	/* PHY_935 PHY_PAD_CKE_DRIVE */
+	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+	/* PHY_937 PHY_PAD_RST_DRIVE */
+	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+	/* PHY_939 PHY_PAD_CS_DRIVE */
+	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+	return 0;
+}
+
 static void set_ds_odt(const struct chan_info *chan,
 		       const struct rk3399_sdram_params *params)
 {

@@ -332,6 +492,8 @@ static void set_ds_odt(const struct chan_info *chan,
 
 	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
+
+	phy_io_config(chan, params);
 }
 
 static void pctl_start(struct dram_info *dram, u8 channel)

@@ -376,166 +538,6 @@ static void pctl_start(struct dram_info *dram, u8 channel)
 			dram->pwrup_srefresh_exit[channel]);
 }
 
-static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *params)
-{
-	u32 *denali_phy = chan->publ->denali_phy;
-	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
-	u32 mode_sel;
-	u32 reg_value;
-	u32 drv_value, odt_value;
-	u32 speed;
-
-	/* vref setting */
-	if (params->base.dramtype == LPDDR4) {
-		/* LPDDR4 */
-		vref_mode_dq = 0x6;
-		vref_value_dq = 0x1f;
-		vref_mode_ac = 0x6;
-		vref_value_ac = 0x1f;
-	} else if (params->base.dramtype == LPDDR3) {
-		if (params->base.odt == 1) {
-			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
-			drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
-			odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
-			if (drv_value == PHY_DRV_ODT_48) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x16;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x26;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x36;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else if (drv_value == PHY_DRV_ODT_40) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x19;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x23;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x31;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else if (drv_value == PHY_DRV_ODT_34_3) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x17;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x20;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x2e;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else {
-				debug("Invalid DRV value.\n");
-				return -EINVAL;
-			}
-		} else {
-			vref_mode_dq = 0x2;  /* LPDDR3 */
-			vref_value_dq = 0x1f;
-		}
-		vref_mode_ac = 0x2;
-		vref_value_ac = 0x1f;
-	} else if (params->base.dramtype == DDR3) {
-		/* DDR3L */
-		vref_mode_dq = 0x1;
-		vref_value_dq = 0x1f;
-		vref_mode_ac = 0x1;
-		vref_value_ac = 0x1f;
-	} else {
-		debug("Unknown DRAM type.\n");
-		return -EINVAL;
-	}
-
-	reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
-
-	/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
-	clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
-	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
-	clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
-	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
-	clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
-	/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
-	clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
-
-	reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
-
-	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
-	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
-
-	if (params->base.dramtype == LPDDR4)
-		mode_sel = 0x6;
-	else if (params->base.dramtype == LPDDR3)
-		mode_sel = 0x0;
-	else if (params->base.dramtype == DDR3)
-		mode_sel = 0x1;
-	else
-		return -EINVAL;
-
-	/* PHY_924 PHY_PAD_FDBK_DRIVE */
-	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
-	/* PHY_926 PHY_PAD_DATA_DRIVE */
-	clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
-	/* PHY_927 PHY_PAD_DQS_DRIVE */
-	clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
-	/* PHY_928 PHY_PAD_ADDR_DRIVE */
-	clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
-	/* PHY_929 PHY_PAD_CLK_DRIVE */
-	clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
-	/* PHY_935 PHY_PAD_CKE_DRIVE */
-	clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
-	/* PHY_937 PHY_PAD_RST_DRIVE */
-	clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
-	/* PHY_939 PHY_PAD_CS_DRIVE */
-	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
-	/* speed setting */
-	if (params->base.ddr_freq < 400)
-		speed = 0x0;
-	else if (params->base.ddr_freq < 800)
-		speed = 0x1;
-	else if (params->base.ddr_freq < 1200)
-		speed = 0x2;
-	else
-		speed = 0x3;
-
-	/* PHY_924 PHY_PAD_FDBK_DRIVE */
-	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
-	/* PHY_926 PHY_PAD_DATA_DRIVE */
-	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
-	/* PHY_927 PHY_PAD_DQS_DRIVE */
-	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
-	/* PHY_928 PHY_PAD_ADDR_DRIVE */
-	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
-	/* PHY_929 PHY_PAD_CLK_DRIVE */
-	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
-	/* PHY_935 PHY_PAD_CKE_DRIVE */
-	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
-	/* PHY_937 PHY_PAD_RST_DRIVE */
-	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
-	/* PHY_939 PHY_PAD_CS_DRIVE */
-	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
-
-	return 0;
-}
-
 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 		    u32 channel, const struct rk3399_sdram_params *params)
 {

@@ -545,7 +547,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	const u32 *params_ctl = params->pctl_regs.denali_ctl;
 	const u32 *params_phy = params->phy_regs.denali_phy;
 	u32 tmp, tmp1, tmp2;
-	int ret;
 
 	/*
 	 * work around controller bug:

@@ -623,10 +624,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
 	clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 
-	ret = phy_io_config(chan, params);
-	if (ret)
-		return ret;
-
 	return 0;
 }
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-20-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#51 lore raw

Re: [PATCH v3 19/57] ram: rk3399: Configure phy IO in ds odt

Quoted 9 lines · Jagan Teki

Some dramtypes like lpddr4 initialization would required to configure phy IO even after pctl_cfg and after set_ds_odt.

For those cases the set_ds_odt would be an initial call to setup the phy.

To satisfy all the cases, trigger phy IO from set_ds_odt.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 360 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------
  1 file changed, 162 insertions(+), 165 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +162 -161
index e4723c7d59..a49677285d 100644
@@ -188,6 +188,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  		writel(0x2EC7FFFF, &denali_pi[34]);
  }
 
+static int phy_io_config(const struct chan_info *chan,
+			 const struct rk3399_sdram_params *params)
+{
+	u32 *denali_phy = chan->publ->denali_phy;
+	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
+	u32 mode_sel;
+	u32 reg_value;
+	u32 drv_value, odt_value;
+	u32 speed;
+
+	/* vref setting */
+	if (params->base.dramtype == LPDDR4) {
+		/* LPDDR4 */
+		vref_mode_dq = 0x6;
+		vref_value_dq = 0x1f;
+		vref_mode_ac = 0x6;
+		vref_value_ac = 0x1f;
+	} else if (params->base.dramtype == LPDDR3) {
+		if (params->base.odt == 1) {
+			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
+			drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
+			odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
+			if (drv_value == PHY_DRV_ODT_48) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x16;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x26;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x36;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else if (drv_value == PHY_DRV_ODT_40) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x19;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x23;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x31;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else if (drv_value == PHY_DRV_ODT_34_3) {
+				switch (odt_value) {
+				case PHY_DRV_ODT_240:
+					vref_value_dq = 0x17;
+					break;
+				case PHY_DRV_ODT_120:
+					vref_value_dq = 0x20;
+					break;
+				case PHY_DRV_ODT_60:
+					vref_value_dq = 0x2e;
+					break;
+				default:
+					debug("Invalid ODT value.\n");
+					return -EINVAL;
+				}
+			} else {
+				debug("Invalid DRV value.\n");
+				return -EINVAL;
+			}
+		} else {
+			vref_mode_dq = 0x2;  /* LPDDR3 */
+			vref_value_dq = 0x1f;
+		}
+		vref_mode_ac = 0x2;
+		vref_value_ac = 0x1f;
+	} else if (params->base.dramtype == DDR3) {
+		/* DDR3L */
+		vref_mode_dq = 0x1;
+		vref_value_dq = 0x1f;
+		vref_mode_ac = 0x1;
+		vref_value_ac = 0x1f;
+	} else {
+		debug("Unknown DRAM type.\n");
+		return -EINVAL;
+	}
+
+	reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
+
+	/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
+	clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
+	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
+	clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
+	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
+	clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
+	/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
+	clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
+
+	reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
+
+	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
+	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
+
+	if (params->base.dramtype == LPDDR4)
+		mode_sel = 0x6;
+	else if (params->base.dramtype == LPDDR3)
+		mode_sel = 0x0;
+	else if (params->base.dramtype == DDR3)
+		mode_sel = 0x1;
+	else
+		return -EINVAL;
+
+	/* PHY_924 PHY_PAD_FDBK_DRIVE */
+	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
+	/* PHY_926 PHY_PAD_DATA_DRIVE */
+	clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
+	/* PHY_927 PHY_PAD_DQS_DRIVE */
+	clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
+	/* PHY_928 PHY_PAD_ADDR_DRIVE */
+	clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
+	/* PHY_929 PHY_PAD_CLK_DRIVE */
+	clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
+	/* PHY_935 PHY_PAD_CKE_DRIVE */
+	clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
+	/* PHY_937 PHY_PAD_RST_DRIVE */
+	clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
+	/* PHY_939 PHY_PAD_CS_DRIVE */
+	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
+
+	/* speed setting */
+	if (params->base.ddr_freq < 400)
+		speed = 0x0;
+	else if (params->base.ddr_freq < 800)
+		speed = 0x1;
+	else if (params->base.ddr_freq < 1200)
+		speed = 0x2;
+	else
+		speed = 0x3;
+
+	/* PHY_924 PHY_PAD_FDBK_DRIVE */
+	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+	/* PHY_926 PHY_PAD_DATA_DRIVE */
+	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+	/* PHY_927 PHY_PAD_DQS_DRIVE */
+	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+	/* PHY_928 PHY_PAD_ADDR_DRIVE */
+	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+	/* PHY_929 PHY_PAD_CLK_DRIVE */
+	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+	/* PHY_935 PHY_PAD_CKE_DRIVE */
+	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+	/* PHY_937 PHY_PAD_RST_DRIVE */
+	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+	/* PHY_939 PHY_PAD_CS_DRIVE */
+	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+	return 0;
+}
+
  static void set_ds_odt(const struct chan_info *chan,
  		       const struct rk3399_sdram_params *params)
  {

@@ -332,6 +492,8 @@ static void set_ds_odt(const struct chan_info *chan,
 
  	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
  	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
+
+	phy_io_config(chan, params);
  }
 
  static void pctl_start(struct dram_info *dram, u8 channel)

@@ -376,166 +538,6 @@ static void pctl_start(struct dram_info *dram, u8 channel)
  			dram->pwrup_srefresh_exit[channel]);
  }
 
-static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *params)
-{
-	u32 *denali_phy = chan->publ->denali_phy;
-	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
-	u32 mode_sel;
-	u32 reg_value;
-	u32 drv_value, odt_value;
-	u32 speed;
-
-	/* vref setting */
-	if (params->base.dramtype == LPDDR4) {
-		/* LPDDR4 */
-		vref_mode_dq = 0x6;
-		vref_value_dq = 0x1f;
-		vref_mode_ac = 0x6;
-		vref_value_ac = 0x1f;
-	} else if (params->base.dramtype == LPDDR3) {
-		if (params->base.odt == 1) {
-			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
-			drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
-			odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
-			if (drv_value == PHY_DRV_ODT_48) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x16;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x26;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x36;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else if (drv_value == PHY_DRV_ODT_40) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x19;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x23;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x31;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else if (drv_value == PHY_DRV_ODT_34_3) {
-				switch (odt_value) {
-				case PHY_DRV_ODT_240:
-					vref_value_dq = 0x17;
-					break;
-				case PHY_DRV_ODT_120:
-					vref_value_dq = 0x20;
-					break;
-				case PHY_DRV_ODT_60:
-					vref_value_dq = 0x2e;
-					break;
-				default:
-					debug("Invalid ODT value.\n");
-					return -EINVAL;
-				}
-			} else {
-				debug("Invalid DRV value.\n");
-				return -EINVAL;
-			}
-		} else {
-			vref_mode_dq = 0x2;  /* LPDDR3 */
-			vref_value_dq = 0x1f;
-		}
-		vref_mode_ac = 0x2;
-		vref_value_ac = 0x1f;
-	} else if (params->base.dramtype == DDR3) {
-		/* DDR3L */
-		vref_mode_dq = 0x1;
-		vref_value_dq = 0x1f;
-		vref_mode_ac = 0x1;
-		vref_value_ac = 0x1f;
-	} else {
-		debug("Unknown DRAM type.\n");
-		return -EINVAL;
-	}
-
-	reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
-
-	/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
-	clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
-	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
-	clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
-	/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
-	clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
-	/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
-	clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
-
-	reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
-
-	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
-	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
-
-	if (params->base.dramtype == LPDDR4)
-		mode_sel = 0x6;
-	else if (params->base.dramtype == LPDDR3)
-		mode_sel = 0x0;
-	else if (params->base.dramtype == DDR3)
-		mode_sel = 0x1;
-	else
-		return -EINVAL;
-
-	/* PHY_924 PHY_PAD_FDBK_DRIVE */
-	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
-	/* PHY_926 PHY_PAD_DATA_DRIVE */
-	clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
-	/* PHY_927 PHY_PAD_DQS_DRIVE */
-	clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
-	/* PHY_928 PHY_PAD_ADDR_DRIVE */
-	clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
-	/* PHY_929 PHY_PAD_CLK_DRIVE */
-	clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
-	/* PHY_935 PHY_PAD_CKE_DRIVE */
-	clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
-	/* PHY_937 PHY_PAD_RST_DRIVE */
-	clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
-	/* PHY_939 PHY_PAD_CS_DRIVE */
-	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
-
-	/* speed setting */
-	if (params->base.ddr_freq < 400)
-		speed = 0x0;
-	else if (params->base.ddr_freq < 800)
-		speed = 0x1;
-	else if (params->base.ddr_freq < 1200)
-		speed = 0x2;
-	else
-		speed = 0x3;
-
-	/* PHY_924 PHY_PAD_FDBK_DRIVE */
-	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
-	/* PHY_926 PHY_PAD_DATA_DRIVE */
-	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
-	/* PHY_927 PHY_PAD_DQS_DRIVE */
-	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
-	/* PHY_928 PHY_PAD_ADDR_DRIVE */
-	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
-	/* PHY_929 PHY_PAD_CLK_DRIVE */
-	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
-	/* PHY_935 PHY_PAD_CKE_DRIVE */
-	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
-	/* PHY_937 PHY_PAD_RST_DRIVE */
-	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
-	/* PHY_939 PHY_PAD_CS_DRIVE */
-	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
-
-	return 0;
-}
-
  static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  		    u32 channel, const struct rk3399_sdram_params *params)
  {

@@ -545,7 +547,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	const u32 *params_ctl = params->pctl_regs.denali_ctl;
  	const u32 *params_phy = params->phy_regs.denali_phy;
  	u32 tmp, tmp1, tmp2;
-	int ret;
 
  	/*
  	 * work around controller bug:

drivers/ram/rockchip/sdram_rk3399.c static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, · line 629

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +0 -4
@@ -623,10 +624,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
  	clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 
-	ret = phy_io_config(chan, params);
-	if (ret)
-		return ret;
-
  	return 0;
  }

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#52 lore raw

PATCH v3 20/57 ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry

In reply to a message not in the archive

Supporting LPDDR4 code support in RK3399 would increases the size of SPL/TPL.

So add kconfig entry for RK3399 LPDDR4 code so-that the boards have LPDDR4 can enable them via defconfig.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/Kconfig | 7 +++++++
 1 file changed, 7 insertions(+)
drivers/ram/rockchip/Kconfig +7 -0
index 151ffb684d..4f274e01b3 100644
@@ -23,4 +23,11 @@ config RAM_RK3399
 	  This enables ram drivers support for the platforms based on
 	  Rockchip RK3399 SoC.
 
+config RAM_RK3399_LPDDR4
+	bool "LPDDR4 support for Rockchip RK3399"
+	depends on RAM_RK3399
+	help
+	  This enables LPDDR4 sdram code support for the platforms based
+	  on Rockchip RK3399 SoC.
+
 endif # RAM_ROCKCHIP
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Reviewed-by
#54 lore raw

Re: [PATCH v3 20/57] ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry

Quoted 7 lines · Jagan Teki

Supporting LPDDR4 code support in RK3399 would increases the size of SPL/TPL.

So add kconfig entry for RK3399 LPDDR4 code so-that the boards have LPDDR4 can enable them via defconfig.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 10 lines
---
  drivers/ram/rockchip/Kconfig | 7 +++++++
  1 file changed, 7 insertions(+)
drivers/ram/rockchip/Kconfig +0 -0
index 151ffb684d..4f274e01b3 100644
@@ -23,4 +23,11 @@ config RAM_RK3399
  	  This enables ram drivers support for the platforms based on

drivers/ram/rockchip/Kconfig config RAM_RK3399 · line 33

Quoted 10 lines
drivers/ram/rockchip/Kconfig +7 -0
  	  Rockchip RK3399 SoC.
 
+config RAM_RK3399_LPDDR4
+	bool "LPDDR4 support for Rockchip RK3399"
+	depends on RAM_RK3399
+	help
+	  This enables LPDDR4 sdram code support for the platforms based
+	  on Rockchip RK3399 SoC.
+
  endif # RAM_ROCKCHIP

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#55 lore raw

PATCH v3 21/57 ram: rk3399: Add lpddr4 rank mask for ca training

In reply to a message not in the archive

Add rank_mask based on the rank number for lpddr4.

This would keep the ca data training loop based on the desired rank mask value instead of looping for all values.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +4 -1
index a49677285d..8ecc3a1b74 100644
@@ -687,7 +687,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
 	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 	writel(0x00003f7c, (&denali_pi[175]));
 
-	rank_mask = (rank == 1) ? 0x1 : 0x3;
+	if (params->base.dramtype == LPDDR4)
+		rank_mask = (rank == 1) ? 0x5 : 0xf;
+	else
+		rank_mask = (rank == 1) ? 0x1 : 0x3;
 
 	for (i = 0; i < 4; i++) {
 		if (!(rank_mask & (1 << i)))
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Reviewed-by
#57 lore raw

Re: [PATCH v3 21/57] ram: rk3399: Add lpddr4 rank mask for ca training

Quoted 7 lines · Jagan Teki

Add rank_mask based on the rank number for lpddr4.

This would keep the ca data training loop based on the desired rank mask value instead of looping for all values.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 10 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index a49677285d..8ecc3a1b74 100644
@@ -687,7 +687,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
  	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */

drivers/ram/rockchip/sdram_rk3399.c static int data_training_ca(const struct chan_info *chan, u32 channel, · line 696

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +4 -1
  	writel(0x00003f7c, (&denali_pi[175]));
 
-	rank_mask = (rank == 1) ? 0x1 : 0x3;
+	if (params->base.dramtype == LPDDR4)
+		rank_mask = (rank == 1) ? 0x5 : 0xf;
+	else
+		rank_mask = (rank == 1) ? 0x1 : 0x3;
 
  	for (i = 0; i < 4; i++) {
  		if (!(rank_mask & (1 << i)))

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#58 lore raw

PATCH v3 22/57 ram: rk3399: Add lpddr4 rank mask for wdql training

In reply to a message not in the archive

Add rank_mask based on the rank number for lpddr4.

This would keep the wdql data training loop based on the desired rank mask value instead of looping for all values.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +4 -1
index 8ecc3a1b74..711477188e 100644
@@ -925,7 +925,10 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
 	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
 	writel(0x00003f7c, (&denali_pi[175]));
 
-	rank_mask = (rank == 1) ? 0x1 : 0x3;
+	if (params->base.dramtype == LPDDR4)
+		rank_mask = (rank == 1) ? 0x5 : 0xf;
+	else
+		rank_mask = (rank == 1) ? 0x1 : 0x3;
 
 	for (i = 0; i < 4; i++) {
 		if (!(rank_mask & (1 << i)))
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Reviewed-by
#60 lore raw

Re: [PATCH v3 22/57] ram: rk3399: Add lpddr4 rank mask for wdql training

Quoted 7 lines · Jagan Teki

Add rank_mask based on the rank number for lpddr4.

This would keep the wdql data training loop based on the desired rank mask value instead of looping for all values.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 10 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 8ecc3a1b74..711477188e 100644
@@ -925,7 +925,10 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
  	/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */

drivers/ram/rockchip/sdram_rk3399.c static int data_training_wdql(const struct chan_info *chan, u32 channel, · line 934

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +4 -1
  	writel(0x00003f7c, (&denali_pi[175]));
 
-	rank_mask = (rank == 1) ? 0x1 : 0x3;
+	if (params->base.dramtype == LPDDR4)
+		rank_mask = (rank == 1) ? 0x5 : 0xf;
+	else
+		rank_mask = (rank == 1) ? 0x1 : 0x3;
 
  	for (i = 0; i < 4; i++) {
  		if (!(rank_mask & (1 << i)))

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#61 lore raw

PATCH v3 23/57 ram: rk3399: Move mode_sel assignment

In reply to a message not in the archive

mode_sel assignment is based on dram type.

In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area.

No functionality change.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/sdram_rk3399.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +3 -9
index 711477188e..88fbfa440d 100644
@@ -205,6 +205,7 @@ static int phy_io_config(const struct chan_info *chan,
 		vref_value_dq = 0x1f;
 		vref_mode_ac = 0x6;
 		vref_value_ac = 0x1f;
+		mode_sel = 0x6;
 	} else if (params->base.dramtype == LPDDR3) {
 		if (params->base.odt == 1) {
 			vref_mode_dq = 0x5;  /* LPDDR3 ODT */

@@ -265,12 +266,14 @@ static int phy_io_config(const struct chan_info *chan,
 		}
 		vref_mode_ac = 0x2;
 		vref_value_ac = 0x1f;
+		mode_sel = 0x0;
 	} else if (params->base.dramtype == DDR3) {
 		/* DDR3L */
 		vref_mode_dq = 0x1;
 		vref_value_dq = 0x1f;
 		vref_mode_ac = 0x1;
 		vref_value_ac = 0x1f;
+		mode_sel = 0x1;
 	} else {
 		debug("Unknown DRAM type.\n");
 		return -EINVAL;

@@ -292,15 +295,6 @@ static int phy_io_config(const struct chan_info *chan,
 	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
 	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 
-	if (params->base.dramtype == LPDDR4)
-		mode_sel = 0x6;
-	else if (params->base.dramtype == LPDDR3)
-		mode_sel = 0x0;
-	else if (params->base.dramtype == DDR3)
-		mode_sel = 0x1;
-	else
-		return -EINVAL;
-
 	/* PHY_924 PHY_PAD_FDBK_DRIVE */
 	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
 	/* PHY_926 PHY_PAD_DATA_DRIVE */
Signature · 1 line
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Reviewed-by
#63 lore raw

Re: [PATCH v3 23/57] ram: rk3399: Move mode_sel assignment

Quoted 9 lines · Jagan Teki

mode_sel assignment is based on dram type.

In phy_io_config, already have vref setting based on the dram type, so move this mode_sel assignment on vref setting area.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 37 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 12 +++---------
  1 file changed, 3 insertions(+), 9 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +3 -2
index 711477188e..88fbfa440d 100644
@@ -205,6 +205,7 @@ static int phy_io_config(const struct chan_info *chan,
  		vref_value_dq = 0x1f;
  		vref_mode_ac = 0x6;
  		vref_value_ac = 0x1f;
+		mode_sel = 0x6;
  	} else if (params->base.dramtype == LPDDR3) {
  		if (params->base.odt == 1) {
  			vref_mode_dq = 0x5;  /* LPDDR3 ODT */

@@ -265,12 +266,14 @@ static int phy_io_config(const struct chan_info *chan,
  		}
  		vref_mode_ac = 0x2;
  		vref_value_ac = 0x1f;
+		mode_sel = 0x0;
  	} else if (params->base.dramtype == DDR3) {
  		/* DDR3L */
  		vref_mode_dq = 0x1;
  		vref_value_dq = 0x1f;
  		vref_mode_ac = 0x1;
  		vref_value_ac = 0x1f;
+		mode_sel = 0x1;
  	} else {
  		debug("Unknown DRAM type.\n");
  		return -EINVAL;

@@ -292,15 +295,6 @@ static int phy_io_config(const struct chan_info *chan,
  	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
  	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 
-	if (params->base.dramtype == LPDDR4)
-		mode_sel = 0x6;

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 300

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +0 -7
-	else if (params->base.dramtype == LPDDR3)
-		mode_sel = 0x0;
-	else if (params->base.dramtype == DDR3)
-		mode_sel = 0x1;
-	else
-		return -EINVAL;
-
  	/* PHY_924 PHY_PAD_FDBK_DRIVE */
  	clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
  	/* PHY_926 PHY_PAD_DATA_DRIVE */

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#64 lore raw

PATCH v3 24/57 ram: rk3399: Don't wait for PLL lock in lpddr4

In reply to a message not in the archive

lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations.

So no need to wait explicitly during pctl config.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +16 -10
index 88fbfa440d..023838a301 100644
@@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	setbits_le32(&denali_pi[0], START);
 	setbits_le32(&denali_ctl[0], START);
 
-	/* Waiting for phy DLL lock */
-	while (1) {
-		tmp = readl(&denali_phy[920]);
-		tmp1 = readl(&denali_phy[921]);
-		tmp2 = readl(&denali_phy[922]);
-		if ((((tmp >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 0) & 0x1) == 0x1) &&
-		    (((tmp2 >> 0) & 0x1) == 0x1))
-			break;
+	/**
+	 * LPDDR4 use PLL bypass mode for init
+	 * not need to wait for the PLL to lock
+	 */
+	if (params->base.dramtype != LPDDR4) {
+		/* Waiting for phy DLL lock */
+		while (1) {
+			tmp = readl(&denali_phy[920]);
+			tmp1 = readl(&denali_phy[921]);
+			tmp2 = readl(&denali_phy[922]);
+			if ((((tmp >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 0) & 0x1) == 0x1) &&
+			    (((tmp2 >> 0) & 0x1) == 0x1))
+				break;
+		}
 	}
 
 	copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);
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Reviewed-by
#66 lore raw

Re: [PATCH v3 24/57] ram: rk3399: Don't wait for PLL lock in lpddr4

Quoted 7 lines · Jagan Teki

lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations.

So no need to wait explicitly during pctl config.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 31 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------
  1 file changed, 16 insertions(+), 10 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +9 -10
index 88fbfa440d..023838a301 100644
@@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	setbits_le32(&denali_pi[0], START);
  	setbits_le32(&denali_ctl[0], START);
 
-	/* Waiting for phy DLL lock */
-	while (1) {
-		tmp = readl(&denali_phy[920]);
-		tmp1 = readl(&denali_phy[921]);
-		tmp2 = readl(&denali_phy[922]);
-		if ((((tmp >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 16) & 0x1) == 0x1) &&
-		    (((tmp1 >> 0) & 0x1) == 0x1) &&
-		    (((tmp2 >> 0) & 0x1) == 0x1))
-			break;
+	/**
+	 * LPDDR4 use PLL bypass mode for init
+	 * not need to wait for the PLL to lock
+	 */
+	if (params->base.dramtype != LPDDR4) {
+		/* Waiting for phy DLL lock */
+		while (1) {
+			tmp = readl(&denali_phy[920]);
+			tmp1 = readl(&denali_phy[921]);

drivers/ram/rockchip/sdram_rk3399.c static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, · line 591

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+			tmp2 = readl(&denali_phy[922]);
+			if ((((tmp >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 16) & 0x1) == 0x1) &&
+			    (((tmp1 >> 0) & 0x1) == 0x1) &&
+			    (((tmp2 >> 0) & 0x1) == 0x1))
+				break;
+		}
  	}
 
  	copy_to_reg(&denali_phy[896], &params_phy[896], (958 - 895) * 4);

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#67 lore raw

PATCH v3 25/57 ram: rk3399: Avoid two channel ZQ Cal Start at the same time

In reply to a message not in the archive

It is possible in lpddr4 dram, where both the channels would start at same time with ZQ Cal Start. If it uses ZQ Call start then it will use RZQ.

For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe connect to both channel. If ZQ Cal Start at the same time, it will use the same RZQ.

It is not a problem of using RZQ in both the channels, but can not use at the same time.

So, to avoid this, we have an option of dram tINIT3 value for increasing the frequency for channel 1.

This patch increase the available tINIT3 with existing running dram frequency.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +14 -0
index 023838a301..beb4f6de54 100644
@@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 		    sizeof(struct rk3399_ddr_pctl_regs) - 4);
 	writel(params_ctl[0], &denali_ctl[0]);
 
+	/*
+	 * two channel init at the same time, then ZQ Cal Start
+	 * at the same time, it will use the same RZQ, but cannot
+	 * start at the same time.
+	 *
+	 * So, increase tINIT3 for channel 1, will avoid two
+	 * channel ZQ Cal Start at the same time
+	 */
+	if (params->base.dramtype == LPDDR4 && channel == 1) {
+		tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
+		tmp1 = readl(&denali_ctl[14]);
+		writel(tmp + tmp1, &denali_ctl[14]);
+	}
+
 	copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
 		    sizeof(struct rk3399_ddr_pi_regs));
Signature · 1 line
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Reviewed-by
#69 lore raw

Re: [PATCH v3 25/57] ram: rk3399: Avoid two channel ZQ Cal Start at the same time

Quoted 11 lines · Jagan Teki

It is possible in lpddr4 dram, where both the channels would start at same time with ZQ Cal Start. If it uses ZQ Call start then it will use RZQ.

For example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe connect to both channel. If ZQ Cal Start at the same time, it will use the same RZQ.

It is not a problem of using RZQ in both the channels, but can not use at the same time.

Quoted 8 lines

So, to avoid this, we have an option of dram tINIT3 value for increasing the frequency for channel 1.

This patch increase the available tINIT3 with existing running dram frequency.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 19 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++
  1 file changed, 14 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +7 -0
index 023838a301..beb4f6de54 100644
@@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  		    sizeof(struct rk3399_ddr_pctl_regs) - 4);
  	writel(params_ctl[0], &denali_ctl[0]);
 
+	/*
+	 * two channel init at the same time, then ZQ Cal Start
+	 * at the same time, it will use the same RZQ, but cannot
+	 * start at the same time.
+	 *
+	 * So, increase tINIT3 for channel 1, will avoid two
+	 * channel ZQ Cal Start at the same time

drivers/ram/rockchip/sdram_rk3399.c static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, · line 569

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+	 */
+	if (params->base.dramtype == LPDDR4 && channel == 1) {
+		tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
+		tmp1 = readl(&denali_ctl[14]);
+		writel(tmp + tmp1, &denali_ctl[14]);
+	}
+
  	copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
  		    sizeof(struct rk3399_ddr_pi_regs));

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#70 lore raw

PATCH v3 26/57 ram: rk3399: Configure PHY_898, PHY_919 for lpddr4

In reply to a message not in the archive

PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4.

So, configure the same in pctl_cfg for LPDDR4.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 5 +++++
 1 file changed, 5 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +5 -0
index beb4f6de54..7625506458 100644
@@ -574,6 +574,11 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
 	writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
+		writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
+	}
+
 	dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
 					     PWRUP_SREFRESH_EXIT;
 	clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
Signature · 1 line
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Reviewed-by
#72 lore raw

Re: [PATCH v3 26/57] ram: rk3399: Configure PHY_898, PHY_919 for lpddr4

Quoted 7 lines · Jagan Teki

PHY_898, PHY_919 would require to configure PHY LP4 boot pll control and ca for lpddr4.

So, configure the same in pctl_cfg for LPDDR4.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 10 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 5 +++++
  1 file changed, 5 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index beb4f6de54..7625506458 100644
@@ -574,6 +574,11 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	writel(params->phy_regs.denali_phy[911], &denali_phy[911]);

drivers/ram/rockchip/sdram_rk3399.c static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, · line 584

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +5 -0
  	writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
+		writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
+	}
+
  	dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
  					     PWRUP_SREFRESH_EXIT;
  	clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

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#73 lore raw

PATCH v3 27/57 ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4

In reply to a message not in the archive

Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +24 -0
index 7625506458..a9e092c39f 100644
@@ -35,6 +35,9 @@
 #define PHY_DRV_ODT_40		0xe
 #define PHY_DRV_ODT_34_3	0xf
 
+#define PHY_BOOSTP_EN		0x1
+#define PHY_BOOSTN_EN		0x1
+
 #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
 					((n) << (8 + (ch) * 4)))
 #define CRU_SFTRST_DDR_PHY(ch, n)	((0x1 << (9 + 16 + (ch) * 4)) | \

@@ -312,6 +315,27 @@ static int phy_io_config(const struct chan_info *chan,
 	/* PHY_939 PHY_PAD_CS_DRIVE */
 	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* BOOSTP_EN & BOOSTN_EN */
+		reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
+		/* PHY_925 PHY_PAD_FDBK_DRIVE2 */
+		clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */
+		clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+	}
+
 	/* speed setting */
 	if (params->base.ddr_freq < 400)
 		speed = 0x0;
Signature · 1 line
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Reviewed-by
#75 lore raw

Re: [PATCH v3 27/57] ram: rk3399: Configure BOOSTP_EN, BOOSTN_EN for lpddr4

Quoted 4 lines · Jagan Teki

Configure BOOSTP_EN, BOOSTN_EN for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 36 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 24 ++++++++++++++++++++++++
  1 file changed, 24 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +17 -0
index 7625506458..a9e092c39f 100644
@@ -35,6 +35,9 @@
  #define PHY_DRV_ODT_40		0xe
  #define PHY_DRV_ODT_34_3	0xf
 
+#define PHY_BOOSTP_EN		0x1
+#define PHY_BOOSTN_EN		0x1
+
  #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
  					((n) << (8 + (ch) * 4)))
  #define CRU_SFTRST_DDR_PHY(ch, n)	((0x1 << (9 + 16 + (ch) * 4)) | \

@@ -312,6 +315,27 @@ static int phy_io_config(const struct chan_info *chan,
  	/* PHY_939 PHY_PAD_CS_DRIVE */
  	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* BOOSTP_EN & BOOSTN_EN */
+		reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
+		/* PHY_925 PHY_PAD_FDBK_DRIVE2 */
+		clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 341

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+	}
+
  	/* speed setting */
  	if (params->base.ddr_freq < 400)
  		speed = 0x0;

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#76 lore raw

PATCH v3 28/57 ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4

In reply to a message not in the archive

Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +21 -0
index a9e092c39f..c02f936f2a 100644
@@ -37,6 +37,8 @@
 
 #define PHY_BOOSTP_EN		0x1
 #define PHY_BOOSTN_EN		0x1
+#define PHY_SLEWP_EN		0x1
+#define PHY_SLEWN_EN		0x1
 
 #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
 					((n) << (8 + (ch) * 4)))

@@ -334,6 +336,25 @@ static int phy_io_config(const struct chan_info *chan,
 		clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
 		/* PHY_939 PHY_PAD_CS_DRIVE */
 		clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+
+		/* SLEWP_EN & SLEWN_EN */
+		reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
+		/* PHY_924 PHY_PAD_FDBK_DRIVE */
+		clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */
+		clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
 	}
 
 	/* speed setting */
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-29-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#78 lore raw

Re: [PATCH v3 28/57] ram: rk3399: Configure SLEWP_EN, SLEWN_EN for lpddr4

Quoted 4 lines · Jagan Teki

Configure SLEWP_EN, SLEWN_EN for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 33 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 21 +++++++++++++++++++++
  1 file changed, 21 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +14 -0
index a9e092c39f..c02f936f2a 100644
@@ -37,6 +37,8 @@
 
  #define PHY_BOOSTP_EN		0x1
  #define PHY_BOOSTN_EN		0x1
+#define PHY_SLEWP_EN		0x1
+#define PHY_SLEWN_EN		0x1
 
  #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
  					((n) << (8 + (ch) * 4)))

@@ -334,6 +336,25 @@ static int phy_io_config(const struct chan_info *chan,
  		clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
  		/* PHY_939 PHY_PAD_CS_DRIVE */
  		clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
+
+		/* SLEWP_EN & SLEWN_EN */
+		reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
+		/* PHY_924 PHY_PAD_FDBK_DRIVE */
+		clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 360

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */
+		clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
  	}
 
  	/* speed setting */

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#79 lore raw

PATCH v3 29/57 ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4

In reply to a message not in the archive

Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +22 -0
index c02f936f2a..2ab10da53f 100644
@@ -39,6 +39,7 @@
 #define PHY_BOOSTN_EN		0x1
 #define PHY_SLEWP_EN		0x1
 #define PHY_SLEWN_EN		0x1
+#define PHY_RX_CM_INPUT		0x1
 
 #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
 					((n) << (8 + (ch) * 4)))

@@ -384,6 +385,27 @@ static int phy_io_config(const struct chan_info *chan,
 	/* PHY_939 PHY_PAD_CS_DRIVE */
 	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* RX_CM_INPUT */
+		reg_value = PHY_RX_CM_INPUT;
+		/* PHY_924 PHY_PAD_FDBK_DRIVE */
+		clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */
+		clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
+	}
+
 	return 0;
 }
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Reviewed-by
#81 lore raw

Re: [PATCH v3 29/57] ram: rk3399: Configure PHY RX_CM_INPUT for lpddr4

Quoted 4 lines · Jagan Teki

Configure PHY RX_CM_INPUT for lpddr4 during phy IO config.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 34 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 22 ++++++++++++++++++++++
  1 file changed, 22 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +15 -0
index c02f936f2a..2ab10da53f 100644
@@ -39,6 +39,7 @@
  #define PHY_BOOSTN_EN		0x1
  #define PHY_SLEWP_EN		0x1
  #define PHY_SLEWN_EN		0x1
+#define PHY_RX_CM_INPUT		0x1
 
  #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
  					((n) << (8 + (ch) * 4)))

@@ -384,6 +385,27 @@ static int phy_io_config(const struct chan_info *chan,
  	/* PHY_939 PHY_PAD_CS_DRIVE */
  	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
 
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* RX_CM_INPUT */
+		reg_value = PHY_RX_CM_INPUT;
+		/* PHY_924 PHY_PAD_FDBK_DRIVE */
+		clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
+		/* PHY_926 PHY_PAD_DATA_DRIVE */
+		clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
+		/* PHY_927 PHY_PAD_DQS_DRIVE */
+		clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
+		/* PHY_928 PHY_PAD_ADDR_DRIVE */
+		clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
+		/* PHY_929 PHY_PAD_CLK_DRIVE */
+		clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
+		/* PHY_935 PHY_PAD_CKE_DRIVE */

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 411

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
+		/* PHY_937 PHY_PAD_RST_DRIVE */
+		clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
+		/* PHY_939 PHY_PAD_CS_DRIVE */
+		clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
+	}
+
  	return 0;
  }

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#82 lore raw

PATCH v3 30/57 ram: rk3399: Map chipselect for lpddr4

In reply to a message not in the archive

Assign desired cs_map values for lpddr4 during set memory map.

Initial cs_map values is based on the sdram parameters, so the same will adjusted based dramtype as LPDDR4.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 10 ++++++++++
 1 file changed, 10 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +10 -0
index 2ab10da53f..7689711a99 100644
@@ -188,6 +188,16 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
 	clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
 			((3 - sdram_ch->cap_info.bk) << 16) |
 			((16 - row) << 24));
+
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		if (cs_map == 1)
+			cs_map = 0x5;
+		else if (cs_map == 2)
+			cs_map = 0xa;
+		else
+			cs_map = 0xF;
+	}
+
 	/* PI_41 PI_CS_MAP:RW:24:4 */
 	clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
 	if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
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Reviewed-by
#84 lore raw

Re: [PATCH v3 30/57] ram: rk3399: Map chipselect for lpddr4

Quoted 7 lines · Jagan Teki

Assign desired cs_map values for lpddr4 during set memory map.

Initial cs_map values is based on the sdram parameters, so the same will adjusted based dramtype as LPDDR4.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 15 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 10 ++++++++++
  1 file changed, 10 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +3 -0
index 2ab10da53f..7689711a99 100644
@@ -188,6 +188,16 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  	clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
  			((3 - sdram_ch->cap_info.bk) << 16) |
  			((16 - row) << 24));
+
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		if (cs_map == 1)

drivers/ram/rockchip/sdram_rk3399.c static void set_memory_map(const struct chan_info *chan, u32 channel, · line 203

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+			cs_map = 0x5;
+		else if (cs_map == 2)
+			cs_map = 0xa;
+		else
+			cs_map = 0xF;
+	}
+
  	/* PI_41 PI_CS_MAP:RW:24:4 */
  	clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
  	if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)

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#85 lore raw

PATCH v3 31/57 ram: rk3399: Configure tsel write ca for lpddr4

In reply to a message not in the archive

tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt.

Configure the same PHY register for lpddr4 would require a mask value of (300 << 8).

Add support for it.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +12 -3
index 7689711a99..1050cbdb07 100644
@@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan,
 
 	/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
 	reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
-	clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* LPDDR4 these register read always return 0, so
+		 * can not use clrsetbits_le32(), need to write32
+		 */
+		writel((0x300 << 8) | reg_value, &denali_phy[544]);
+		writel((0x300 << 8) | reg_value, &denali_phy[672]);
+		writel((0x300 << 8) | reg_value, &denali_phy[800]);
+	} else {
+		clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	}
 
 	/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
 	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
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Reviewed-by
#87 lore raw

Re: [PATCH v3 31/57] ram: rk3399: Configure tsel write ca for lpddr4

Quoted 10 lines · Jagan Teki

tsel write ca_p and ca_n values need to write on PHY 544, 672 and 800 to configure ds odt.

Configure the same PHY register for lpddr4 would require a mask value of (300 << 8).

Add support for it.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 20 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---
  1 file changed, 12 insertions(+), 3 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +5 -3
index 7689711a99..1050cbdb07 100644
@@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan,
 
  	/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
  	reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
-	clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
-	clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	if (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {
+		/* LPDDR4 these register read always return 0, so
+		 * can not use clrsetbits_le32(), need to write32
+		 */
+		writel((0x300 << 8) | reg_value, &denali_phy[544]);

drivers/ram/rockchip/sdram_rk3399.c static void set_ds_odt(const struct chan_info *chan, · line 519

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		writel((0x300 << 8) | reg_value, &denali_phy[672]);
+		writel((0x300 << 8) | reg_value, &denali_phy[800]);
+	} else {
+		clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
+		clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
+	}
 
  	/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
  	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);

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#88 lore raw

PATCH v3 32/57 ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1

In reply to a message not in the archive

The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

and usually dfi dram clk is configured via CLK1P/N, so disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4, with rank 1.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +12 -2
index 1050cbdb07..359ab0b826 100644
@@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram,
 		writel(noc_timing->ddrmode.d32,
 		       &ddr_msch_regs->ddrmode);
 
-		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
-		if (params->ch[channel].cap_info.rank == 1)
+		/**
+		 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+		 *
+		 * The hardware for LPDDR4 with
+		 * - CLK0P/N connect to lower 16-bits
+		 * - CLK1P/N connect to higher 16-bits
+		 *
+		 * dfi dram clk is configured via CLK1P/N, so disabling
+		 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+		 */
+		if (params->ch[channel].cap_info.rank == 1 &&
+		    params->base.dramtype != LPDDR4)
 			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
 				     1 << 17);
 	}
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Reviewed-by
#90 lore raw

Re: [PATCH v3 32/57] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1

Quoted 4 lines · Jagan Teki

The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits

Quoted 8 lines

and usually dfi dram clk is configured via CLK1P/N, so disabling dfi dram clk will disable the CLK1P/N as well.

So, add patch to not to disable dfi dram clk for lpddr4, with rank 1.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 19 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
  1 file changed, 12 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +5 -2
index 1050cbdb07..359ab0b826 100644
@@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram,
  		writel(noc_timing->ddrmode.d32,
  		       &ddr_msch_regs->ddrmode);
 
-		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
-		if (params->ch[channel].cap_info.rank == 1)
+		/**
+		 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+		 *
+		 * The hardware for LPDDR4 with
+		 * - CLK0P/N connect to lower 16-bits

drivers/ram/rockchip/sdram_rk3399.c static void dram_all_config(struct dram_info *dram, · line 1242

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		 * - CLK1P/N connect to higher 16-bits
+		 *
+		 * dfi dram clk is configured via CLK1P/N, so disabling
+		 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+		 */
+		if (params->ch[channel].cap_info.rank == 1 &&
+		    params->base.dramtype != LPDDR4)
  			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
  				     1 << 17);
  	}

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#91 lore raw

PATCH v3 33/57 ram: rk3399: Add IO settings

In reply to a message not in the archive

Add IO settings for dram ctl and phy.

IO settings are useful for configuring ctl, phy odt, vref, mr5, mode select and other needed input output operations for lpddr4 or any other dramtype sdram.

Right now, this patch added IO setting for all supported sdram frequencies.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++
 1 file changed, 104 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +104 -0
index 359ab0b826..95d9f3a88b 100644
@@ -80,6 +80,110 @@ struct rockchip_dmc_plat {
 	struct regmap *map;
 };
 
+struct io_setting {
+	u32 mhz;
+	u32 mr5;
+	/* dram side */
+	u32 dq_odt;
+	u32 ca_odt;
+	u32 pdds;
+	u32 dq_vref;
+	u32 ca_vref;
+	/* phy side */
+	u32 rd_odt;
+	u32 wr_dq_drv;
+	u32 wr_ca_drv;
+	u32 wr_ckcs_drv;
+	u32 rd_odt_en;
+	u32 rd_vref;
+} lpddr4_io_setting[] = {
+	{
+		50 * MHz,
+		0,
+		/* dram side */
+		0,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_40,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en;*/
+		41,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		600 * MHz,
+		0,
+		/* dram side */
+		1,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en; */
+		32,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		800 * MHz,
+		0,
+		/* dram side */
+		1,	/* dq_odt; */
+		0,	/* ca_odt; */
+		1,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_40,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		1,	/* rd_odt_en; */
+		17,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		933 * MHz,
+		0,
+		/* dram side */
+		3,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x59,	/* dq_vref; 32% */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en; */
+		32,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		1066 * MHz,
+		0,
+		/* dram side */
+		6,	/* dq_odt; */
+		0,	/* ca_odt; */
+		1,	/* pdds; */
+		0x10,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_40,	/* rd_odt; */
+		PHY_DRV_ODT_60,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		1,	/* rd_odt_en; */
+		17,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+};
+
 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 {
 	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;
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Reviewed-by
#93 lore raw

Re: [PATCH v3 33/57] ram: rk3399: Add IO settings

Quoted 11 lines · Jagan Teki

Add IO settings for dram ctl and phy.

IO settings are useful for configuring ctl, phy odt, vref, mr5, mode select and other needed input output operations for lpddr4 or any other dramtype sdram.

Right now, this patch added IO setting for all supported sdram frequencies.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 109 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++
  1 file changed, 104 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +97 -0
index 359ab0b826..95d9f3a88b 100644
@@ -80,6 +80,110 @@ struct rockchip_dmc_plat {
  	struct regmap *map;
  };
 
+struct io_setting {
+	u32 mhz;
+	u32 mr5;
+	/* dram side */
+	u32 dq_odt;
+	u32 ca_odt;
+	u32 pdds;
+	u32 dq_vref;
+	u32 ca_vref;
+	/* phy side */
+	u32 rd_odt;
+	u32 wr_dq_drv;
+	u32 wr_ca_drv;
+	u32 wr_ckcs_drv;
+	u32 rd_odt_en;
+	u32 rd_vref;
+} lpddr4_io_setting[] = {
+	{
+		50 * MHz,
+		0,
+		/* dram side */
+		0,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_40,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en;*/
+		41,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		600 * MHz,
+		0,
+		/* dram side */
+		1,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en; */
+		32,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		800 * MHz,
+		0,
+		/* dram side */
+		1,	/* dq_odt; */
+		0,	/* ca_odt; */
+		1,	/* pdds; */
+		0x72,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_40,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		1,	/* rd_odt_en; */
+		17,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		933 * MHz,
+		0,
+		/* dram side */
+		3,	/* dq_odt; */
+		0,	/* ca_odt; */
+		6,	/* pdds; */
+		0x59,	/* dq_vref; 32% */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_HI_Z,	/* rd_odt; */
+		PHY_DRV_ODT_48,	/* wr_dq_drv; */
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		0,	/* rd_odt_en; */
+		32,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+	{
+		1066 * MHz,
+		0,
+		/* dram side */
+		6,	/* dq_odt; */
+		0,	/* ca_odt; */
+		1,	/* pdds; */
+		0x10,	/* dq_vref; */
+		0x72,	/* ca_vref; */
+		/* phy side */
+		PHY_DRV_ODT_40,	/* rd_odt; */
+		PHY_DRV_ODT_60,	/* wr_dq_drv; */

drivers/ram/rockchip/sdram_rk3399.c struct rockchip_dmc_plat { · line 189

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+		PHY_DRV_ODT_40,	/* wr_ca_drv; */
+		PHY_DRV_ODT_40,	/* wr_ckcs_drv; */
+		1,	/* rd_odt_en; */
+		17,	/* rd_vref; (unit %, range 3.3% - 48.7%) */
+	},
+};
+
  static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  {
  	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

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#94 lore raw

PATCH v3 34/57 ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings

In reply to a message not in the archive

Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++-----
 1 file changed, 36 insertions(+), 6 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +36 -6
index 95d9f3a88b..1b8ce5160f 100644
@@ -184,6 +184,33 @@ struct io_setting {
 	},
 };
 
+/**
+ * phy = 0, PHY boot freq
+ * phy = 1, PHY index 0
+ * phy = 2, PHY index 1
+ */
+static struct io_setting *
+lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
+{
+	struct io_setting *io = NULL;
+	u32 n;
+
+	for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
+		io = &lpddr4_io_setting[n];
+
+		if (io->mr5 != 0) {
+			if (io->mhz >= params->base.ddr_freq &&
+			    io->mr5 == mr5)
+				break;
+		} else {
+			if (io->mhz >= params->base.ddr_freq)
+				break;
+		}
+	}
+
+	return io;
+}
+
 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 {
 	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

@@ -524,7 +551,7 @@ static int phy_io_config(const struct chan_info *chan,
 }
 
 static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *params)
+		       const struct rk3399_sdram_params *params, u32 mr5)
 {
 	u32 *denali_phy = chan->publ->denali_phy;
 

@@ -533,19 +560,22 @@ static void set_ds_odt(const struct chan_info *chan,
 	u32 tsel_idle_select_n, tsel_rd_select_n;
 	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+	struct io_setting *io = NULL;
 	u32 reg_value;
 
 	if (params->base.dramtype == LPDDR4) {
+		io = lpddr4_get_io_settings(params, mr5);
+
 		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_rd_select_n = io->rd_odt;
 
 		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
+		tsel_wr_select_dq_p = io->wr_dq_drv;
 		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 
-		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+		tsel_wr_select_ca_p = io->wr_ca_drv;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
 	} else if (params->base.dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;

@@ -723,7 +753,7 @@ static void pctl_start(struct dram_info *dram, u8 channel)
 }
 
 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
-		    u32 channel, const struct rk3399_sdram_params *params)
+		    u32 channel, struct rk3399_sdram_params *params)
 {
 	u32 *denali_ctl = chan->pctl->denali_ctl;
 	u32 *denali_pi = chan->pi->denali_pi;

@@ -805,7 +835,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, params);
+	set_ds_odt(chan, params, 0);
 
 	/*
 	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-35-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#96 lore raw

Re: [PATCH v3 34/57] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings

Quoted 6 lines · Jagan Teki

Now we have IO settings available for all supported sdram frequencies, so retrieve these IO settings and make used for LPDDR4 ds odt configuration.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 87 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++-----
  1 file changed, 36 insertions(+), 6 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +35 -5
index 95d9f3a88b..1b8ce5160f 100644
@@ -184,6 +184,33 @@ struct io_setting {
  	},
  };
 
+/**
+ * phy = 0, PHY boot freq
+ * phy = 1, PHY index 0
+ * phy = 2, PHY index 1
+ */
+static struct io_setting *
+lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
+{
+	struct io_setting *io = NULL;
+	u32 n;
+
+	for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
+		io = &lpddr4_io_setting[n];
+
+		if (io->mr5 != 0) {
+			if (io->mhz >= params->base.ddr_freq &&
+			    io->mr5 == mr5)
+				break;
+		} else {
+			if (io->mhz >= params->base.ddr_freq)
+				break;
+		}
+	}
+
+	return io;
+}
+
  static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  {
  	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

@@ -524,7 +551,7 @@ static int phy_io_config(const struct chan_info *chan,
  }
 
  static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *params)
+		       const struct rk3399_sdram_params *params, u32 mr5)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
 

@@ -533,19 +560,22 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 tsel_idle_select_n, tsel_rd_select_n;
  	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
  	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+	struct io_setting *io = NULL;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {
+		io = lpddr4_get_io_settings(params, mr5);
+
  		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_rd_select_n = io->rd_odt;
 
  		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
+		tsel_wr_select_dq_p = io->wr_dq_drv;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
 
-		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+		tsel_wr_select_ca_p = io->wr_ca_drv;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;

@@ -723,7 +753,7 @@ static void pctl_start(struct dram_info *dram, u8 channel)
  }
 
  static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
-		    u32 channel, const struct rk3399_sdram_params *params)
+		    u32 channel, struct rk3399_sdram_params *params)
  {
  	u32 *denali_ctl = chan->pctl->denali_ctl;
  	u32 *denali_pi = chan->pi->denali_pi;

drivers/ram/rockchip/sdram_rk3399.c static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan, · line 841

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -805,7 +835,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
  	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
  	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, params);
+	set_ds_odt(chan, params, 0);
 
  	/*
  	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#97 lore raw

PATCH v3 35/57 ram: rk3399: Add tsel control clock drive

In reply to a message not in the archive

tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings.

Add support for these control clock for all dramtype sdrams.

Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables.

tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +14 -2
index 1b8ce5160f..c38ea1d284 100644
@@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan,
 	u32 tsel_idle_select_n, tsel_rd_select_n;
 	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
 	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+	u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
 	struct io_setting *io = NULL;
 	u32 reg_value;
 

@@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
 		tsel_wr_select_ca_p = io->wr_ca_drv;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
+
+		tsel_ckcs_select_p = io->wr_ckcs_drv;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 	} else if (params->base.dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
 		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;

@@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
 		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
+
+		tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 	} else {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
 		tsel_rd_select_n = PHY_DRV_ODT_240;

@@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
 		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
 		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
+
+		tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 	}
 
 	if (params->base.odt == 1)

@@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan,
 	clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 
 	/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
-	clrsetbits_le32(&denali_phy[939], 0xff, reg_value);
+	clrsetbits_le32(&denali_phy[939], 0xff,
+			tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 
 	/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
-	clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
+	clrsetbits_le32(&denali_phy[929], 0xff,
+			tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 
 	/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
 	clrsetbits_le32(&denali_phy[924], 0xff,
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-36-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#99 lore raw

Re: [PATCH v3 35/57] ram: rk3399: Add tsel control clock drive

Quoted 9 lines · Jagan Teki

tsel contrl clock drives are required to configure PHY 929, 939 controls drive settings.

Add support for these control clock for all dramtype sdrams.

Thse control clock drives are configure via tsel_ckcs_select_p and tsel_ckcs_select_n variables.

Quoted 6 lines

tsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as tsel_ckcs_select_p is retrived from IO settings for lpddr4 and rest uses PHY_DRV_ODT_34_3.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 51 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++--
  1 file changed, 14 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +10 -1
index 1b8ce5160f..c38ea1d284 100644
@@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 tsel_idle_select_n, tsel_rd_select_n;
  	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
  	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
+	u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
  	struct io_setting *io = NULL;
  	u32 reg_value;
 

@@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_wr_select_ca_p = io->wr_ca_drv;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
+
+		tsel_ckcs_select_p = io->wr_ckcs_drv;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;

@@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
+
+		tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_rd_select_n = PHY_DRV_ODT_240;

@@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
+
+		tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
+		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  	}
 
  	if (params->base.odt == 1)

@@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan,
  	clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
 
  	/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
-	clrsetbits_le32(&denali_phy[939], 0xff, reg_value);

drivers/ram/rockchip/sdram_rk3399.c static void set_ds_odt(const struct chan_info *chan, · line 680

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +4 -1
+	clrsetbits_le32(&denali_phy[939], 0xff,
+			tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 
  	/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
-	clrsetbits_le32(&denali_phy[929], 0xff, reg_value);
+	clrsetbits_le32(&denali_phy[929], 0xff,
+			tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
 
  	/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
  	clrsetbits_le32(&denali_phy[924], 0xff,

_______________________________________________
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#100 lore raw

PATCH v3 36/57 ram: rk3399: Configure soc odt support

In reply to a message not in the archive

CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399.

These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +48 -1
index c38ea1d284..e0be9d2485 100644
@@ -40,6 +40,8 @@
 #define PHY_SLEWP_EN		0x1
 #define PHY_SLEWN_EN		0x1
 #define PHY_RX_CM_INPUT		0x1
+#define CS0_MR22_VAL		0
+#define CS1_MR22_VAL		3
 
 #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
 					((n) << (8 + (ch) * 4)))

@@ -554,7 +556,7 @@ static void set_ds_odt(const struct chan_info *chan,
 		       const struct rk3399_sdram_params *params, u32 mr5)
 {
 	u32 *denali_phy = chan->publ->denali_phy;
-
+	u32 *denali_ctl = chan->pctl->denali_ctl;
 	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 	u32 tsel_idle_select_p, tsel_rd_select_p;
 	u32 tsel_idle_select_n, tsel_rd_select_n;

@@ -562,6 +564,7 @@ static void set_ds_odt(const struct chan_info *chan,
 	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
 	u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
 	struct io_setting *io = NULL;
+	u32 soc_odt = 0;
 	u32 reg_value;
 
 	if (params->base.dramtype == LPDDR4) {

@@ -581,6 +584,35 @@ static void set_ds_odt(const struct chan_info *chan,
 
 		tsel_ckcs_select_p = io->wr_ckcs_drv;
 		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
+		switch (tsel_rd_select_n) {
+		case PHY_DRV_ODT_240:
+			soc_odt = 1;
+			break;
+		case PHY_DRV_ODT_120:
+			soc_odt = 2;
+			break;
+		case PHY_DRV_ODT_80:
+			soc_odt = 3;
+			break;
+		case PHY_DRV_ODT_60:
+			soc_odt = 4;
+			break;
+		case PHY_DRV_ODT_48:
+			soc_odt = 5;
+			break;
+		case PHY_DRV_ODT_40:
+			soc_odt = 6;
+			break;
+		case PHY_DRV_ODT_34_3:
+			soc_odt = 6;
+			printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
+			       __func__);
+			break;
+		case PHY_DRV_ODT_HI_Z:
+		default:
+			soc_odt = 0;
+			break;
+		}
 	} else if (params->base.dramtype == LPDDR3) {
 		tsel_rd_select_p = PHY_DRV_ODT_240;
 		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;

@@ -621,6 +653,21 @@ static void set_ds_odt(const struct chan_info *chan,
 	tsel_wr_en = 0;
 	tsel_idle_en = 0;
 
+	/* F0_0 */
+	clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
+			(soc_odt | (CS0_MR22_VAL << 3)) << 16);
+	/* F2_0, F1_0 */
+	clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
+			((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
+			(soc_odt | (CS0_MR22_VAL << 3)));
+	/* F0_1 */
+	clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
+			(soc_odt | (CS1_MR22_VAL << 3)) << 16);
+	/* F2_1, F1_1 */
+	clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
+			((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
+			(soc_odt | (CS1_MR22_VAL << 3)));
+
 	/*
 	 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
 	 * sets termination values for read/idle cycles and drive strength
Signature · 1 line
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Reviewed-by
#102 lore raw

Re: [PATCH v3 36/57] ram: rk3399: Configure soc odt support

Quoted 9 lines · Jagan Teki

CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399.

These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 82 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++-
  1 file changed, 48 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +41 -1
index c38ea1d284..e0be9d2485 100644
@@ -40,6 +40,8 @@
  #define PHY_SLEWP_EN		0x1
  #define PHY_SLEWN_EN		0x1
  #define PHY_RX_CM_INPUT		0x1
+#define CS0_MR22_VAL		0
+#define CS1_MR22_VAL		3
 
  #define CRU_SFTRST_DDR_CTRL(ch, n)	((0x1 << (8 + 16 + (ch) * 4)) | \
  					((n) << (8 + (ch) * 4)))

@@ -554,7 +556,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		       const struct rk3399_sdram_params *params, u32 mr5)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
-
+	u32 *denali_ctl = chan->pctl->denali_ctl;
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_rd_select_p;
  	u32 tsel_idle_select_n, tsel_rd_select_n;

@@ -562,6 +564,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
  	u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
  	struct io_setting *io = NULL;
+	u32 soc_odt = 0;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {

@@ -581,6 +584,35 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_ckcs_select_p = io->wr_ckcs_drv;
  		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
+		switch (tsel_rd_select_n) {
+		case PHY_DRV_ODT_240:
+			soc_odt = 1;
+			break;
+		case PHY_DRV_ODT_120:
+			soc_odt = 2;
+			break;
+		case PHY_DRV_ODT_80:
+			soc_odt = 3;
+			break;
+		case PHY_DRV_ODT_60:
+			soc_odt = 4;
+			break;
+		case PHY_DRV_ODT_48:
+			soc_odt = 5;
+			break;
+		case PHY_DRV_ODT_40:
+			soc_odt = 6;
+			break;
+		case PHY_DRV_ODT_34_3:
+			soc_odt = 6;
+			printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
+			       __func__);
+			break;
+		case PHY_DRV_ODT_HI_Z:
+		default:
+			soc_odt = 0;
+			break;
+		}
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;

@@ -621,6 +653,21 @@ static void set_ds_odt(const struct chan_info *chan,
  	tsel_wr_en = 0;
  	tsel_idle_en = 0;
 
+	/* F0_0 */
+	clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
+			(soc_odt | (CS0_MR22_VAL << 3)) << 16);
+	/* F2_0, F1_0 */
+	clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
+			((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
+			(soc_odt | (CS0_MR22_VAL << 3)));
+	/* F0_1 */

drivers/ram/rockchip/sdram_rk3399.c static void set_ds_odt(const struct chan_info *chan, · line 673

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +7 -0
+	clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
+			(soc_odt | (CS1_MR22_VAL << 3)) << 16);
+	/* F2_1, F1_1 */
+	clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
+			((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
+			(soc_odt | (CS1_MR22_VAL << 3)));
+
  	/*
  	 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
  	 * sets termination values for read/idle cycles and drive strength

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#103 lore raw

PATCH v3 37/57 ram: rk3399: Get lpddr4 tsel_rd_en from io settings

In reply to a message not in the archive

For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en.

Add support for it.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +6 -2
index e0be9d2485..9e40880835 100644
@@ -645,10 +645,14 @@ static void set_ds_odt(const struct chan_info *chan,
 		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
 	}
 
-	if (params->base.odt == 1)
+	if (params->base.odt == 1) {
 		tsel_rd_en = 1;
-	else
+
+		if (params->base.dramtype == LPDDR4)
+			tsel_rd_en = io->rd_odt_en;
+	} else {
 		tsel_rd_en = 0;
+	}
 
 	tsel_wr_en = 0;
 	tsel_idle_en = 0;
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-38-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#105 lore raw

Re: [PATCH v3 37/57] ram: rk3399: Get lpddr4 tsel_rd_en from io settings

Quoted 7 lines · Jagan Teki

For base.odt 1 the lpddr4 tsel_rd_en value is depending on IO settings of rd_odt_en.

Add support for it.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 15 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 8 ++++++--
  1 file changed, 6 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +1 -1
index e0be9d2485..9e40880835 100644
@@ -645,10 +645,14 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
  	}
 
-	if (params->base.odt == 1)
+	if (params->base.odt == 1) {
  		tsel_rd_en = 1;

drivers/ram/rockchip/sdram_rk3399.c static void set_ds_odt(const struct chan_info *chan, · line 658

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +5 -1
-	else
+
+		if (params->base.dramtype == LPDDR4)
+			tsel_rd_en = io->rd_odt_en;
+	} else {
  		tsel_rd_en = 0;
+	}
 
  	tsel_wr_en = 0;
  	tsel_idle_en = 0;

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#106 lore raw

PATCH v3 38/57 ram: rk3399: Update lpddr4 vref based on io settings

In reply to a message not in the archive

The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref.

Add support for it.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +14 -5
index 9e40880835..4a2622a440 100644
@@ -338,7 +338,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
 }
 
 static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *params)
+			 const struct rk3399_sdram_params *params, u32 mr5)
 {
 	u32 *denali_phy = chan->publ->denali_phy;
 	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;

@@ -349,9 +349,18 @@ static int phy_io_config(const struct chan_info *chan,
 
 	/* vref setting */
 	if (params->base.dramtype == LPDDR4) {
-		/* LPDDR4 */
-		vref_mode_dq = 0x6;
-		vref_value_dq = 0x1f;
+		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
+		u32 rd_vref = io->rd_vref * 1000;
+
+		if (rd_vref < 36700) {
+			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
+			vref_mode_dq = 0x7;
+			vref_value_dq = (rd_vref - 3300) / 521;
+		} else {
+			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
+			vref_mode_dq = 0x6;
+			vref_value_dq = (rd_vref - 15300) / 521;
+		}
 		vref_mode_ac = 0x6;
 		vref_value_ac = 0x1f;
 		mode_sel = 0x6;

@@ -770,7 +779,7 @@ static void set_ds_odt(const struct chan_info *chan,
 	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
 	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 
-	phy_io_config(chan, params);
+	phy_io_config(chan, params, mr5);
 }
 
 static void pctl_start(struct dram_info *dram, u8 channel)
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-39-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#108 lore raw

Re: [PATCH v3 38/57] ram: rk3399: Update lpddr4 vref based on io settings

Quoted 7 lines · Jagan Teki

The vref_mode_dq, vref_value_dq on lpddr4 value is depending on IO settings of rd_vref.

Add support for it.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 40 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++-----
  1 file changed, 14 insertions(+), 5 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +13 -4
index 9e40880835..4a2622a440 100644
@@ -338,7 +338,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  }
 
  static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *params)
+			 const struct rk3399_sdram_params *params, u32 mr5)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;

@@ -349,9 +349,18 @@ static int phy_io_config(const struct chan_info *chan,
 
  	/* vref setting */
  	if (params->base.dramtype == LPDDR4) {
-		/* LPDDR4 */
-		vref_mode_dq = 0x6;
-		vref_value_dq = 0x1f;
+		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
+		u32 rd_vref = io->rd_vref * 1000;
+
+		if (rd_vref < 36700) {
+			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
+			vref_mode_dq = 0x7;
+			vref_value_dq = (rd_vref - 3300) / 521;
+		} else {
+			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
+			vref_mode_dq = 0x6;
+			vref_value_dq = (rd_vref - 15300) / 521;
+		}
  		vref_mode_ac = 0x6;
  		vref_value_ac = 0x1f;
  		mode_sel = 0x6;

drivers/ram/rockchip/sdram_rk3399.c static void set_ds_odt(const struct chan_info *chan, · line 785

Quoted 8 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -1
@@ -770,7 +779,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
  	clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
 
-	phy_io_config(chan, params);
+	phy_io_config(chan, params, mr5);
  }
 
  static void pctl_start(struct dram_info *dram, u8 channel)

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#109 lore raw

PATCH v3 39/57 ram: rk3399: Update lpddr4 mode_sel based on io settings

In reply to a message not in the archive

The mode_sel on lpddr4 value is depending on IO settings of rd_vref.

Add support for it.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +5 -2
index 4a2622a440..63763062f9 100644
@@ -347,7 +347,7 @@ static int phy_io_config(const struct chan_info *chan,
 	u32 drv_value, odt_value;
 	u32 speed;
 
-	/* vref setting */
+	/* vref setting & mode setting */
 	if (params->base.dramtype == LPDDR4) {
 		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
 		u32 rd_vref = io->rd_vref * 1000;

@@ -355,15 +355,18 @@ static int phy_io_config(const struct chan_info *chan,
 		if (rd_vref < 36700) {
 			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
 			vref_mode_dq = 0x7;
+			/* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
+			mode_sel = 0x5;
 			vref_value_dq = (rd_vref - 3300) / 521;
 		} else {
 			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
 			vref_mode_dq = 0x6;
+			/* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
+			mode_sel = 0x4;
 			vref_value_dq = (rd_vref - 15300) / 521;
 		}
 		vref_mode_ac = 0x6;
 		vref_value_ac = 0x1f;
-		mode_sel = 0x6;
 	} else if (params->base.dramtype == LPDDR3) {
 		if (params->base.odt == 1) {
 			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-40-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#111 lore raw

Re: [PATCH v3 39/57] ram: rk3399: Update lpddr4 mode_sel based on io settings

Quoted 7 lines · Jagan Teki

The mode_sel on lpddr4 value is depending on IO settings of rd_vref.

Add support for it.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 27 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 7 +++++--
  1 file changed, 5 insertions(+), 2 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +3 -1
index 4a2622a440..63763062f9 100644
@@ -347,7 +347,7 @@ static int phy_io_config(const struct chan_info *chan,
  	u32 drv_value, odt_value;
  	u32 speed;
 
-	/* vref setting */
+	/* vref setting & mode setting */
  	if (params->base.dramtype == LPDDR4) {
  		struct io_setting *io = lpddr4_get_io_settings(params, mr5);
  		u32 rd_vref = io->rd_vref * 1000;

@@ -355,15 +355,18 @@ static int phy_io_config(const struct chan_info *chan,
  		if (rd_vref < 36700) {
  			/* MODE_LV[2:0] = LPDDR4 (Range 2)*/
  			vref_mode_dq = 0x7;
+			/* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
+			mode_sel = 0x5;
  			vref_value_dq = (rd_vref - 3300) / 521;
  		} else {
  			/* MODE_LV[2:0] = LPDDR4 (Range 1)*/
  			vref_mode_dq = 0x6;

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 372

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +2 -1
+			/* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
+			mode_sel = 0x4;
  			vref_value_dq = (rd_vref - 15300) / 521;
  		}
  		vref_mode_ac = 0x6;
  		vref_value_ac = 0x1f;
-		mode_sel = 0x6;
  	} else if (params->base.dramtype == LPDDR3) {
  		if (params->base.odt == 1) {
  			vref_mode_dq = 0x5;  /* LPDDR3 ODT */

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#112 lore raw

PATCH v3 40/57 ram: rk3399: Update lpddr4 vref_mode_ac

In reply to a message not in the archive

Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +2 -1
index 63763062f9..e3f1abf7e7 100644
@@ -366,7 +366,8 @@ static int phy_io_config(const struct chan_info *chan,
 			vref_value_dq = (rd_vref - 15300) / 521;
 		}
 		vref_mode_ac = 0x6;
-		vref_value_ac = 0x1f;
+		/* VDDQ/3/2=16.8% */
+		vref_value_ac = 0x3;
 	} else if (params->base.dramtype == LPDDR3) {
 		if (params->base.odt == 1) {
 			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
Signature · 1 line
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Reviewed-by
#114 lore raw

Re: [PATCH v3 40/57] ram: rk3399: Update lpddr4 vref_mode_ac

Quoted 4 lines · Jagan Teki

Update vref_mode_ac for lpddr4 based on VDDQ/3/2=16.8%

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)
drivers/ram/rockchip/sdram_rk3399.c +0 -0
index 63763062f9..e3f1abf7e7 100644

drivers/ram/rockchip/sdram_rk3399.c static int phy_io_config(const struct chan_info *chan, · line 373

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +2 -1
@@ -366,7 +366,8 @@ static int phy_io_config(const struct chan_info *chan,
  			vref_value_dq = (rd_vref - 15300) / 521;
  		}
  		vref_mode_ac = 0x6;
-		vref_value_ac = 0x1f;
+		/* VDDQ/3/2=16.8% */
+		vref_value_ac = 0x3;
  	} else if (params->base.dramtype == LPDDR3) {
  		if (params->base.odt == 1) {
  			vref_mode_dq = 0x5;  /* LPDDR3 ODT */

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#115 lore raw

PATCH v3 41/57 ram: rk3399: Simplify data training first argument

In reply to a message not in the archive

data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition.

This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/sdram_rk3399.c | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +4 -5
index e3f1abf7e7..1aaaeb5b88 100644
@@ -1286,10 +1286,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
 	return 0;
 }
 
-static int data_training(const struct chan_info *chan, u32 channel,
+static int data_training(struct dram_info *dram, u32 channel,
 			 const struct rk3399_sdram_params *params,
 			 u32 training_flag)
 {
+	struct chan_info *chan = &dram->chan[channel];
 	u32 *denali_phy = chan->publ->denali_phy;
 	int ret;
 

@@ -1498,8 +1499,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
 	for (channel = 0; channel < ch_count; channel++) {
 		denali_phy = dram->chan[channel].publ->denali_phy;
 		clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
-		ret = data_training(&dram->chan[channel], channel,
-				    params, PI_FULL_TRAINING);
+		ret = data_training(dram, channel, params, PI_FULL_TRAINING);
 		if (ret < 0) {
 			debug("index1 training failed\n");
 			return ret;

@@ -1662,8 +1662,7 @@ static int sdram_init(struct dram_info *dram,
 			if (params->base.dramtype == LPDDR3)
 				training_flag |= PI_CA_TRAINING;
 
-			if (!(data_training(&dram->chan[ch], ch,
-					    params, training_flag)))
+			if (!(data_training(dram, ch, params, training_flag)))
 				break;
 		}
 		/* Computed rank with associated channel number */
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-42-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#117 lore raw

Re: [PATCH v3 41/57] ram: rk3399: Simplify data training first argument

Quoted 10 lines · Jagan Teki

data training is using chan_info as first argument with channel number as second argument instead of that use dram_info as first argument so-that we can get the chan_info at data training definition.

This was the argument handling is meaningful, readable and it would help to add similar data training for lpddr4 in future.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 32 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 9 ++++-----
  1 file changed, 4 insertions(+), 5 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +3 -3
index e3f1abf7e7..1aaaeb5b88 100644
@@ -1286,10 +1286,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
  	return 0;
  }
 
-static int data_training(const struct chan_info *chan, u32 channel,
+static int data_training(struct dram_info *dram, u32 channel,
  			 const struct rk3399_sdram_params *params,
  			 u32 training_flag)
  {
+	struct chan_info *chan = &dram->chan[channel];
  	u32 *denali_phy = chan->publ->denali_phy;
  	int ret;
 

@@ -1498,8 +1499,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
  	for (channel = 0; channel < ch_count; channel++) {
  		denali_phy = dram->chan[channel].publ->denali_phy;
  		clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
-		ret = data_training(&dram->chan[channel], channel,
-				    params, PI_FULL_TRAINING);
+		ret = data_training(dram, channel, params, PI_FULL_TRAINING);
  		if (ret < 0) {
  			debug("index1 training failed\n");
  			return ret;

drivers/ram/rockchip/sdram_rk3399.c static int sdram_init(struct dram_info *dram, · line 1668

Quoted 9 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -2
@@ -1662,8 +1662,7 @@ static int sdram_init(struct dram_info *dram,
  			if (params->base.dramtype == LPDDR3)
  				training_flag |= PI_CA_TRAINING;
 
-			if (!(data_training(&dram->chan[ch], ch,
-					    params, training_flag)))
+			if (!(data_training(dram, ch, params, training_flag)))
  				break;
  		}
  		/* Computed rank with associated channel number */

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#118 lore raw

PATCH v3 42/57 ram: rk3399: Handle data training via ops

In reply to a message not in the archive

data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4.

For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/sdram_rk3399.c | 43 ++++++++++++++++++++++-------
 1 file changed, 33 insertions(+), 10 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +33 -10
index 1aaaeb5b88..da01f08732 100644
@@ -65,11 +65,17 @@ struct dram_info {
 	struct rk3399_pmucru *pmucru;
 	struct rk3399_pmusgrf_regs *pmusgrf;
 	struct rk3399_ddr_cic_regs *cic;
+	const struct sdram_rk3399_ops *ops;
 #endif
 	struct ram_info info;
 	struct rk3399_pmugrf_regs *pmugrf;
 };
 
+struct sdram_rk3399_ops {
+	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
+			     struct rk3399_sdram_params *sdram);
+};
+
 #if defined(CONFIG_TPL_BUILD) || \
 	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 

@@ -1464,6 +1470,23 @@ static void dram_all_config(struct dram_info *dram,
 	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
 }
 
+static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
+				 struct rk3399_sdram_params *params)
+{
+	u8 training_flag = PI_READ_GATE_TRAINING;
+
+	/*
+	 * LPDDR3 CA training msut be trigger before
+	 * other training.
+	 * DDR3 is not have CA training.
+	 */
+
+	if (params->base.dramtype == LPDDR3)
+		training_flag |= PI_CA_TRAINING;
+
+	return data_training(dram, channel, params, training_flag);
+}
+
 static int switch_to_phy_index1(struct dram_info *dram,
 				const struct rk3399_sdram_params *params)
 {

@@ -1626,7 +1649,6 @@ static int sdram_init(struct dram_info *dram,
 {
 	unsigned char dramtype = params->base.dramtype;
 	unsigned int ddr_freq = params->base.ddr_freq;
-	u32 training_flag = PI_READ_GATE_TRAINING;
 	int channel, ch, rank;
 	int ret;
 

@@ -1654,16 +1676,12 @@ static int sdram_init(struct dram_info *dram,
 
 			params->ch[ch].cap_info.rank = rank;
 
-			/*
-			 * LPDDR3 CA training msut be trigger before
-			 * other training.
-			 * DDR3 is not have CA training.
-			 */
-			if (params->base.dramtype == LPDDR3)
-				training_flag |= PI_CA_TRAINING;
-
-			if (!(data_training(dram, ch, params, training_flag)))
+			ret = dram->ops->data_training(dram, ch, rank, params);
+			if (!ret) {
+				debug("%s: data trained for rank %d, ch %d\n",
+				      __func__, rank, ch);
 				break;
+			}
 		}
 		/* Computed rank with associated channel number */
 		params->ch[ch].cap_info.rank = rank;

@@ -1743,6 +1761,10 @@ static int conv_of_platdata(struct udevice *dev)
 }
 #endif
 
+static const struct sdram_rk3399_ops rk3399_ops = {
+	.data_training = default_data_training,
+};
+
 static int rk3399_dmc_init(struct udevice *dev)
 {
 	struct dram_info *priv = dev_get_priv(dev);

@@ -1760,6 +1782,7 @@ static int rk3399_dmc_init(struct udevice *dev)
 		return ret;
 #endif
 
+	priv->ops = &rk3399_ops;
 	priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
Signature · 1 line
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A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-43-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#120 lore raw

Re: [PATCH v3 42/57] ram: rk3399: Handle data training via ops

Quoted 9 lines · Jagan Teki

data training can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4.

For this requirement, and for code readability handle data training via sdram_rk3399_ops and same will update in future while supporting lpddr4 code.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 92 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 43 ++++++++++++++++++++++-------
  1 file changed, 33 insertions(+), 10 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +32 -10
index 1aaaeb5b88..da01f08732 100644
@@ -65,11 +65,17 @@ struct dram_info {
  	struct rk3399_pmucru *pmucru;
  	struct rk3399_pmusgrf_regs *pmusgrf;
  	struct rk3399_ddr_cic_regs *cic;
+	const struct sdram_rk3399_ops *ops;
  #endif
  	struct ram_info info;
  	struct rk3399_pmugrf_regs *pmugrf;
  };
 
+struct sdram_rk3399_ops {
+	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
+			     struct rk3399_sdram_params *sdram);
+};
+
  #if defined(CONFIG_TPL_BUILD) || \
  	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 

@@ -1464,6 +1470,23 @@ static void dram_all_config(struct dram_info *dram,
  	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
  }
 
+static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
+				 struct rk3399_sdram_params *params)
+{
+	u8 training_flag = PI_READ_GATE_TRAINING;
+
+	/*
+	 * LPDDR3 CA training msut be trigger before
+	 * other training.
+	 * DDR3 is not have CA training.
+	 */
+
+	if (params->base.dramtype == LPDDR3)
+		training_flag |= PI_CA_TRAINING;
+
+	return data_training(dram, channel, params, training_flag);
+}
+
  static int switch_to_phy_index1(struct dram_info *dram,
  				const struct rk3399_sdram_params *params)
  {

@@ -1626,7 +1649,6 @@ static int sdram_init(struct dram_info *dram,
  {
  	unsigned char dramtype = params->base.dramtype;
  	unsigned int ddr_freq = params->base.ddr_freq;
-	u32 training_flag = PI_READ_GATE_TRAINING;
  	int channel, ch, rank;
  	int ret;
 

@@ -1654,16 +1676,12 @@ static int sdram_init(struct dram_info *dram,
 
  			params->ch[ch].cap_info.rank = rank;
 
-			/*
-			 * LPDDR3 CA training msut be trigger before
-			 * other training.
-			 * DDR3 is not have CA training.
-			 */
-			if (params->base.dramtype == LPDDR3)
-				training_flag |= PI_CA_TRAINING;
-
-			if (!(data_training(dram, ch, params, training_flag)))
+			ret = dram->ops->data_training(dram, ch, rank, params);
+			if (!ret) {
+				debug("%s: data trained for rank %d, ch %d\n",
+				      __func__, rank, ch);
  				break;
+			}
  		}
  		/* Computed rank with associated channel number */
  		params->ch[ch].cap_info.rank = rank;

@@ -1743,6 +1761,10 @@ static int conv_of_platdata(struct udevice *dev)
  }
  #endif
 
+static const struct sdram_rk3399_ops rk3399_ops = {
+	.data_training = default_data_training,
+};
+
  static int rk3399_dmc_init(struct udevice *dev)
  {
  	struct dram_info *priv = dev_get_priv(dev);

drivers/ram/rockchip/sdram_rk3399.c static int rk3399_dmc_init(struct udevice *dev) · line 1788

Quoted 7 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -0
@@ -1760,6 +1782,7 @@ static int rk3399_dmc_init(struct udevice *dev)
  		return ret;
  #endif
 
+	priv->ops = &rk3399_ops;
  	priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
  	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);

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#121 lore raw

PATCH v3 43/57 ram: rk3399: Add LPPDR4 mr detection

In reply to a message not in the archive

Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held.

Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization.

So, add code to support for it.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 226 ++++++++++++++++++++++++++++
 1 file changed, 226 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +226 -0
index da01f08732..623685e3c5 100644
@@ -1470,6 +1470,7 @@ static void dram_all_config(struct dram_info *dram,
 	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
 }
 
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
 static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 				 struct rk3399_sdram_params *params)
 {

@@ -1486,6 +1487,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 
 	return data_training(dram, channel, params, training_flag);
 }
+#endif
 
 static int switch_to_phy_index1(struct dram_info *dram,
 				const struct rk3399_sdram_params *params)

@@ -1532,6 +1534,226 @@ static int switch_to_phy_index1(struct dram_info *dram,
 	return 0;
 }
 
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
+{
+	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
+}
+
+static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
+{
+	rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
+}
+
+static void set_cap_relate_config(const struct chan_info *chan,
+				  struct rk3399_sdram_params *params,
+				  unsigned int channel)
+{
+	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 tmp;
+	struct rk3399_msch_timings *noc_timing;
+
+	if (params->base.dramtype == LPDDR3) {
+		tmp = (8 << params->ch[channel].cap_info.bw) /
+			(8 << params->ch[channel].cap_info.dbw);
+
+		/**
+		 * memdata_ratio
+		 * 1 -> 0, 2 -> 1, 4 -> 2
+		 */
+		clrsetbits_le32(&denali_ctl[197], 0x7,
+				(tmp >> 1));
+		clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+				(tmp >> 1) << 8);
+	}
+
+	noc_timing = &params->ch[channel].noc_timings;
+
+	/*
+	 * noc timing bw relate timing is 32 bit, and real bw is 16bit
+	 * actually noc reg is setting at function dram_all_config
+	 */
+	if (params->ch[channel].cap_info.bw == 16 &&
+	    noc_timing->ddrmode.b.mwrsize == 2) {
+		if (noc_timing->ddrmode.b.burstsize)
+			noc_timing->ddrmode.b.burstsize -= 1;
+		noc_timing->ddrmode.b.mwrsize -= 1;
+		noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+		noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+	}
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
+{
+	unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
+	unsigned int col = params->ch[channel].cap_info.col;
+	unsigned int bw = params->ch[channel].cap_info.bw;
+	u16  ddr_cfg_2_rbc[] = {
+		/*
+		 * [6]	  highest bit col
+		 * [5:3]  max row(14+n)
+		 * [2]    insertion row
+		 * [1:0]  col(9+n),col, data bus 32bit
+		 *
+		 * highbitcol, max_row, insertion_row,  col
+		 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+		((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+		((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+		((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+		((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+		((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+		((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+	};
+	u32 i;
+
+	col -= (bw == 2) ? 0 : 1;
+	col -= 9;
+
+	for (i = 0; i < 4; i++) {
+		if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+		    (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+			break;
+	}
+
+	if (i >= 4)
+		i = -EINVAL;
+
+	return i;
+}
+
+/**
+ * read mr_num mode register
+ * rank = 1: cs0
+ * rank = 2: cs1
+ */
+static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
+		   u32 mr_num, u32 *buf)
+{
+	s32 timeout = 100;
+
+	writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
+	       &ddr_pctl_regs->denali_ctl[118]);
+
+	while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
+			((1 << 21) | (1 << 12)))) {
+		udelay(1);
+
+		if (timeout <= 0) {
+			printf("%s: pctl timeout!\n", __func__);
+			return -ETIMEDOUT;
+		}
+
+		timeout--;
+	}
+
+	if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
+		*buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
+	} else {
+		printf("%s: read mr failed with 0x%x status\n", __func__,
+		       readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
+		*buf = 0;
+	}
+
+	setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
+
+	return 0;
+}
+
+static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
+			    struct rk3399_sdram_params *params)
+{
+	u64 cs0_cap;
+	u32 stride;
+	u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
+	u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
+	u32 mr5, mr12, mr14;
+	struct chan_info *chan = &dram->chan[channel];
+	struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
+	void __iomem *addr = NULL;
+	int ret = 0;
+	u32 val;
+
+	stride = get_ddr_stride(dram->pmusgrf);
+
+	if (params->ch[channel].cap_info.col == 0) {
+		ret = -EPERM;
+		goto end;
+	}
+
+	cs = params->ch[channel].cap_info.rank;
+	col = params->ch[channel].cap_info.col;
+	bk = params->ch[channel].cap_info.bk;
+	bw = params->ch[channel].cap_info.bw;
+	row_3_4 = params->ch[channel].cap_info.row_3_4;
+	cs0_row = params->ch[channel].cap_info.cs0_row;
+	cs1_row = params->ch[channel].cap_info.cs1_row;
+	ddrconfig = params->ch[channel].cap_info.ddrconfig;
+
+	/* 2GB */
+	params->ch[channel].cap_info.rank = 2;
+	params->ch[channel].cap_info.col = 10;
+	params->ch[channel].cap_info.bk = 3;
+	params->ch[channel].cap_info.bw = 2;
+	params->ch[channel].cap_info.row_3_4 = 0;
+	params->ch[channel].cap_info.cs0_row = 15;
+	params->ch[channel].cap_info.cs1_row = 15;
+	params->ch[channel].cap_info.ddrconfig = 1;
+
+	set_memory_map(chan, channel, params);
+	params->ch[channel].cap_info.ddrconfig =
+			calculate_ddrconfig(params, channel);
+	set_ddrconfig(chan, params, channel,
+		      params->ch[channel].cap_info.ddrconfig);
+	set_cap_relate_config(chan, params, channel);
+
+	cs0_cap = (1 << (params->ch[channel].cap_info.bw
+			+ params->ch[channel].cap_info.col
+			+ params->ch[channel].cap_info.bk
+			+ params->ch[channel].cap_info.cs0_row));
+
+	if (params->ch[channel].cap_info.row_3_4)
+		cs0_cap = cs0_cap * 3 / 4;
+
+	if (channel == 0)
+		set_ddr_stride(dram->pmusgrf, 0x17);
+	else
+		set_ddr_stride(dram->pmusgrf, 0x18);
+
+	/* read and write data to DRAM, avoid be optimized by compiler. */
+	if (rank == 1)
+		addr = (void __iomem *)0x100;
+	else if (rank == 2)
+		addr = (void __iomem *)(cs0_cap + 0x100);
+
+	val = readl(addr);
+	writel(val + 1, addr);
+
+	read_mr(ddr_pctl_regs, rank, 5, &mr5);
+	read_mr(ddr_pctl_regs, rank, 12, &mr12);
+	read_mr(ddr_pctl_regs, rank, 14, &mr14);
+
+	if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
+		ret = -EINVAL;
+		goto end;
+	}
+end:
+	params->ch[channel].cap_info.rank = cs;
+	params->ch[channel].cap_info.col = col;
+	params->ch[channel].cap_info.bk = bk;
+	params->ch[channel].cap_info.bw = bw;
+	params->ch[channel].cap_info.row_3_4 = row_3_4;
+	params->ch[channel].cap_info.cs0_row = cs0_row;
+	params->ch[channel].cap_info.cs1_row = cs1_row;
+	params->ch[channel].cap_info.ddrconfig = ddrconfig;
+
+	set_ddr_stride(dram->pmusgrf, stride);
+
+	return ret;
+}
+#endif /* CONFIG_RAM_RK3399_LPDDR4 */
+
 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
 {
 	unsigned int stride = params->base.stride;

@@ -1762,7 +1984,11 @@ static int conv_of_platdata(struct udevice *dev)
 #endif
 
 static const struct sdram_rk3399_ops rk3399_ops = {
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
 	.data_training = default_data_training,
+#else
+	.data_training = lpddr4_mr_detect,
+#endif
 };
 
 static int rk3399_dmc_init(struct udevice *dev)
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-44-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#123 lore raw

Re: [PATCH v3 43/57] ram: rk3399: Add LPPDR4 mr detection

Quoted 4 lines · Jagan Teki

Like data training in other sdram types, mr detection need to taken care for lpddr4 with looped rank and associated channel to make sure the proper configuration held.

Quoted 8 lines

Once the mr detection successful for active and configured rank with channel number, the same can later reused during actual LPDDR4 initialization.

So, add code to support for it.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 253 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 226 ++++++++++++++++++++++++++++
  1 file changed, 226 insertions(+)
drivers/ram/rockchip/sdram_rk3399.c +222 -0
index da01f08732..623685e3c5 100644
@@ -1470,6 +1470,7 @@ static void dram_all_config(struct dram_info *dram,
  	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
  }
 
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
  static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
  				 struct rk3399_sdram_params *params)
  {

@@ -1486,6 +1487,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 
  	return data_training(dram, channel, params, training_flag);
  }
+#endif
 
  static int switch_to_phy_index1(struct dram_info *dram,
  				const struct rk3399_sdram_params *params)

@@ -1532,6 +1534,226 @@ static int switch_to_phy_index1(struct dram_info *dram,
  	return 0;
  }
 
+#if defined(CONFIG_RAM_RK3399_LPDDR4)
+static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
+{
+	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
+}
+
+static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
+{
+	rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
+}
+
+static void set_cap_relate_config(const struct chan_info *chan,
+				  struct rk3399_sdram_params *params,
+				  unsigned int channel)
+{
+	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 tmp;
+	struct rk3399_msch_timings *noc_timing;
+
+	if (params->base.dramtype == LPDDR3) {
+		tmp = (8 << params->ch[channel].cap_info.bw) /
+			(8 << params->ch[channel].cap_info.dbw);
+
+		/**
+		 * memdata_ratio
+		 * 1 -> 0, 2 -> 1, 4 -> 2
+		 */
+		clrsetbits_le32(&denali_ctl[197], 0x7,
+				(tmp >> 1));
+		clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+				(tmp >> 1) << 8);
+	}
+
+	noc_timing = &params->ch[channel].noc_timings;
+
+	/*
+	 * noc timing bw relate timing is 32 bit, and real bw is 16bit
+	 * actually noc reg is setting at function dram_all_config
+	 */
+	if (params->ch[channel].cap_info.bw == 16 &&
+	    noc_timing->ddrmode.b.mwrsize == 2) {
+		if (noc_timing->ddrmode.b.burstsize)
+			noc_timing->ddrmode.b.burstsize -= 1;
+		noc_timing->ddrmode.b.mwrsize -= 1;
+		noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+		noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+	}
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
+{
+	unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
+	unsigned int col = params->ch[channel].cap_info.col;
+	unsigned int bw = params->ch[channel].cap_info.bw;
+	u16  ddr_cfg_2_rbc[] = {
+		/*
+		 * [6]	  highest bit col
+		 * [5:3]  max row(14+n)
+		 * [2]    insertion row
+		 * [1:0]  col(9+n),col, data bus 32bit
+		 *
+		 * highbitcol, max_row, insertion_row,  col
+		 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+		((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+		((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+		((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+		((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+		((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+		((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+	};
+	u32 i;
+
+	col -= (bw == 2) ? 0 : 1;
+	col -= 9;
+
+	for (i = 0; i < 4; i++) {
+		if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+		    (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+			break;
+	}
+
+	if (i >= 4)
+		i = -EINVAL;
+
+	return i;
+}
+
+/**
+ * read mr_num mode register
+ * rank = 1: cs0
+ * rank = 2: cs1
+ */
+static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
+		   u32 mr_num, u32 *buf)
+{
+	s32 timeout = 100;
+
+	writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
+	       &ddr_pctl_regs->denali_ctl[118]);
+
+	while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
+			((1 << 21) | (1 << 12)))) {
+		udelay(1);
+
+		if (timeout <= 0) {
+			printf("%s: pctl timeout!\n", __func__);
+			return -ETIMEDOUT;
+		}
+
+		timeout--;
+	}
+
+	if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
+		*buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
+	} else {
+		printf("%s: read mr failed with 0x%x status\n", __func__,
+		       readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
+		*buf = 0;
+	}
+
+	setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
+
+	return 0;
+}
+
+static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
+			    struct rk3399_sdram_params *params)
+{
+	u64 cs0_cap;
+	u32 stride;
+	u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
+	u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
+	u32 mr5, mr12, mr14;
+	struct chan_info *chan = &dram->chan[channel];
+	struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
+	void __iomem *addr = NULL;
+	int ret = 0;
+	u32 val;
+
+	stride = get_ddr_stride(dram->pmusgrf);
+
+	if (params->ch[channel].cap_info.col == 0) {
+		ret = -EPERM;
+		goto end;
+	}
+
+	cs = params->ch[channel].cap_info.rank;
+	col = params->ch[channel].cap_info.col;
+	bk = params->ch[channel].cap_info.bk;
+	bw = params->ch[channel].cap_info.bw;
+	row_3_4 = params->ch[channel].cap_info.row_3_4;
+	cs0_row = params->ch[channel].cap_info.cs0_row;
+	cs1_row = params->ch[channel].cap_info.cs1_row;
+	ddrconfig = params->ch[channel].cap_info.ddrconfig;
+
+	/* 2GB */
+	params->ch[channel].cap_info.rank = 2;
+	params->ch[channel].cap_info.col = 10;
+	params->ch[channel].cap_info.bk = 3;
+	params->ch[channel].cap_info.bw = 2;
+	params->ch[channel].cap_info.row_3_4 = 0;
+	params->ch[channel].cap_info.cs0_row = 15;
+	params->ch[channel].cap_info.cs1_row = 15;
+	params->ch[channel].cap_info.ddrconfig = 1;
+
+	set_memory_map(chan, channel, params);
+	params->ch[channel].cap_info.ddrconfig =
+			calculate_ddrconfig(params, channel);
+	set_ddrconfig(chan, params, channel,
+		      params->ch[channel].cap_info.ddrconfig);
+	set_cap_relate_config(chan, params, channel);
+
+	cs0_cap = (1 << (params->ch[channel].cap_info.bw
+			+ params->ch[channel].cap_info.col
+			+ params->ch[channel].cap_info.bk
+			+ params->ch[channel].cap_info.cs0_row));
+
+	if (params->ch[channel].cap_info.row_3_4)
+		cs0_cap = cs0_cap * 3 / 4;
+
+	if (channel == 0)
+		set_ddr_stride(dram->pmusgrf, 0x17);
+	else
+		set_ddr_stride(dram->pmusgrf, 0x18);
+
+	/* read and write data to DRAM, avoid be optimized by compiler. */
+	if (rank == 1)
+		addr = (void __iomem *)0x100;
+	else if (rank == 2)
+		addr = (void __iomem *)(cs0_cap + 0x100);
+
+	val = readl(addr);
+	writel(val + 1, addr);
+
+	read_mr(ddr_pctl_regs, rank, 5, &mr5);
+	read_mr(ddr_pctl_regs, rank, 12, &mr12);
+	read_mr(ddr_pctl_regs, rank, 14, &mr14);
+
+	if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
+		ret = -EINVAL;
+		goto end;
+	}
+end:
+	params->ch[channel].cap_info.rank = cs;
+	params->ch[channel].cap_info.col = col;
+	params->ch[channel].cap_info.bk = bk;
+	params->ch[channel].cap_info.bw = bw;
+	params->ch[channel].cap_info.row_3_4 = row_3_4;
+	params->ch[channel].cap_info.cs0_row = cs0_row;
+	params->ch[channel].cap_info.cs1_row = cs1_row;
+	params->ch[channel].cap_info.ddrconfig = ddrconfig;
+
+	set_ddr_stride(dram->pmusgrf, stride);
+
+	return ret;
+}
+#endif /* CONFIG_RAM_RK3399_LPDDR4 */
+
  static unsigned char calculate_stride(struct rk3399_sdram_params *params)
  {
  	unsigned int stride = params->base.stride;

@@ -1762,7 +1984,11 @@ static int conv_of_platdata(struct udevice *dev)
  #endif

drivers/ram/rockchip/sdram_rk3399.c static int conv_of_platdata(struct udevice *dev) · line 1994

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +4 -0
 
  static const struct sdram_rk3399_ops rk3399_ops = {
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
  	.data_training = default_data_training,
+#else
+	.data_training = lpddr4_mr_detect,
+#endif
  };
 
  static int rk3399_dmc_init(struct udevice *dev)

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#124 lore raw

PATCH v3 44/57 arm: include: rockchip: Add rk3399 pmu file

In reply to a message not in the archive

Add pmu header file for rk3399 SoC, this will help to configure pmu in sdram driver.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 .../include/asm/arch-rockchip/pmu_rk3399.h    | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h
arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file +72 -0
new file mode 100644
index 0000000000..f1096dccce
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+	u32 pmu_wakeup_cfg[5];
+	u32 pmu_pwrdn_con;
+	u32 pmu_pwrdn_st;
+	u32 pmu_pll_con;
+	u32 pmu_pwrmode_con;
+	u32 pmu_sft_con;
+	u32 pmu_int_con;
+	u32 pmu_int_st;
+	u32 pmu_gpio0_pos_int_con;
+	u32 pmu_gpio0_net_int_con;
+	u32 pmu_gpio1_pos_int_con;
+	u32 pmu_gpio1_net_int_con;
+	u32 pmu_gpio0_pos_int_st;
+	u32 pmu_gpio0_net_int_st;
+	u32 pmu_gpio1_pos_int_st;
+	u32 pmu_gpio1_net_int_st;
+	u32 pmu_pwrdn_inten;
+	u32 pmu_pwrdn_status;
+	u32 pmu_wakeup_status;
+	u32 pmu_bus_clr;
+	u32 pmu_bus_idle_req;
+	u32 pmu_bus_idle_st;
+	u32 pmu_bus_idle_ack;
+	u32 pmu_cci500_con;
+	u32 pmu_adb400_con;
+	u32 pmu_adb400_st;
+	u32 pmu_power_st;
+	u32 pmu_core_pwr_st;
+	u32 pmu_osc_cnt;
+	u32 pmu_plllock_cnt;
+	u32 pmu_pllrst_cnt;
+	u32 pmu_stable_cnt;
+	u32 pmu_ddrio_pwron_cnt;
+	u32 pmu_wakeup_rst_clr_cnt;
+	u32 pmu_ddr_sref_st;
+	u32 pmu_scu_l_pwrdn_cnt;
+	u32 pmu_scu_l_pwrup_cnt;
+	u32 pmu_scu_b_pwrdn_cnt;
+	u32 pmu_scu_b_pwrup_cnt;
+	u32 pmu_gpu_pwrdn_cnt;
+	u32 pmu_gpu_pwrup_cnt;
+	u32 pmu_center_pwrdn_cnt;
+	u32 pmu_center_pwrup_cnt;
+	u32 pmu_timeout_cnt;
+	u32 pmu_cpu0apm_con;
+	u32 pmu_cpu1apm_con;
+	u32 pmu_cpu2apm_con;
+	u32 pmu_cpu3apm_con;
+	u32 pmu_cpu0bpm_con;
+	u32 pmu_cpu1bpm_con;
+	u32 pmu_noc_auto_ena;
+	u32 pmu_pwrdn_con1;
+	u32 reserved0[0x4];
+	u32 pmu_sys_reg_reg0;
+	u32 pmu_sys_reg_reg1;
+	u32 pmu_sys_reg_reg2;
+	u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif	/* __SOC_ROCKCHIP_RK3399_PMU_H__ */
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-45-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#126 lore raw

Re: [PATCH v3 44/57] arm: include: rockchip: Add rk3399 pmu file

Quoted 5 lines · Jagan Teki

Add pmu header file for rk3399 SoC, this will help to configure pmu in sdram driver.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 73 lines
---
  .../include/asm/arch-rockchip/pmu_rk3399.h    | 72 +++++++++++++++++++
  1 file changed, 72 insertions(+)

create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3399.h

arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file +62 -0
new file mode 100644
index 0000000000..f1096dccce
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier:     GPL-2.0+ */
+/*
+ * (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_PMU_H__
+#define __SOC_ROCKCHIP_RK3399_PMU_H__
+
+struct rk3399_pmu_regs {
+	u32 pmu_wakeup_cfg[5];
+	u32 pmu_pwrdn_con;
+	u32 pmu_pwrdn_st;
+	u32 pmu_pll_con;
+	u32 pmu_pwrmode_con;
+	u32 pmu_sft_con;
+	u32 pmu_int_con;
+	u32 pmu_int_st;
+	u32 pmu_gpio0_pos_int_con;
+	u32 pmu_gpio0_net_int_con;
+	u32 pmu_gpio1_pos_int_con;
+	u32 pmu_gpio1_net_int_con;
+	u32 pmu_gpio0_pos_int_st;
+	u32 pmu_gpio0_net_int_st;
+	u32 pmu_gpio1_pos_int_st;
+	u32 pmu_gpio1_net_int_st;
+	u32 pmu_pwrdn_inten;
+	u32 pmu_pwrdn_status;
+	u32 pmu_wakeup_status;
+	u32 pmu_bus_clr;
+	u32 pmu_bus_idle_req;
+	u32 pmu_bus_idle_st;
+	u32 pmu_bus_idle_ack;
+	u32 pmu_cci500_con;
+	u32 pmu_adb400_con;
+	u32 pmu_adb400_st;
+	u32 pmu_power_st;
+	u32 pmu_core_pwr_st;
+	u32 pmu_osc_cnt;
+	u32 pmu_plllock_cnt;
+	u32 pmu_pllrst_cnt;
+	u32 pmu_stable_cnt;
+	u32 pmu_ddrio_pwron_cnt;
+	u32 pmu_wakeup_rst_clr_cnt;
+	u32 pmu_ddr_sref_st;
+	u32 pmu_scu_l_pwrdn_cnt;
+	u32 pmu_scu_l_pwrup_cnt;
+	u32 pmu_scu_b_pwrdn_cnt;
+	u32 pmu_scu_b_pwrup_cnt;
+	u32 pmu_gpu_pwrdn_cnt;
+	u32 pmu_gpu_pwrup_cnt;
+	u32 pmu_center_pwrdn_cnt;
+	u32 pmu_center_pwrup_cnt;
+	u32 pmu_timeout_cnt;
+	u32 pmu_cpu0apm_con;
+	u32 pmu_cpu1apm_con;
+	u32 pmu_cpu2apm_con;
+	u32 pmu_cpu3apm_con;
+	u32 pmu_cpu0bpm_con;
+	u32 pmu_cpu1bpm_con;
+	u32 pmu_noc_auto_ena;
+	u32 pmu_pwrdn_con1;

arch/arm/include/asm/arch-rockchip/pmu_rk3399.h line 72

Quoted 10 lines
arch/arm/include/asm/arch-rockchip/pmu_rk3399.h new file +10 -0
+	u32 reserved0[0x4];
+	u32 pmu_sys_reg_reg0;
+	u32 pmu_sys_reg_reg1;
+	u32 pmu_sys_reg_reg2;
+	u32 pmu_sys_reg_reg3;
+};
+
+check_member(rk3399_pmu_regs, pmu_sys_reg_reg3, 0xfc);
+
+#endif	/* __SOC_ROCKCHIP_RK3399_PMU_H__ */

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#127 lore raw

PATCH v3 45/57 rockchip: rk3399: syscon: Add pmu support

In reply to a message not in the archive

Add pmu compatible with relevant U_BOOT_DRIVER for rk3399 via syscon rk3399 driver.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 ++++++++
 1 file changed, 8 insertions(+)
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +8 -0
index a8bb5b11e5..259ca44d68 100644
@@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
 	{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
 	{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
 	{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+	{ .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
 	{ }
 };
 

@@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = {
 	.of_match = rk3399_syscon_ids + 3,
 	.bind = rk3399_syscon_bind_of_platdata,
 };
+
+U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
+	.name = "rockchip_rk3399_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3399_syscon_ids + 4,
+	.bind = rk3399_syscon_bind_of_platdata,
+};
 #endif
Signature · 1 line
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Reviewed-by
#129 lore raw

Re: [PATCH v3 45/57] rockchip: rk3399: syscon: Add pmu support

Quoted 5 lines · Jagan Teki

Add pmu compatible with relevant U_BOOT_DRIVER for rk3399 via syscon rk3399 driver.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 18 lines
---
  arch/arm/mach-rockchip/rk3399/syscon_rk3399.c | 8 ++++++++
  1 file changed, 8 insertions(+)
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +1 -0
index a8bb5b11e5..259ca44d68 100644
@@ -13,6 +13,7 @@ static const struct udevice_id rk3399_syscon_ids[] = {
  	{ .compatible = "rockchip,rk3399-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
  	{ .compatible = "rockchip,rk3399-pmusgrf", .data = ROCKCHIP_SYSCON_PMUSGRF },
  	{ .compatible = "rockchip,rk3399-cic", .data = ROCKCHIP_SYSCON_CIC },
+	{ .compatible = "rockchip,rk3399-pmu", .data = ROCKCHIP_SYSCON_PMU },
  	{ }
  };
 

@@ -58,4 +59,11 @@ U_BOOT_DRIVER(rockchip_rk3399_cic) = {
  	.of_match = rk3399_syscon_ids + 3,

arch/arm/mach-rockchip/rk3399/syscon_rk3399.c U_BOOT_DRIVER(rockchip_rk3399_cic) = { · line 69

Quoted 10 lines
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c +7 -0
  	.bind = rk3399_syscon_bind_of_platdata,
  };
+
+U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
+	.name = "rockchip_rk3399_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3399_syscon_ids + 4,
+	.bind = rk3399_syscon_bind_of_platdata,
+};
  #endif

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#130 lore raw

PATCH v3 46/57 rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu

In reply to a message not in the archive

Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi so-that SPL can access pmu.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++
 1 file changed, 4 insertions(+)
arch/arm/dts/rk3399-u-boot.dtsi +4 -0
index fcfce9ae02..2738a3889e 100644
@@ -3,6 +3,10 @@
  * Copyright (C) 2019 Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
  */
 
+&pmu {
+	u-boot,dm-pre-reloc;
+};
+
 &sdmmc {
 	u-boot,dm-pre-reloc;
 };
Signature · 1 line
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Reviewed-by
#132 lore raw

Re: [PATCH v3 46/57] rockchip: dts: rk3399: Add u-boot, dm-pre-reloc for pmu

Quoted 5 lines · Jagan Teki

Add u-boot,dm-pre-reloc property for pmu in rk3399-u-boot.dtsi so-that SPL can access pmu.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  arch/arm/dts/rk3399-u-boot.dtsi | 4 ++++
  1 file changed, 4 insertions(+)
arch/arm/dts/rk3399-u-boot.dtsi +0 -0
index fcfce9ae02..2738a3889e 100644

arch/arm/dts/rk3399-u-boot.dtsi line 12

Quoted 10 lines
arch/arm/dts/rk3399-u-boot.dtsi +4 -0
@@ -3,6 +3,10 @@
   * Copyright (C) 2019 Jagan Teki <[email protected]>
   */
 
+&pmu {
+	u-boot,dm-pre-reloc;
+};
+
  &sdmmc {
  	u-boot,dm-pre-reloc;
  };

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#133 lore raw

PATCH v3 47/57 clk: rockchip: rk3399: Set 50MHz ddr clock

In reply to a message not in the archive

Add support for setting 50MHz ddr clock.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/clk/rockchip/clk_rk3399.c +4 -0
index 5d1ad94e85..1de21c9f3e 100644
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
 	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
 	switch (set_rate) {
+	case 50 * MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+		break;
 	case 200 * MHz:
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
Signature · 1 line
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Reviewed-by
#135 lore raw

Re: [PATCH v3 47/57] clk: rockchip: rk3399: Set 50MHz ddr clock

Quoted 4 lines · Jagan Teki

Add support for setting 50MHz ddr clock.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  drivers/clk/rockchip/clk_rk3399.c | 4 ++++
  1 file changed, 4 insertions(+)
drivers/clk/rockchip/clk_rk3399.c +0 -0
index 5d1ad94e85..1de21c9f3e 100644

drivers/clk/rockchip/clk_rk3399.c static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, · line 836

Quoted 10 lines
drivers/clk/rockchip/clk_rk3399.c +4 -0
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
  	/*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
  	switch (set_rate) {
+	case 50 * MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+		break;
  	case 200 * MHz:
  		dpll_cfg = (struct pll_div)
  		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};

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#136 lore raw

PATCH v3 48/57 clk: rockchip: rk3399: Set 400MHz ddr clock

In reply to a message not in the archive

Add support for setting 400MHz ddr clock.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)
drivers/clk/rockchip/clk_rk3399.c +4 -0
index 1de21c9f3e..79007b8682 100644
@@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
 		break;
+	case 400 * MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+		break;
 	case 666 * MHz:
 		dpll_cfg = (struct pll_div)
 		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};
Signature · 1 line
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Reviewed-by
#138 lore raw

Re: [PATCH v3 48/57] clk: rockchip: rk3399: Set 400MHz ddr clock

Quoted 4 lines · Jagan Teki

Add support for setting 400MHz ddr clock.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  drivers/clk/rockchip/clk_rk3399.c | 4 ++++
  1 file changed, 4 insertions(+)
drivers/clk/rockchip/clk_rk3399.c +0 -0
index 1de21c9f3e..79007b8682 100644

drivers/clk/rockchip/clk_rk3399.c static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, · line 848

Quoted 10 lines
drivers/clk/rockchip/clk_rk3399.c +4 -0
@@ -839,6 +839,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
  		dpll_cfg = (struct pll_div)
  		{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};
  		break;
+	case 400 * MHz:
+		dpll_cfg = (struct pll_div)
+		{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
+		break;
  	case 666 * MHz:
  		dpll_cfg = (struct pll_div)
  		{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};

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#139 lore raw

PATCH v3 49/57 ram: rk3399: Add LPPDDR4-400 timings inc

In reply to a message not in the archive

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 .../ram/rockchip/sdram-rk3399-lpddr4-400.inc  | 1570 +++++++++++++++++
 1 file changed, 1570 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc
drivers/ram/rockchip/sdram-rk3399-lpddr4-400.inc new file +1570 -0
new file mode 100644
index 0000000000..c50a03d9dd
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+	{
+		{
+			{
+				.rank = 0x2,
+				.col = 0xA,
+				.bk = 0x3,
+				.bw = 0x2,
+				.dbw = 0x1,
+				.row_3_4 = 0x0,
+				.cs0_row = 0xF,
+				.cs1_row = 0xF,
+				.ddrconfig = 1,
+			},
+			{
+				.ddrtiminga0 = 0x80241d22,
+				.ddrtimingb0 = 0x15050f08,
+				.ddrtimingc0 = {
+					0x00000602,
+				},
+				.devtodev0 = 0x00002122,
+				.ddrmode = {
+					0x0000004c,
+				},
+				.agingx0 = 0x00000000,
+			}
+		},
+		{
+			{
+				.rank = 0x2,
+				.col = 0xA,
+				.bk = 0x3,
+				.bw = 0x2,
+				.dbw = 0x1,
+				.row_3_4 = 0x0,
+				.cs0_row = 0xF,
+				.cs1_row = 0xF,
+				.ddrconfig = 1,
+			},
+			{
+				.ddrtiminga0 = 0x80241d22,
+				.ddrtimingb0 = 0x15050f08,
+				.ddrtimingc0 = {
+					0x00000602,
+				},
+				.devtodev0 = 0x00002122,
+				.ddrmode = {
+					0x0000004c,
+				},
+				.agingx0 = 0x00000000,
+			}
+		}
+	},
+	{
+		.ddr_freq = 400 * MHz,
+		.dramtype = LPDDR4,
+		.num_channels = 2,
+		.stride = 13,
+		.odt = 1,
+	},
+	{
+		{
+			0x00000b00,	/* DENALI_CTL_00_DATA */
+			0x00000000,	/* DENALI_CTL_01_DATA */
+			0x00000000,	/* DENALI_CTL_02_DATA */
+			0x00000000,	/* DENALI_CTL_03_DATA */
+			0x00000000,	/* DENALI_CTL_04_DATA */
+			0x00013880,	/* DENALI_CTL_05_DATA */
+			0x000c3500,	/* DENALI_CTL_06_DATA */
+			0x00000005,	/* DENALI_CTL_07_DATA */
+			0x00000320,	/* DENALI_CTL_08_DATA */
+			0x00027100,	/* DENALI_CTL_09_DATA */
+			0x00186a00,	/* DENALI_CTL_10_DATA */
+			0x00000005,	/* DENALI_CTL_11_DATA */
+			0x00000640,	/* DENALI_CTL_12_DATA */
+			0x00002710,	/* DENALI_CTL_13_DATA */
+			0x000186a0,	/* DENALI_CTL_14_DATA */
+			0x00000005,	/* DENALI_CTL_15_DATA */
+			0x01000064,	/* DENALI_CTL_16_DATA */
+			0x00000000,	/* DENALI_CTL_17_DATA */
+			0x02020101,	/* DENALI_CTL_18_DATA */
+			0x00000102,	/* DENALI_CTL_19_DATA */
+			0x00000050,	/* DENALI_CTL_20_DATA */
+			0x000000c8,	/* DENALI_CTL_21_DATA */
+			0x00000000,	/* DENALI_CTL_22_DATA */
+			0x06140000,	/* DENALI_CTL_23_DATA */
+			0x00081c00,	/* DENALI_CTL_24_DATA */
+			0x0400040c,	/* DENALI_CTL_25_DATA */
+			0x19042008,	/* DENALI_CTL_26_DATA */
+			0x10080a11,	/* DENALI_CTL_27_DATA */
+			0x22310800,	/* DENALI_CTL_28_DATA */
+			0x00200f0a,	/* DENALI_CTL_29_DATA */
+			0x0a030704,	/* DENALI_CTL_30_DATA */
+			0x08000204,	/* DENALI_CTL_31_DATA */
+			0x00000a0a,	/* DENALI_CTL_32_DATA */
+			0x04006db0,	/* DENALI_CTL_33_DATA */
+			0x0a0a0804,	/* DENALI_CTL_34_DATA */
+			0x0600db60,	/* DENALI_CTL_35_DATA */
+			0x0a0a0806,	/* DENALI_CTL_36_DATA */
+			0x04000db6,	/* DENALI_CTL_37_DATA */
+			0x02030404,	/* DENALI_CTL_38_DATA */
+			0x0f0a0800,	/* DENALI_CTL_39_DATA */
+			0x08040411,	/* DENALI_CTL_40_DATA */
+			0x1400640a,	/* DENALI_CTL_41_DATA */
+			0x02010a0a,	/* DENALI_CTL_42_DATA */
+			0x00010001,	/* DENALI_CTL_43_DATA */
+			0x04082012,	/* DENALI_CTL_44_DATA */
+			0x00041109,	/* DENALI_CTL_45_DATA */
+			0x00000000,	/* DENALI_CTL_46_DATA */
+			0x03010000,	/* DENALI_CTL_47_DATA */
+			0x06100034,	/* DENALI_CTL_48_DATA */
+			0x0c280068,	/* DENALI_CTL_49_DATA */
+			0x00bb0007,	/* DENALI_CTL_50_DATA */
+			0x00000000,	/* DENALI_CTL_51_DATA */
+			0x00060003,	/* DENALI_CTL_52_DATA */
+			0x000a0003,	/* DENALI_CTL_53_DATA */
+			0x000a0014,	/* DENALI_CTL_54_DATA */
+			0x01000000,	/* DENALI_CTL_55_DATA */
+			0x030a0000,	/* DENALI_CTL_56_DATA */
+			0x0c000002,	/* DENALI_CTL_57_DATA */
+			0x00000103,	/* DENALI_CTL_58_DATA */
+			0x0003030a,	/* DENALI_CTL_59_DATA */
+			0x00060037,	/* DENALI_CTL_60_DATA */
+			0x0003006e,	/* DENALI_CTL_61_DATA */
+			0x05050007,	/* DENALI_CTL_62_DATA */
+			0x03020605,	/* DENALI_CTL_63_DATA */
+			0x06050301,	/* DENALI_CTL_64_DATA */
+			0x06020c05,	/* DENALI_CTL_65_DATA */
+			0x05050302,	/* DENALI_CTL_66_DATA */
+			0x03020305,	/* DENALI_CTL_67_DATA */
+			0x00000301,	/* DENALI_CTL_68_DATA */
+			0x00000301,	/* DENALI_CTL_69_DATA */
+			0x00000001,	/* DENALI_CTL_70_DATA */
+			0x00000000,	/* DENALI_CTL_71_DATA */
+			0x00000000,	/* DENALI_CTL_72_DATA */
+			0x01000000,	/* DENALI_CTL_73_DATA */
+			0x80104002,	/* DENALI_CTL_74_DATA */
+			0x00040003,	/* DENALI_CTL_75_DATA */
+			0x00040005,	/* DENALI_CTL_76_DATA */
+			0x00030000,	/* DENALI_CTL_77_DATA */
+			0x00050004,	/* DENALI_CTL_78_DATA */
+			0x00000004,	/* DENALI_CTL_79_DATA */
+			0x00040003,	/* DENALI_CTL_80_DATA */
+			0x00040005,	/* DENALI_CTL_81_DATA */
+			0x18400000,	/* DENALI_CTL_82_DATA */
+			0x00000c20,	/* DENALI_CTL_83_DATA */
+			0x185030a0,	/* DENALI_CTL_84_DATA */
+			0x02ec0000,	/* DENALI_CTL_85_DATA */
+			0x00000176,	/* DENALI_CTL_86_DATA */
+			0x00000000,	/* DENALI_CTL_87_DATA */
+			0x00000000,	/* DENALI_CTL_88_DATA */
+			0x00000000,	/* DENALI_CTL_89_DATA */
+			0x00000000,	/* DENALI_CTL_90_DATA */
+			0x00000000,	/* DENALI_CTL_91_DATA */
+			0x06030300,	/* DENALI_CTL_92_DATA */
+			0x00030303,	/* DENALI_CTL_93_DATA */
+			0x02030200,	/* DENALI_CTL_94_DATA */
+			0x00040703,	/* DENALI_CTL_95_DATA */
+			0x03020302,	/* DENALI_CTL_96_DATA */
+			0x02000407,	/* DENALI_CTL_97_DATA */
+			0x07030203,	/* DENALI_CTL_98_DATA */
+			0x00030f04,	/* DENALI_CTL_99_DATA */
+			0x00070004,	/* DENALI_CTL_100_DATA */
+			0x00000000,	/* DENALI_CTL_101_DATA */
+			0x00000000,	/* DENALI_CTL_102_DATA */
+			0x00000000,	/* DENALI_CTL_103_DATA */
+			0x00000000,	/* DENALI_CTL_104_DATA */
+			0x00000000,	/* DENALI_CTL_105_DATA */
+			0x00000000,	/* DENALI_CTL_106_DATA */
+			0x00000000,	/* DENALI_CTL_107_DATA */
+			0x00010000,	/* DENALI_CTL_108_DATA */
+			0x20040020,	/* DENALI_CTL_109_DATA */
+			0x00200400,	/* DENALI_CTL_110_DATA */
+			0x01000400,	/* DENALI_CTL_111_DATA */
+			0x00000b80,	/* DENALI_CTL_112_DATA */
+			0x00000000,	/* DENALI_CTL_113_DATA */
+			0x00000001,	/* DENALI_CTL_114_DATA */
+			0x00000002,	/* DENALI_CTL_115_DATA */
+			0x0000000e,	/* DENALI_CTL_116_DATA */
+			0x00000000,	/* DENALI_CTL_117_DATA */
+			0x00000000,	/* DENALI_CTL_118_DATA */
+			0x00000000,	/* DENALI_CTL_119_DATA */
+			0x00000000,	/* DENALI_CTL_120_DATA */
+			0x00000000,	/* DENALI_CTL_121_DATA */
+			0x00500000,	/* DENALI_CTL_122_DATA */
+			0x00640028,	/* DENALI_CTL_123_DATA */
+			0x00640404,	/* DENALI_CTL_124_DATA */
+			0x005000a0,	/* DENALI_CTL_125_DATA */
+			0x060600c8,	/* DENALI_CTL_126_DATA */
+			0x000a00c8,	/* DENALI_CTL_127_DATA */
+			0x000d0005,	/* DENALI_CTL_128_DATA */
+			0x000d0404,	/* DENALI_CTL_129_DATA */
+			0x00000000,	/* DENALI_CTL_130_DATA */
+			0x00000000,	/* DENALI_CTL_131_DATA */
+			0x00000000,	/* DENALI_CTL_132_DATA */
+			0x001400a3,	/* DENALI_CTL_133_DATA */
+			0x00e30009,	/* DENALI_CTL_134_DATA */
+			0x00120024,	/* DENALI_CTL_135_DATA */
+			0x00040063,	/* DENALI_CTL_136_DATA */
+			0x00000000,	/* DENALI_CTL_137_DATA */
+			0x00310031,	/* DENALI_CTL_138_DATA */
+			0x00000031,	/* DENALI_CTL_139_DATA */
+			0x004d0000,	/* DENALI_CTL_140_DATA */
+			0x004d004d,	/* DENALI_CTL_141_DATA */
+			0x004d0000,	/* DENALI_CTL_142_DATA */
+			0x004d004d,	/* DENALI_CTL_143_DATA */
+			0x00010101,	/* DENALI_CTL_144_DATA */
+			0x00000000,	/* DENALI_CTL_145_DATA */
+			0x00000000,	/* DENALI_CTL_146_DATA */
+			0x001400a3,	/* DENALI_CTL_147_DATA */
+			0x00e30009,	/* DENALI_CTL_148_DATA */
+			0x00120024,	/* DENALI_CTL_149_DATA */
+			0x00040063,	/* DENALI_CTL_150_DATA */
+			0x00000000,	/* DENALI_CTL_151_DATA */
+			0x00310031,	/* DENALI_CTL_152_DATA */
+			0x00000031,	/* DENALI_CTL_153_DATA */
+			0x004d0000,	/* DENALI_CTL_154_DATA */
+			0x004d004d,	/* DENALI_CTL_155_DATA */
+			0x004d0000,	/* DENALI_CTL_156_DATA */
+			0x004d004d,	/* DENALI_CTL_157_DATA */
+			0x00010101,	/* DENALI_CTL_158_DATA */
+			0x00000000,	/* DENALI_CTL_159_DATA */
+			0x00000000,	/* DENALI_CTL_160_DATA */
+			0x00000000,	/* DENALI_CTL_161_DATA */
+			0x00000001,	/* DENALI_CTL_162_DATA */
+			0x00000000,	/* DENALI_CTL_163_DATA */
+			0x18151100,	/* DENALI_CTL_164_DATA */
+			0x0000000c,	/* DENALI_CTL_165_DATA */
+			0x00000000,	/* DENALI_CTL_166_DATA */
+			0x00000000,	/* DENALI_CTL_167_DATA */
+			0x00000000,	/* DENALI_CTL_168_DATA */
+			0x00000000,	/* DENALI_CTL_169_DATA */
+			0x00000000,	/* DENALI_CTL_170_DATA */
+			0x00000000,	/* DENALI_CTL_171_DATA */
+			0x00000000,	/* DENALI_CTL_172_DATA */
+			0x00000000,	/* DENALI_CTL_173_DATA */
+			0x00000000,	/* DENALI_CTL_174_DATA */
+			0x00000000,	/* DENALI_CTL_175_DATA */
+			0x00000000,	/* DENALI_CTL_176_DATA */
+			0x00000000,	/* DENALI_CTL_177_DATA */
+			0x00000000,	/* DENALI_CTL_178_DATA */
+			0x00020003,	/* DENALI_CTL_179_DATA */
+			0x00400100,	/* DENALI_CTL_180_DATA */
+			0x000c0190,	/* DENALI_CTL_181_DATA */
+			0x01000200,	/* DENALI_CTL_182_DATA */
+			0x03200040,	/* DENALI_CTL_183_DATA */
+			0x00020018,	/* DENALI_CTL_184_DATA */
+			0x00400100,	/* DENALI_CTL_185_DATA */
+			0x00080032,	/* DENALI_CTL_186_DATA */
+			0x00140000,	/* DENALI_CTL_187_DATA */
+			0x00030028,	/* DENALI_CTL_188_DATA */
+			0x01010100,	/* DENALI_CTL_189_DATA */
+			0x02000202,	/* DENALI_CTL_190_DATA */
+			0x0b000002,	/* DENALI_CTL_191_DATA */
+			0x01000f0f,	/* DENALI_CTL_192_DATA */
+			0x00000000,	/* DENALI_CTL_193_DATA */
+			0x00000000,	/* DENALI_CTL_194_DATA */
+			0x00010003,	/* DENALI_CTL_195_DATA */
+			0x00000c03,	/* DENALI_CTL_196_DATA */
+			0x00040101,	/* DENALI_CTL_197_DATA */
+			0x04010100,	/* DENALI_CTL_198_DATA */
+			0x01000000,	/* DENALI_CTL_199_DATA */
+			0x02010000,	/* DENALI_CTL_200_DATA */
+			0x00000001,	/* DENALI_CTL_201_DATA */
+			0x00000000,	/* DENALI_CTL_202_DATA */
+			0x00000000,	/* DENALI_CTL_203_DATA */
+			0x00000000,	/* DENALI_CTL_204_DATA */
+			0x00000000,	/* DENALI_CTL_205_DATA */
+			0x00000000,	/* DENALI_CTL_206_DATA */
+			0x00000000,	/* DENALI_CTL_207_DATA */
+			0x00000000,	/* DENALI_CTL_208_DATA */
+			0x00000000,	/* DENALI_CTL_209_DATA */
+			0x00000000,	/* DENALI_CTL_210_DATA */
+			0x00010000,	/* DENALI_CTL_211_DATA */
+			0x00000001,	/* DENALI_CTL_212_DATA */
+			0x01010001,	/* DENALI_CTL_213_DATA */
+			0x05040001,	/* DENALI_CTL_214_DATA */
+			0x040a0703,	/* DENALI_CTL_215_DATA */
+			0x02080808,	/* DENALI_CTL_216_DATA */
+			0x020e000a,	/* DENALI_CTL_217_DATA */
+			0x020f010b,	/* DENALI_CTL_218_DATA */
+			0x000d0008,	/* DENALI_CTL_219_DATA */
+			0x00080b0a,	/* DENALI_CTL_220_DATA */
+			0x03000200,	/* DENALI_CTL_221_DATA */
+			0x00000100,	/* DENALI_CTL_222_DATA */
+			0x00000000,	/* DENALI_CTL_223_DATA */
+			0x00000000,	/* DENALI_CTL_224_DATA */
+			0x0d000001,	/* DENALI_CTL_225_DATA */
+			0x00000028,	/* DENALI_CTL_226_DATA */
+			0x00010000,	/* DENALI_CTL_227_DATA */
+			0x00000003,	/* DENALI_CTL_228_DATA */
+			0x00000000,	/* DENALI_CTL_229_DATA */
+			0x00000000,	/* DENALI_CTL_230_DATA */
+			0x00000000,	/* DENALI_CTL_231_DATA */
+			0x00000000,	/* DENALI_CTL_232_DATA */
+			0x00000000,	/* DENALI_CTL_233_DATA */
+			0x00000000,	/* DENALI_CTL_234_DATA */
+			0x00000000,	/* DENALI_CTL_235_DATA */
+			0x00000000,	/* DENALI_CTL_236_DATA */
+			0x00010100,	/* DENALI_CTL_237_DATA */
+			0x01000000,	/* DENALI_CTL_238_DATA */
+			0x00000001,	/* DENALI_CTL_239_DATA */
+			0x00000303,	/* DENALI_CTL_240_DATA */
+			0x00000000,	/* DENALI_CTL_241_DATA */
+			0x00000000,	/* DENALI_CTL_242_DATA */
+			0x00000000,	/* DENALI_CTL_243_DATA */
+			0x00000000,	/* DENALI_CTL_244_DATA */
+			0x00000000,	/* DENALI_CTL_245_DATA */
+			0x00000000,	/* DENALI_CTL_246_DATA */
+			0x00000000,	/* DENALI_CTL_247_DATA */
+			0x00000000,	/* DENALI_CTL_248_DATA */
+			0x00000000,	/* DENALI_CTL_249_DATA */
+			0x00000000,	/* DENALI_CTL_250_DATA */
+			0x00000000,	/* DENALI_CTL_251_DATA */
+			0x00000000,	/* DENALI_CTL_252_DATA */
+			0x00000000,	/* DENALI_CTL_253_DATA */
+			0x00000000,	/* DENALI_CTL_254_DATA */
+			0x00000000,	/* DENALI_CTL_255_DATA */
+			0x000556aa,	/* DENALI_CTL_256_DATA */
+			0x000aaaaa,	/* DENALI_CTL_257_DATA */
+			0x000aa955,	/* DENALI_CTL_258_DATA */
+			0x00055555,	/* DENALI_CTL_259_DATA */
+			0x000b3133,	/* DENALI_CTL_260_DATA */
+			0x0004cd33,	/* DENALI_CTL_261_DATA */
+			0x0004cecc,	/* DENALI_CTL_262_DATA */
+			0x000b32cc,	/* DENALI_CTL_263_DATA */
+			0x00010300,	/* DENALI_CTL_264_DATA */
+			0x03000100,	/* DENALI_CTL_265_DATA */
+			0x00000000,	/* DENALI_CTL_266_DATA */
+			0x00000000,	/* DENALI_CTL_267_DATA */
+			0x00000000,	/* DENALI_CTL_268_DATA */
+			0x00000000,	/* DENALI_CTL_269_DATA */
+			0x00000000,	/* DENALI_CTL_270_DATA */
+			0x00000000,	/* DENALI_CTL_271_DATA */
+			0x00000000,	/* DENALI_CTL_272_DATA */
+			0x00000000,	/* DENALI_CTL_273_DATA */
+			0x00ffff00,	/* DENALI_CTL_274_DATA */
+			0x1a160000,	/* DENALI_CTL_275_DATA */
+			0x08000012,	/* DENALI_CTL_276_DATA */
+			0x00000c20,	/* DENALI_CTL_277_DATA */
+			0x00000200,	/* DENALI_CTL_278_DATA */
+			0x00000200,	/* DENALI_CTL_279_DATA */
+			0x00000200,	/* DENALI_CTL_280_DATA */
+			0x00000200,	/* DENALI_CTL_281_DATA */
+			0x00000c20,	/* DENALI_CTL_282_DATA */
+			0x00007940,	/* DENALI_CTL_283_DATA */
+			0x18500409,	/* DENALI_CTL_284_DATA */
+			0x00000200,	/* DENALI_CTL_285_DATA */
+			0x00000200,	/* DENALI_CTL_286_DATA */
+			0x00000200,	/* DENALI_CTL_287_DATA */
+			0x00000200,	/* DENALI_CTL_288_DATA */
+			0x00001850,	/* DENALI_CTL_289_DATA */
+			0x0000f320,	/* DENALI_CTL_290_DATA */
+			0x0176060c,	/* DENALI_CTL_291_DATA */
+			0x00000200,	/* DENALI_CTL_292_DATA */
+			0x00000200,	/* DENALI_CTL_293_DATA */
+			0x00000200,	/* DENALI_CTL_294_DATA */
+			0x00000200,	/* DENALI_CTL_295_DATA */
+			0x00000176,	/* DENALI_CTL_296_DATA */
+			0x00000e9c,	/* DENALI_CTL_297_DATA */
+			0x02020205,	/* DENALI_CTL_298_DATA */
+			0x03030202,	/* DENALI_CTL_299_DATA */
+			0x00000018,	/* DENALI_CTL_300_DATA */
+			0x00000000,	/* DENALI_CTL_301_DATA */
+			0x00000000,	/* DENALI_CTL_302_DATA */
+			0x00001403,	/* DENALI_CTL_303_DATA */
+			0x00000000,	/* DENALI_CTL_304_DATA */
+			0x00000000,	/* DENALI_CTL_305_DATA */
+			0x00000000,	/* DENALI_CTL_306_DATA */
+			0x00030000,	/* DENALI_CTL_307_DATA */
+			0x000a001c,	/* DENALI_CTL_308_DATA */
+			0x000e0020,	/* DENALI_CTL_309_DATA */
+			0x00060018,	/* DENALI_CTL_310_DATA */
+			0x00000000,	/* DENALI_CTL_311_DATA */
+			0x00000000,	/* DENALI_CTL_312_DATA */
+			0x02000000,	/* DENALI_CTL_313_DATA */
+			0x00090305,	/* DENALI_CTL_314_DATA */
+			0x00050101,	/* DENALI_CTL_315_DATA */
+			0x00000000,	/* DENALI_CTL_316_DATA */
+			0x00000000,	/* DENALI_CTL_317_DATA */
+			0x00000000,	/* DENALI_CTL_318_DATA */
+			0x00000000,	/* DENALI_CTL_319_DATA */
+			0x00000000,	/* DENALI_CTL_320_DATA */
+			0x00000000,	/* DENALI_CTL_321_DATA */
+			0x00000000,	/* DENALI_CTL_322_DATA */
+			0x00000000,	/* DENALI_CTL_323_DATA */
+			0x01000001,	/* DENALI_CTL_324_DATA */
+			0x01010101,	/* DENALI_CTL_325_DATA */
+			0x01000101,	/* DENALI_CTL_326_DATA */
+			0x01000100,	/* DENALI_CTL_327_DATA */
+			0x00010001,	/* DENALI_CTL_328_DATA */
+			0x00010002,	/* DENALI_CTL_329_DATA */
+			0x00020100,	/* DENALI_CTL_330_DATA */
+			0x00000002	/* DENALI_CTL_331_DATA */
+		}
+	},
+	{
+		{
+			0x00000b00,	/* DENALI_PI_00_DATA */
+			0x00000000,	/* DENALI_PI_01_DATA */
+			0x000002ec,	/* DENALI_PI_02_DATA */
+			0x00000176,	/* DENALI_PI_03_DATA */
+			0x000030a0,	/* DENALI_PI_04_DATA */
+			0x00001850,	/* DENALI_PI_05_DATA */
+			0x00001840,	/* DENALI_PI_06_DATA */
+			0x01760c20,	/* DENALI_PI_07_DATA */
+			0x00000200,	/* DENALI_PI_08_DATA */
+			0x00000200,	/* DENALI_PI_09_DATA */
+			0x00000200,	/* DENALI_PI_10_DATA */
+			0x00000200,	/* DENALI_PI_11_DATA */
+			0x00001850,	/* DENALI_PI_12_DATA */
+			0x00000200,	/* DENALI_PI_13_DATA */
+			0x00000200,	/* DENALI_PI_14_DATA */
+			0x00000200,	/* DENALI_PI_15_DATA */
+			0x00000200,	/* DENALI_PI_16_DATA */
+			0x00000c20,	/* DENALI_PI_17_DATA */
+			0x00000200,	/* DENALI_PI_18_DATA */
+			0x00000200,	/* DENALI_PI_19_DATA */
+			0x00000200,	/* DENALI_PI_20_DATA */
+			0x00000200,	/* DENALI_PI_21_DATA */
+			0x00010000,	/* DENALI_PI_22_DATA */
+			0x00000007,	/* DENALI_PI_23_DATA */
+			0x01000001,	/* DENALI_PI_24_DATA */
+			0x00000000,	/* DENALI_PI_25_DATA */
+			0x3fffffff,	/* DENALI_PI_26_DATA */
+			0x00000000,	/* DENALI_PI_27_DATA */
+			0x00000000,	/* DENALI_PI_28_DATA */
+			0x00000000,	/* DENALI_PI_29_DATA */
+			0x00000000,	/* DENALI_PI_30_DATA */
+			0x00000000,	/* DENALI_PI_31_DATA */
+			0x00000000,	/* DENALI_PI_32_DATA */
+			0x00000000,	/* DENALI_PI_33_DATA */
+			0x00000000,	/* DENALI_PI_34_DATA */
+			0x00000000,	/* DENALI_PI_35_DATA */
+			0x00000000,	/* DENALI_PI_36_DATA */
+			0x00000000,	/* DENALI_PI_37_DATA */
+			0x00000000,	/* DENALI_PI_38_DATA */
+			0x00000000,	/* DENALI_PI_39_DATA */
+			0x00000000,	/* DENALI_PI_40_DATA */
+			0x0f000101,	/* DENALI_PI_41_DATA */
+			0x082b3223,	/* DENALI_PI_42_DATA */
+			0x080c0004,	/* DENALI_PI_43_DATA */
+			0x00061c00,	/* DENALI_PI_44_DATA */
+			0x00000214,	/* DENALI_PI_45_DATA */
+			0x00bb0007,	/* DENALI_PI_46_DATA */
+			0x0c280068,	/* DENALI_PI_47_DATA */
+			0x06100034,	/* DENALI_PI_48_DATA */
+			0x00000500,	/* DENALI_PI_49_DATA */
+			0x00000000,	/* DENALI_PI_50_DATA */
+			0x00000000,	/* DENALI_PI_51_DATA */
+			0x00000000,	/* DENALI_PI_52_DATA */
+			0x00000000,	/* DENALI_PI_53_DATA */
+			0x00000000,	/* DENALI_PI_54_DATA */
+			0x00000000,	/* DENALI_PI_55_DATA */
+			0x00000000,	/* DENALI_PI_56_DATA */
+			0x00000000,	/* DENALI_PI_57_DATA */
+			0x04040100,	/* DENALI_PI_58_DATA */
+			0x0a000004,	/* DENALI_PI_59_DATA */
+			0x00000128,	/* DENALI_PI_60_DATA */
+			0x00000000,	/* DENALI_PI_61_DATA */
+			0x0003000f,	/* DENALI_PI_62_DATA */
+			0x00000018,	/* DENALI_PI_63_DATA */
+			0x00000000,	/* DENALI_PI_64_DATA */
+			0x00000000,	/* DENALI_PI_65_DATA */
+			0x00060002,	/* DENALI_PI_66_DATA */
+			0x00010001,	/* DENALI_PI_67_DATA */
+			0x00000101,	/* DENALI_PI_68_DATA */
+			0x00020001,	/* DENALI_PI_69_DATA */
+			0x00080004,	/* DENALI_PI_70_DATA */
+			0x00000000,	/* DENALI_PI_71_DATA */
+			0x05030000,	/* DENALI_PI_72_DATA */
+			0x070a0404,	/* DENALI_PI_73_DATA */
+			0x00000000,	/* DENALI_PI_74_DATA */
+			0x00000000,	/* DENALI_PI_75_DATA */
+			0x00000000,	/* DENALI_PI_76_DATA */
+			0x000f0f00,	/* DENALI_PI_77_DATA */
+			0x0000001e,	/* DENALI_PI_78_DATA */
+			0x00000000,	/* DENALI_PI_79_DATA */
+			0x01010300,	/* DENALI_PI_80_DATA */
+			0x00000000,	/* DENALI_PI_81_DATA */
+			0x00000000,	/* DENALI_PI_82_DATA */
+			0x01000000,	/* DENALI_PI_83_DATA */
+			0x00000101,	/* DENALI_PI_84_DATA */
+			0x55555a5a,	/* DENALI_PI_85_DATA */
+			0x55555a5a,	/* DENALI_PI_86_DATA */
+			0x55555a5a,	/* DENALI_PI_87_DATA */
+			0x55555a5a,	/* DENALI_PI_88_DATA */
+			0x0c050001,	/* DENALI_PI_89_DATA */
+			0x06020009,	/* DENALI_PI_90_DATA */
+			0x00010004,	/* DENALI_PI_91_DATA */
+			0x00000203,	/* DENALI_PI_92_DATA */
+			0x00030000,	/* DENALI_PI_93_DATA */
+			0x170f0000,	/* DENALI_PI_94_DATA */
+			0x00060018,	/* DENALI_PI_95_DATA */
+			0x000e0020,	/* DENALI_PI_96_DATA */
+			0x000a001c,	/* DENALI_PI_97_DATA */
+			0x00000000,	/* DENALI_PI_98_DATA */
+			0x00000000,	/* DENALI_PI_99_DATA */
+			0x00000100,	/* DENALI_PI_100_DATA */
+			0x140a0000,	/* DENALI_PI_101_DATA */
+			0x000d010a,	/* DENALI_PI_102_DATA */
+			0x0100c802,	/* DENALI_PI_103_DATA */
+			0x010a0064,	/* DENALI_PI_104_DATA */
+			0x000e0100,	/* DENALI_PI_105_DATA */
+			0x0100000e,	/* DENALI_PI_106_DATA */
+			0x00c900c9,	/* DENALI_PI_107_DATA */
+			0x00650100,	/* DENALI_PI_108_DATA */
+			0x1e1a0065,	/* DENALI_PI_109_DATA */
+			0x10010204,	/* DENALI_PI_110_DATA */
+			0x06070605,	/* DENALI_PI_111_DATA */
+			0x20000202,	/* DENALI_PI_112_DATA */
+			0x00201000,	/* DENALI_PI_113_DATA */
+			0x00201000,	/* DENALI_PI_114_DATA */
+			0x04041000,	/* DENALI_PI_115_DATA */
+			0x10020100,	/* DENALI_PI_116_DATA */
+			0x0003010c,	/* DENALI_PI_117_DATA */
+			0x004b004a,	/* DENALI_PI_118_DATA */
+			0x1a0f0000,	/* DENALI_PI_119_DATA */
+			0x0102041e,	/* DENALI_PI_120_DATA */
+			0x34000000,	/* DENALI_PI_121_DATA */
+			0x00000000,	/* DENALI_PI_122_DATA */
+			0x00000000,	/* DENALI_PI_123_DATA */
+			0x00010000,	/* DENALI_PI_124_DATA */
+			0x00000400,	/* DENALI_PI_125_DATA */
+			0x00310000,	/* DENALI_PI_126_DATA */
+			0x004d4d00,	/* DENALI_PI_127_DATA */
+			0x00120024,	/* DENALI_PI_128_DATA */
+			0x4d000031,	/* DENALI_PI_129_DATA */
+			0x0000144d,	/* DENALI_PI_130_DATA */
+			0x00310009,	/* DENALI_PI_131_DATA */
+			0x004d4d00,	/* DENALI_PI_132_DATA */
+			0x00000004,	/* DENALI_PI_133_DATA */
+			0x4d000031,	/* DENALI_PI_134_DATA */
+			0x0000244d,	/* DENALI_PI_135_DATA */
+			0x00310012,	/* DENALI_PI_136_DATA */
+			0x004d4d00,	/* DENALI_PI_137_DATA */
+			0x00090014,	/* DENALI_PI_138_DATA */
+			0x4d000031,	/* DENALI_PI_139_DATA */
+			0x0004004d,	/* DENALI_PI_140_DATA */
+			0x00310000,	/* DENALI_PI_141_DATA */
+			0x004d4d00,	/* DENALI_PI_142_DATA */
+			0x00120024,	/* DENALI_PI_143_DATA */
+			0x4d000031,	/* DENALI_PI_144_DATA */
+			0x0000144d,	/* DENALI_PI_145_DATA */
+			0x00310009,	/* DENALI_PI_146_DATA */
+			0x004d4d00,	/* DENALI_PI_147_DATA */
+			0x00000004,	/* DENALI_PI_148_DATA */
+			0x4d000031,	/* DENALI_PI_149_DATA */
+			0x0000244d,	/* DENALI_PI_150_DATA */
+			0x00310012,	/* DENALI_PI_151_DATA */
+			0x004d4d00,	/* DENALI_PI_152_DATA */
+			0x00090014,	/* DENALI_PI_153_DATA */
+			0x4d000031,	/* DENALI_PI_154_DATA */
+			0x0200004d,	/* DENALI_PI_155_DATA */
+			0x00c8000d,	/* DENALI_PI_156_DATA */
+			0x08080064,	/* DENALI_PI_157_DATA */
+			0x040a0404,	/* DENALI_PI_158_DATA */
+			0x03000d92,	/* DENALI_PI_159_DATA */
+			0x010a2001,	/* DENALI_PI_160_DATA */
+			0x0f11080a,	/* DENALI_PI_161_DATA */
+			0x0000110a,	/* DENALI_PI_162_DATA */
+			0x2200d92e,	/* DENALI_PI_163_DATA */
+			0x080c2003,	/* DENALI_PI_164_DATA */
+			0x0809080a,	/* DENALI_PI_165_DATA */
+			0x00000a0a,	/* DENALI_PI_166_DATA */
+			0x11006c97,	/* DENALI_PI_167_DATA */
+			0x040a2002,	/* DENALI_PI_168_DATA */
+			0x0200020a,	/* DENALI_PI_169_DATA */
+			0x02000200,	/* DENALI_PI_170_DATA */
+			0x02000200,	/* DENALI_PI_171_DATA */
+			0x02000200,	/* DENALI_PI_172_DATA */
+			0x02000200,	/* DENALI_PI_173_DATA */
+			0x00000000,	/* DENALI_PI_174_DATA */
+			0x00000000,	/* DENALI_PI_175_DATA */
+			0x00000000,	/* DENALI_PI_176_DATA */
+			0x00000000,	/* DENALI_PI_177_DATA */
+			0x00000000,	/* DENALI_PI_178_DATA */
+			0x00000000,	/* DENALI_PI_179_DATA */
+			0x00000000,	/* DENALI_PI_180_DATA */
+			0x00000000,	/* DENALI_PI_181_DATA */
+			0x00000000,	/* DENALI_PI_182_DATA */
+			0x00000000,	/* DENALI_PI_183_DATA */
+			0x00000000,	/* DENALI_PI_184_DATA */
+			0x00000000,	/* DENALI_PI_185_DATA */
+			0x01000400,	/* DENALI_PI_186_DATA */
+			0x00017600,	/* DENALI_PI_187_DATA */
+			0x00000e9c,	/* DENALI_PI_188_DATA */
+			0x00001850,	/* DENALI_PI_189_DATA */
+			0x0000f320,	/* DENALI_PI_190_DATA */
+			0x00000c20,	/* DENALI_PI_191_DATA */
+			0x00007940,	/* DENALI_PI_192_DATA */
+			0x08000000,	/* DENALI_PI_193_DATA */
+			0x00000100,	/* DENALI_PI_194_DATA */
+			0x00000000,	/* DENALI_PI_195_DATA */
+			0x00000000,	/* DENALI_PI_196_DATA */
+			0x00000000,	/* DENALI_PI_197_DATA */
+			0x00000000,	/* DENALI_PI_198_DATA */
+			0x00000002	/* DENALI_PI_199_DATA */
+		}
+	},
+	{
+		{
+			0x76543210,	/* DENALI_PHY_00_DATA */
+			0x0004f008,	/* DENALI_PHY_01_DATA */
+			0x00020119,	/* DENALI_PHY_02_DATA */
+			0x00000000,	/* DENALI_PHY_03_DATA */
+			0x00000000,	/* DENALI_PHY_04_DATA */
+			0x00010000,	/* DENALI_PHY_05_DATA */
+			0x01665555,	/* DENALI_PHY_06_DATA */
+			0x03665555,	/* DENALI_PHY_07_DATA */
+			0x00010f00,	/* DENALI_PHY_08_DATA */
+			0x04000100,	/* DENALI_PHY_09_DATA */
+			0x00000001,	/* DENALI_PHY_10_DATA */
+			0x00170180,	/* DENALI_PHY_11_DATA */
+			0x00cc0201,	/* DENALI_PHY_12_DATA */
+			0x00030066,	/* DENALI_PHY_13_DATA */
+			0x00000000,	/* DENALI_PHY_14_DATA */
+			0x00000000,	/* DENALI_PHY_15_DATA */
+			0x00000000,	/* DENALI_PHY_16_DATA */
+			0x00000000,	/* DENALI_PHY_17_DATA */
+			0x00000000,	/* DENALI_PHY_18_DATA */
+			0x00000000,	/* DENALI_PHY_19_DATA */
+			0x00000000,	/* DENALI_PHY_20_DATA */
+			0x00000000,	/* DENALI_PHY_21_DATA */
+			0x04080000,	/* DENALI_PHY_22_DATA */
+			0x04080400,	/* DENALI_PHY_23_DATA */
+			0x30000000,	/* DENALI_PHY_24_DATA */
+			0x0c00c007,	/* DENALI_PHY_25_DATA */
+			0x00000100,	/* DENALI_PHY_26_DATA */
+			0x00000000,	/* DENALI_PHY_27_DATA */
+			0xfd02fe01,	/* DENALI_PHY_28_DATA */
+			0xf708fb04,	/* DENALI_PHY_29_DATA */
+			0xdf20ef10,	/* DENALI_PHY_30_DATA */
+			0x7f80bf40,	/* DENALI_PHY_31_DATA */
+			0x0001aaaa,	/* DENALI_PHY_32_DATA */
+			0x00000000,	/* DENALI_PHY_33_DATA */
+			0x00000000,	/* DENALI_PHY_34_DATA */
+			0x00000000,	/* DENALI_PHY_35_DATA */
+			0x00000000,	/* DENALI_PHY_36_DATA */
+			0x00000000,	/* DENALI_PHY_37_DATA */
+			0x00000000,	/* DENALI_PHY_38_DATA */
+			0x00000000,	/* DENALI_PHY_39_DATA */
+			0x00000000,	/* DENALI_PHY_40_DATA */
+			0x00000000,	/* DENALI_PHY_41_DATA */
+			0x00000000,	/* DENALI_PHY_42_DATA */
+			0x00000000,	/* DENALI_PHY_43_DATA */
+			0x00000000,	/* DENALI_PHY_44_DATA */
+			0x00000000,	/* DENALI_PHY_45_DATA */
+			0x00000000,	/* DENALI_PHY_46_DATA */
+			0x00000000,	/* DENALI_PHY_47_DATA */
+			0x00000000,	/* DENALI_PHY_48_DATA */
+			0x00000000,	/* DENALI_PHY_49_DATA */
+			0x00000000,	/* DENALI_PHY_50_DATA */
+			0x00000000,	/* DENALI_PHY_51_DATA */
+			0x00200000,	/* DENALI_PHY_52_DATA */
+			0x00000000,	/* DENALI_PHY_53_DATA */
+			0x00000000,	/* DENALI_PHY_54_DATA */
+			0x00000000,	/* DENALI_PHY_55_DATA */
+			0x00000000,	/* DENALI_PHY_56_DATA */
+			0x00000000,	/* DENALI_PHY_57_DATA */
+			0x00000000,	/* DENALI_PHY_58_DATA */
+			0x02800280,	/* DENALI_PHY_59_DATA */
+			0x02800280,	/* DENALI_PHY_60_DATA */
+			0x02800280,	/* DENALI_PHY_61_DATA */
+			0x02800280,	/* DENALI_PHY_62_DATA */
+			0x00000280,	/* DENALI_PHY_63_DATA */
+			0x00000000,	/* DENALI_PHY_64_DATA */
+			0x00000000,	/* DENALI_PHY_65_DATA */
+			0x00000000,	/* DENALI_PHY_66_DATA */
+			0x00000000,	/* DENALI_PHY_67_DATA */
+			0x00800000,	/* DENALI_PHY_68_DATA */
+			0x00800080,	/* DENALI_PHY_69_DATA */
+			0x00800080,	/* DENALI_PHY_70_DATA */
+			0x00800080,	/* DENALI_PHY_71_DATA */
+			0x00800080,	/* DENALI_PHY_72_DATA */
+			0x00800080,	/* DENALI_PHY_73_DATA */
+			0x00800080,	/* DENALI_PHY_74_DATA */
+			0x00800080,	/* DENALI_PHY_75_DATA */
+			0x00800080,	/* DENALI_PHY_76_DATA */
+			0x01190080,	/* DENALI_PHY_77_DATA */
+			0x00000001,	/* DENALI_PHY_78_DATA */
+			0x00000000,	/* DENALI_PHY_79_DATA */
+			0x00000000,	/* DENALI_PHY_80_DATA */
+			0x00000200,	/* DENALI_PHY_81_DATA */
+			0x00000000,	/* DENALI_PHY_82_DATA */
+			0x51315152,	/* DENALI_PHY_83_DATA */
+			0xc0003150,	/* DENALI_PHY_84_DATA */
+			0x010000c0,	/* DENALI_PHY_85_DATA */
+			0x00100000,	/* DENALI_PHY_86_DATA */
+			0x07044204,	/* DENALI_PHY_87_DATA */
+			0x000f0c18,	/* DENALI_PHY_88_DATA */
+			0x01000140,	/* DENALI_PHY_89_DATA */
+			0x00000c10,	/* DENALI_PHY_90_DATA */
+			0x00000000,	/* DENALI_PHY_91_DATA */
+			0x00000000,	/* DENALI_PHY_92_DATA */
+			0x00000000,	/* DENALI_PHY_93_DATA */
+			0x00000000,	/* DENALI_PHY_94_DATA */
+			0x00000000,	/* DENALI_PHY_95_DATA */
+			0x00000000,	/* DENALI_PHY_96_DATA */
+			0x00000000,	/* DENALI_PHY_97_DATA */
+			0x00000000,	/* DENALI_PHY_98_DATA */
+			0x00000000,	/* DENALI_PHY_99_DATA */
+			0x00000000,	/* DENALI_PHY_100_DATA */
+			0x00000000,	/* DENALI_PHY_101_DATA */
+			0x00000000,	/* DENALI_PHY_102_DATA */
+			0x00000000,	/* DENALI_PHY_103_DATA */
+			0x00000000,	/* DENALI_PHY_104_DATA */
+			0x00000000,	/* DENALI_PHY_105_DATA */
+			0x00000000,	/* DENALI_PHY_106_DATA */
+			0x00000000,	/* DENALI_PHY_107_DATA */
+			0x00000000,	/* DENALI_PHY_108_DATA */
+			0x00000000,	/* DENALI_PHY_109_DATA */
+			0x00000000,	/* DENALI_PHY_110_DATA */
+			0x00000000,	/* DENALI_PHY_111_DATA */
+			0x00000000,	/* DENALI_PHY_112_DATA */
+			0x00000000,	/* DENALI_PHY_113_DATA */
+			0x00000000,	/* DENALI_PHY_114_DATA */
+			0x00000000,	/* DENALI_PHY_115_DATA */
+			0x00000000,	/* DENALI_PHY_116_DATA */
+			0x00000000,	/* DENALI_PHY_117_DATA */
+			0x00000000,	/* DENALI_PHY_118_DATA */
+			0x00000000,	/* DENALI_PHY_119_DATA */
+			0x00000000,	/* DENALI_PHY_120_DATA */
+			0x00000000,	/* DENALI_PHY_121_DATA */
+			0x00000000,	/* DENALI_PHY_122_DATA */
+			0x00000000,	/* DENALI_PHY_123_DATA */
+			0x00000000,	/* DENALI_PHY_124_DATA */
+			0x00000000,	/* DENALI_PHY_125_DATA */
+			0x00000000,	/* DENALI_PHY_126_DATA */
+			0x00000000,	/* DENALI_PHY_127_DATA */
+			0x76543210,	/* DENALI_PHY_128_DATA */
+			0x0004f008,	/* DENALI_PHY_129_DATA */
+			0x00020119,	/* DENALI_PHY_130_DATA */
+			0x00000000,	/* DENALI_PHY_131_DATA */
+			0x00000000,	/* DENALI_PHY_132_DATA */
+			0x00010000,	/* DENALI_PHY_133_DATA */
+			0x01665555,	/* DENALI_PHY_134_DATA */
+			0x03665555,	/* DENALI_PHY_135_DATA */
+			0x00010f00,	/* DENALI_PHY_136_DATA */
+			0x04000100,	/* DENALI_PHY_137_DATA */
+			0x00000001,	/* DENALI_PHY_138_DATA */
+			0x00170180,	/* DENALI_PHY_139_DATA */
+			0x00cc0201,	/* DENALI_PHY_140_DATA */
+			0x00030066,	/* DENALI_PHY_141_DATA */
+			0x00000000,	/* DENALI_PHY_142_DATA */
+			0x00000000,	/* DENALI_PHY_143_DATA */
+			0x00000000,	/* DENALI_PHY_144_DATA */
+			0x00000000,	/* DENALI_PHY_145_DATA */
+			0x00000000,	/* DENALI_PHY_146_DATA */
+			0x00000000,	/* DENALI_PHY_147_DATA */
+			0x00000000,	/* DENALI_PHY_148_DATA */
+			0x00000000,	/* DENALI_PHY_149_DATA */
+			0x04080000,	/* DENALI_PHY_150_DATA */
+			0x04080400,	/* DENALI_PHY_151_DATA */
+			0x30000000,	/* DENALI_PHY_152_DATA */
+			0x0c00c007,	/* DENALI_PHY_153_DATA */
+			0x00000100,	/* DENALI_PHY_154_DATA */
+			0x00000000,	/* DENALI_PHY_155_DATA */
+			0xfd02fe01,	/* DENALI_PHY_156_DATA */
+			0xf708fb04,	/* DENALI_PHY_157_DATA */
+			0xdf20ef10,	/* DENALI_PHY_158_DATA */
+			0x7f80bf40,	/* DENALI_PHY_159_DATA */
+			0x0000aaaa,	/* DENALI_PHY_160_DATA */
+			0x00000000,	/* DENALI_PHY_161_DATA */
+			0x00000000,	/* DENALI_PHY_162_DATA */
+			0x00000000,	/* DENALI_PHY_163_DATA */
+			0x00000000,	/* DENALI_PHY_164_DATA */
+			0x00000000,	/* DENALI_PHY_165_DATA */
+			0x00000000,	/* DENALI_PHY_166_DATA */
+			0x00000000,	/* DENALI_PHY_167_DATA */
+			0x00000000,	/* DENALI_PHY_168_DATA */
+			0x00000000,	/* DENALI_PHY_169_DATA */
+			0x00000000,	/* DENALI_PHY_170_DATA */
+			0x00000000,	/* DENALI_PHY_171_DATA */
+			0x00000000,	/* DENALI_PHY_172_DATA */
+			0x00000000,	/* DENALI_PHY_173_DATA */
+			0x00000000,	/* DENALI_PHY_174_DATA */
+			0x00000000,	/* DENALI_PHY_175_DATA */
+			0x00000000,	/* DENALI_PHY_176_DATA */
+			0x00000000,	/* DENALI_PHY_177_DATA */
+			0x00000000,	/* DENALI_PHY_178_DATA */
+			0x00000000,	/* DENALI_PHY_179_DATA */
+			0x00200000,	/* DENALI_PHY_180_DATA */
+			0x00000000,	/* DENALI_PHY_181_DATA */
+			0x00000000,	/* DENALI_PHY_182_DATA */
+			0x00000000,	/* DENALI_PHY_183_DATA */
+			0x00000000,	/* DENALI_PHY_184_DATA */
+			0x00000000,	/* DENALI_PHY_185_DATA */
+			0x00000000,	/* DENALI_PHY_186_DATA */
+			0x02800280,	/* DENALI_PHY_187_DATA */
+			0x02800280,	/* DENALI_PHY_188_DATA */
+			0x02800280,	/* DENALI_PHY_189_DATA */
+			0x02800280,	/* DENALI_PHY_190_DATA */
+			0x00000280,	/* DENALI_PHY_191_DATA */
+			0x00000000,	/* DENALI_PHY_192_DATA */
+			0x00000000,	/* DENALI_PHY_193_DATA */
+			0x00000000,	/* DENALI_PHY_194_DATA */
+			0x00000000,	/* DENALI_PHY_195_DATA */
+			0x00800000,	/* DENALI_PHY_196_DATA */
+			0x00800080,	/* DENALI_PHY_197_DATA */
+			0x00800080,	/* DENALI_PHY_198_DATA */
+			0x00800080,	/* DENALI_PHY_199_DATA */
+			0x00800080,	/* DENALI_PHY_200_DATA */
+			0x00800080,	/* DENALI_PHY_201_DATA */
+			0x00800080,	/* DENALI_PHY_202_DATA */
+			0x00800080,	/* DENALI_PHY_203_DATA */
+			0x00800080,	/* DENALI_PHY_204_DATA */
+			0x01190080,	/* DENALI_PHY_205_DATA */
+			0x00000001,	/* DENALI_PHY_206_DATA */
+			0x00000000,	/* DENALI_PHY_207_DATA */
+			0x00000000,	/* DENALI_PHY_208_DATA */
+			0x00000200,	/* DENALI_PHY_209_DATA */
+			0x00000000,	/* DENALI_PHY_210_DATA */
+			0x51315152,	/* DENALI_PHY_211_DATA */
+			0xc0003150,	/* DENALI_PHY_212_DATA */
+			0x010000c0,	/* DENALI_PHY_213_DATA */
+			0x00100000,	/* DENALI_PHY_214_DATA */
+			0x07044204,	/* DENALI_PHY_215_DATA */
+			0x000f0c18,	/* DENALI_PHY_216_DATA */
+			0x01000140,	/* DENALI_PHY_217_DATA */
+			0x00000c10,	/* DENALI_PHY_218_DATA */
+			0x00000000,	/* DENALI_PHY_219_DATA */
+			0x00000000,	/* DENALI_PHY_220_DATA */
+			0x00000000,	/* DENALI_PHY_221_DATA */
+			0x00000000,	/* DENALI_PHY_222_DATA */
+			0x00000000,	/* DENALI_PHY_223_DATA */
+			0x00000000,	/* DENALI_PHY_224_DATA */
+			0x00000000,	/* DENALI_PHY_225_DATA */
+			0x00000000,	/* DENALI_PHY_226_DATA */
+			0x00000000,	/* DENALI_PHY_227_DATA */
+			0x00000000,	/* DENALI_PHY_228_DATA */
+			0x00000000,	/* DENALI_PHY_229_DATA */
+			0x00000000,	/* DENALI_PHY_230_DATA */
+			0x00000000,	/* DENALI_PHY_231_DATA */
+			0x00000000,	/* DENALI_PHY_232_DATA */
+			0x00000000,	/* DENALI_PHY_233_DATA */
+			0x00000000,	/* DENALI_PHY_234_DATA */
+			0x00000000,	/* DENALI_PHY_235_DATA */
+			0x00000000,	/* DENALI_PHY_236_DATA */
+			0x00000000,	/* DENALI_PHY_237_DATA */
+			0x00000000,	/* DENALI_PHY_238_DATA */
+			0x00000000,	/* DENALI_PHY_239_DATA */
+			0x00000000,	/* DENALI_PHY_240_DATA */
+			0x00000000,	/* DENALI_PHY_241_DATA */
+			0x00000000,	/* DENALI_PHY_242_DATA */
+			0x00000000,	/* DENALI_PHY_243_DATA */
+			0x00000000,	/* DENALI_PHY_244_DATA */
+			0x00000000,	/* DENALI_PHY_245_DATA */
+			0x00000000,	/* DENALI_PHY_246_DATA */
+			0x00000000,	/* DENALI_PHY_247_DATA */
+			0x00000000,	/* DENALI_PHY_248_DATA */
+			0x00000000,	/* DENALI_PHY_249_DATA */
+			0x00000000,	/* DENALI_PHY_250_DATA */
+			0x00000000,	/* DENALI_PHY_251_DATA */
+			0x00000000,	/* DENALI_PHY_252_DATA */
+			0x00000000,	/* DENALI_PHY_253_DATA */
+			0x00000000,	/* DENALI_PHY_254_DATA */
+			0x00000000,	/* DENALI_PHY_255_DATA */
+			0x76543210,	/* DENALI_PHY_256_DATA */
+			0x0004f008,	/* DENALI_PHY_257_DATA */
+			0x00020119,	/* DENALI_PHY_258_DATA */
+			0x00000000,	/* DENALI_PHY_259_DATA */
+			0x00000000,	/* DENALI_PHY_260_DATA */
+			0x00010000,	/* DENALI_PHY_261_DATA */
+			0x01665555,	/* DENALI_PHY_262_DATA */
+			0x03665555,	/* DENALI_PHY_263_DATA */
+			0x00010f00,	/* DENALI_PHY_264_DATA */
+			0x04000100,	/* DENALI_PHY_265_DATA */
+			0x00000001,	/* DENALI_PHY_266_DATA */
+			0x00170180,	/* DENALI_PHY_267_DATA */
+			0x00cc0201,	/* DENALI_PHY_268_DATA */
+			0x00030066,	/* DENALI_PHY_269_DATA */
+			0x00000000,	/* DENALI_PHY_270_DATA */
+			0x00000000,	/* DENALI_PHY_271_DATA */
+			0x00000000,	/* DENALI_PHY_272_DATA */
+			0x00000000,	/* DENALI_PHY_273_DATA */
+			0x00000000,	/* DENALI_PHY_274_DATA */
+			0x00000000,	/* DENALI_PHY_275_DATA */
+			0x00000000,	/* DENALI_PHY_276_DATA */
+			0x00000000,	/* DENALI_PHY_277_DATA */
+			0x04080000,	/* DENALI_PHY_278_DATA */
+			0x04080400,	/* DENALI_PHY_279_DATA */
+			0x30000000,	/* DENALI_PHY_280_DATA */
+			0x0c00c007,	/* DENALI_PHY_281_DATA */
+			0x00000100,	/* DENALI_PHY_282_DATA */
+			0x00000000,	/* DENALI_PHY_283_DATA */
+			0xfd02fe01,	/* DENALI_PHY_284_DATA */
+			0xf708fb04,	/* DENALI_PHY_285_DATA */
+			0xdf20ef10,	/* DENALI_PHY_286_DATA */
+			0x7f80bf40,	/* DENALI_PHY_287_DATA */
+			0x0001aaaa,	/* DENALI_PHY_288_DATA */
+			0x00000000,	/* DENALI_PHY_289_DATA */
+			0x00000000,	/* DENALI_PHY_290_DATA */
+			0x00000000,	/* DENALI_PHY_291_DATA */
+			0x00000000,	/* DENALI_PHY_292_DATA */
+			0x00000000,	/* DENALI_PHY_293_DATA */
+			0x00000000,	/* DENALI_PHY_294_DATA */
+			0x00000000,	/* DENALI_PHY_295_DATA */
+			0x00000000,	/* DENALI_PHY_296_DATA */
+			0x00000000,	/* DENALI_PHY_297_DATA */
+			0x00000000,	/* DENALI_PHY_298_DATA */
+			0x00000000,	/* DENALI_PHY_299_DATA */
+			0x00000000,	/* DENALI_PHY_300_DATA */
+			0x00000000,	/* DENALI_PHY_301_DATA */
+			0x00000000,	/* DENALI_PHY_302_DATA */
+			0x00000000,	/* DENALI_PHY_303_DATA */
+			0x00000000,	/* DENALI_PHY_304_DATA */
+			0x00000000,	/* DENALI_PHY_305_DATA */
+			0x00000000,	/* DENALI_PHY_306_DATA */
+			0x00000000,	/* DENALI_PHY_307_DATA */
+			0x00200000,	/* DENALI_PHY_308_DATA */
+			0x00000000,	/* DENALI_PHY_309_DATA */
+			0x00000000,	/* DENALI_PHY_310_DATA */
+			0x00000000,	/* DENALI_PHY_311_DATA */
+			0x00000000,	/* DENALI_PHY_312_DATA */
+			0x00000000,	/* DENALI_PHY_313_DATA */
+			0x00000000,	/* DENALI_PHY_314_DATA */
+			0x02800280,	/* DENALI_PHY_315_DATA */
+			0x02800280,	/* DENALI_PHY_316_DATA */
+			0x02800280,	/* DENALI_PHY_317_DATA */
+			0x02800280,	/* DENALI_PHY_318_DATA */
+			0x00000280,	/* DENALI_PHY_319_DATA */
+			0x00000000,	/* DENALI_PHY_320_DATA */
+			0x00000000,	/* DENALI_PHY_321_DATA */
+			0x00000000,	/* DENALI_PHY_322_DATA */
+			0x00000000,	/* DENALI_PHY_323_DATA */
+			0x00800000,	/* DENALI_PHY_324_DATA */
+			0x00800080,	/* DENALI_PHY_325_DATA */
+			0x00800080,	/* DENALI_PHY_326_DATA */
+			0x00800080,	/* DENALI_PHY_327_DATA */
+			0x00800080,	/* DENALI_PHY_328_DATA */
+			0x00800080,	/* DENALI_PHY_329_DATA */
+			0x00800080,	/* DENALI_PHY_330_DATA */
+			0x00800080,	/* DENALI_PHY_331_DATA */
+			0x00800080,	/* DENALI_PHY_332_DATA */
+			0x01190080,	/* DENALI_PHY_333_DATA */
+			0x00000001,	/* DENALI_PHY_334_DATA */
+			0x00000000,	/* DENALI_PHY_335_DATA */
+			0x00000000,	/* DENALI_PHY_336_DATA */
+			0x00000200,	/* DENALI_PHY_337_DATA */
+			0x00000000,	/* DENALI_PHY_338_DATA */
+			0x51315152,	/* DENALI_PHY_339_DATA */
+			0xc0003150,	/* DENALI_PHY_340_DATA */
+			0x010000c0,	/* DENALI_PHY_341_DATA */
+			0x00100000,	/* DENALI_PHY_342_DATA */
+			0x07044204,	/* DENALI_PHY_343_DATA */
+			0x000f0c18,	/* DENALI_PHY_344_DATA */
+			0x01000140,	/* DENALI_PHY_345_DATA */
+			0x00000c10,	/* DENALI_PHY_346_DATA */
+			0x00000000,	/* DENALI_PHY_347_DATA */
+			0x00000000,	/* DENALI_PHY_348_DATA */
+			0x00000000,	/* DENALI_PHY_349_DATA */
+			0x00000000,	/* DENALI_PHY_350_DATA */
+			0x00000000,	/* DENALI_PHY_351_DATA */
+			0x00000000,	/* DENALI_PHY_352_DATA */
+			0x00000000,	/* DENALI_PHY_353_DATA */
+			0x00000000,	/* DENALI_PHY_354_DATA */
+			0x00000000,	/* DENALI_PHY_355_DATA */
+			0x00000000,	/* DENALI_PHY_356_DATA */
+			0x00000000,	/* DENALI_PHY_357_DATA */
+			0x00000000,	/* DENALI_PHY_358_DATA */
+			0x00000000,	/* DENALI_PHY_359_DATA */
+			0x00000000,	/* DENALI_PHY_360_DATA */
+			0x00000000,	/* DENALI_PHY_361_DATA */
+			0x00000000,	/* DENALI_PHY_362_DATA */
+			0x00000000,	/* DENALI_PHY_363_DATA */
+			0x00000000,	/* DENALI_PHY_364_DATA */
+			0x00000000,	/* DENALI_PHY_365_DATA */
+			0x00000000,	/* DENALI_PHY_366_DATA */
+			0x00000000,	/* DENALI_PHY_367_DATA */
+			0x00000000,	/* DENALI_PHY_368_DATA */
+			0x00000000,	/* DENALI_PHY_369_DATA */
+			0x00000000,	/* DENALI_PHY_370_DATA */
+			0x00000000,	/* DENALI_PHY_371_DATA */
+			0x00000000,	/* DENALI_PHY_372_DATA */
+			0x00000000,	/* DENALI_PHY_373_DATA */
+			0x00000000,	/* DENALI_PHY_374_DATA */
+			0x00000000,	/* DENALI_PHY_375_DATA */
+			0x00000000,	/* DENALI_PHY_376_DATA */
+			0x00000000,	/* DENALI_PHY_377_DATA */
+			0x00000000,	/* DENALI_PHY_378_DATA */
+			0x00000000,	/* DENALI_PHY_379_DATA */
+			0x00000000,	/* DENALI_PHY_380_DATA */
+			0x00000000,	/* DENALI_PHY_381_DATA */
+			0x00000000,	/* DENALI_PHY_382_DATA */
+			0x00000000,	/* DENALI_PHY_383_DATA */
+			0x76543210,	/* DENALI_PHY_384_DATA */
+			0x0004f008,	/* DENALI_PHY_385_DATA */
+			0x00020119,	/* DENALI_PHY_386_DATA */
+			0x00000000,	/* DENALI_PHY_387_DATA */
+			0x00000000,	/* DENALI_PHY_388_DATA */
+			0x00010000,	/* DENALI_PHY_389_DATA */
+			0x01665555,	/* DENALI_PHY_390_DATA */
+			0x03665555,	/* DENALI_PHY_391_DATA */
+			0x00010f00,	/* DENALI_PHY_392_DATA */
+			0x04000100,	/* DENALI_PHY_393_DATA */
+			0x00000001,	/* DENALI_PHY_394_DATA */
+			0x00170180,	/* DENALI_PHY_395_DATA */
+			0x00cc0201,	/* DENALI_PHY_396_DATA */
+			0x00030066,	/* DENALI_PHY_397_DATA */
+			0x00000000,	/* DENALI_PHY_398_DATA */
+			0x00000000,	/* DENALI_PHY_399_DATA */
+			0x00000000,	/* DENALI_PHY_400_DATA */
+			0x00000000,	/* DENALI_PHY_401_DATA */
+			0x00000000,	/* DENALI_PHY_402_DATA */
+			0x00000000,	/* DENALI_PHY_403_DATA */
+			0x00000000,	/* DENALI_PHY_404_DATA */
+			0x00000000,	/* DENALI_PHY_405_DATA */
+			0x04080000,	/* DENALI_PHY_406_DATA */
+			0x04080400,	/* DENALI_PHY_407_DATA */
+			0x30000000,	/* DENALI_PHY_408_DATA */
+			0x0c00c007,	/* DENALI_PHY_409_DATA */
+			0x00000100,	/* DENALI_PHY_410_DATA */
+			0x00000000,	/* DENALI_PHY_411_DATA */
+			0xfd02fe01,	/* DENALI_PHY_412_DATA */
+			0xf708fb04,	/* DENALI_PHY_413_DATA */
+			0xdf20ef10,	/* DENALI_PHY_414_DATA */
+			0x7f80bf40,	/* DENALI_PHY_415_DATA */
+			0x0000aaaa,	/* DENALI_PHY_416_DATA */
+			0x00000000,	/* DENALI_PHY_417_DATA */
+			0x00000000,	/* DENALI_PHY_418_DATA */
+			0x00000000,	/* DENALI_PHY_419_DATA */
+			0x00000000,	/* DENALI_PHY_420_DATA */
+			0x00000000,	/* DENALI_PHY_421_DATA */
+			0x00000000,	/* DENALI_PHY_422_DATA */
+			0x00000000,	/* DENALI_PHY_423_DATA */
+			0x00000000,	/* DENALI_PHY_424_DATA */
+			0x00000000,	/* DENALI_PHY_425_DATA */
+			0x00000000,	/* DENALI_PHY_426_DATA */
+			0x00000000,	/* DENALI_PHY_427_DATA */
+			0x00000000,	/* DENALI_PHY_428_DATA */
+			0x00000000,	/* DENALI_PHY_429_DATA */
+			0x00000000,	/* DENALI_PHY_430_DATA */
+			0x00000000,	/* DENALI_PHY_431_DATA */
+			0x00000000,	/* DENALI_PHY_432_DATA */
+			0x00000000,	/* DENALI_PHY_433_DATA */
+			0x00000000,	/* DENALI_PHY_434_DATA */
+			0x00000000,	/* DENALI_PHY_435_DATA */
+			0x00200000,	/* DENALI_PHY_436_DATA */
+			0x00000000,	/* DENALI_PHY_437_DATA */
+			0x00000000,	/* DENALI_PHY_438_DATA */
+			0x00000000,	/* DENALI_PHY_439_DATA */
+			0x00000000,	/* DENALI_PHY_440_DATA */
+			0x00000000,	/* DENALI_PHY_441_DATA */
+			0x00000000,	/* DENALI_PHY_442_DATA */
+			0x02800280,	/* DENALI_PHY_443_DATA */
+			0x02800280,	/* DENALI_PHY_444_DATA */
+			0x02800280,	/* DENALI_PHY_445_DATA */
+			0x02800280,	/* DENALI_PHY_446_DATA */
+			0x00000280,	/* DENALI_PHY_447_DATA */
+			0x00000000,	/* DENALI_PHY_448_DATA */
+			0x00000000,	/* DENALI_PHY_449_DATA */
+			0x00000000,	/* DENALI_PHY_450_DATA */
+			0x00000000,	/* DENALI_PHY_451_DATA */
+			0x00800000,	/* DENALI_PHY_452_DATA */
+			0x00800080,	/* DENALI_PHY_453_DATA */
+			0x00800080,	/* DENALI_PHY_454_DATA */
+			0x00800080,	/* DENALI_PHY_455_DATA */
+			0x00800080,	/* DENALI_PHY_456_DATA */
+			0x00800080,	/* DENALI_PHY_457_DATA */
+			0x00800080,	/* DENALI_PHY_458_DATA */
+			0x00800080,	/* DENALI_PHY_459_DATA */
+			0x00800080,	/* DENALI_PHY_460_DATA */
+			0x01190080,	/* DENALI_PHY_461_DATA */
+			0x00000001,	/* DENALI_PHY_462_DATA */
+			0x00000000,	/* DENALI_PHY_463_DATA */
+			0x00000000,	/* DENALI_PHY_464_DATA */
+			0x00000200,	/* DENALI_PHY_465_DATA */
+			0x00000000,	/* DENALI_PHY_466_DATA */
+			0x51315152,	/* DENALI_PHY_467_DATA */
+			0xc0003150,	/* DENALI_PHY_468_DATA */
+			0x010000c0,	/* DENALI_PHY_469_DATA */
+			0x00100000,	/* DENALI_PHY_470_DATA */
+			0x07044204,	/* DENALI_PHY_471_DATA */
+			0x000f0c18,	/* DENALI_PHY_472_DATA */
+			0x01000140,	/* DENALI_PHY_473_DATA */
+			0x00000c10,	/* DENALI_PHY_474_DATA */
+			0x00000000,	/* DENALI_PHY_475_DATA */
+			0x00000000,	/* DENALI_PHY_476_DATA */
+			0x00000000,	/* DENALI_PHY_477_DATA */
+			0x00000000,	/* DENALI_PHY_478_DATA */
+			0x00000000,	/* DENALI_PHY_479_DATA */
+			0x00000000,	/* DENALI_PHY_480_DATA */
+			0x00000000,	/* DENALI_PHY_481_DATA */
+			0x00000000,	/* DENALI_PHY_482_DATA */
+			0x00000000,	/* DENALI_PHY_483_DATA */
+			0x00000000,	/* DENALI_PHY_484_DATA */
+			0x00000000,	/* DENALI_PHY_485_DATA */
+			0x00000000,	/* DENALI_PHY_486_DATA */
+			0x00000000,	/* DENALI_PHY_487_DATA */
+			0x00000000,	/* DENALI_PHY_488_DATA */
+			0x00000000,	/* DENALI_PHY_489_DATA */
+			0x00000000,	/* DENALI_PHY_490_DATA */
+			0x00000000,	/* DENALI_PHY_491_DATA */
+			0x00000000,	/* DENALI_PHY_492_DATA */
+			0x00000000,	/* DENALI_PHY_493_DATA */
+			0x00000000,	/* DENALI_PHY_494_DATA */
+			0x00000000,	/* DENALI_PHY_495_DATA */
+			0x00000000,	/* DENALI_PHY_496_DATA */
+			0x00000000,	/* DENALI_PHY_497_DATA */
+			0x00000000,	/* DENALI_PHY_498_DATA */
+			0x00000000,	/* DENALI_PHY_499_DATA */
+			0x00000000,	/* DENALI_PHY_500_DATA */
+			0x00000000,	/* DENALI_PHY_501_DATA */
+			0x00000000,	/* DENALI_PHY_502_DATA */
+			0x00000000,	/* DENALI_PHY_503_DATA */
+			0x00000000,	/* DENALI_PHY_504_DATA */
+			0x00000000,	/* DENALI_PHY_505_DATA */
+			0x00000000,	/* DENALI_PHY_506_DATA */
+			0x00000000,	/* DENALI_PHY_507_DATA */
+			0x00000000,	/* DENALI_PHY_508_DATA */
+			0x00000000,	/* DENALI_PHY_509_DATA */
+			0x00000000,	/* DENALI_PHY_510_DATA */
+			0x00000000,	/* DENALI_PHY_511_DATA */
+			0x00000000,	/* DENALI_PHY_512_DATA */
+			0x00000000,	/* DENALI_PHY_513_DATA */
+			0x00000000,	/* DENALI_PHY_514_DATA */
+			0x00000000,	/* DENALI_PHY_515_DATA */
+			0x00000000,	/* DENALI_PHY_516_DATA */
+			0x00000000,	/* DENALI_PHY_517_DATA */
+			0x00000000,	/* DENALI_PHY_518_DATA */
+			0x00000002,	/* DENALI_PHY_519_DATA */
+			0x00000000,	/* DENALI_PHY_520_DATA */
+			0x00000000,	/* DENALI_PHY_521_DATA */
+			0x00000000,	/* DENALI_PHY_522_DATA */
+			0x00400320,	/* DENALI_PHY_523_DATA */
+			0x00000040,	/* DENALI_PHY_524_DATA */
+			0x00dcba98,	/* DENALI_PHY_525_DATA */
+			0x00000000,	/* DENALI_PHY_526_DATA */
+			0x00dcba98,	/* DENALI_PHY_527_DATA */
+			0x01000000,	/* DENALI_PHY_528_DATA */
+			0x00020003,	/* DENALI_PHY_529_DATA */
+			0x00000000,	/* DENALI_PHY_530_DATA */
+			0x00000000,	/* DENALI_PHY_531_DATA */
+			0x00000000,	/* DENALI_PHY_532_DATA */
+			0x0000002a,	/* DENALI_PHY_533_DATA */
+			0x00000015,	/* DENALI_PHY_534_DATA */
+			0x00000015,	/* DENALI_PHY_535_DATA */
+			0x0000002a,	/* DENALI_PHY_536_DATA */
+			0x00000033,	/* DENALI_PHY_537_DATA */
+			0x0000000c,	/* DENALI_PHY_538_DATA */
+			0x0000000c,	/* DENALI_PHY_539_DATA */
+			0x00000033,	/* DENALI_PHY_540_DATA */
+			0x0a418820,	/* DENALI_PHY_541_DATA */
+			0x003f0000,	/* DENALI_PHY_542_DATA */
+			0x0000003f,	/* DENALI_PHY_543_DATA */
+			0x00030055,	/* DENALI_PHY_544_DATA */
+			0x03000300,	/* DENALI_PHY_545_DATA */
+			0x03000300,	/* DENALI_PHY_546_DATA */
+			0x00000300,	/* DENALI_PHY_547_DATA */
+			0x42080010,	/* DENALI_PHY_548_DATA */
+			0x00000003,	/* DENALI_PHY_549_DATA */
+			0x00000000,	/* DENALI_PHY_550_DATA */
+			0x00000000,	/* DENALI_PHY_551_DATA */
+			0x00000000,	/* DENALI_PHY_552_DATA */
+			0x00000000,	/* DENALI_PHY_553_DATA */
+			0x00000000,	/* DENALI_PHY_554_DATA */
+			0x00000000,	/* DENALI_PHY_555_DATA */
+			0x00000000,	/* DENALI_PHY_556_DATA */
+			0x00000000,	/* DENALI_PHY_557_DATA */
+			0x00000000,	/* DENALI_PHY_558_DATA */
+			0x00000000,	/* DENALI_PHY_559_DATA */
+			0x00000000,	/* DENALI_PHY_560_DATA */
+			0x00000000,	/* DENALI_PHY_561_DATA */
+			0x00000000,	/* DENALI_PHY_562_DATA */
+			0x00000000,	/* DENALI_PHY_563_DATA */
+			0x00000000,	/* DENALI_PHY_564_DATA */
+			0x00000000,	/* DENALI_PHY_565_DATA */
+			0x00000000,	/* DENALI_PHY_566_DATA */
+			0x00000000,	/* DENALI_PHY_567_DATA */
+			0x00000000,	/* DENALI_PHY_568_DATA */
+			0x00000000,	/* DENALI_PHY_569_DATA */
+			0x00000000,	/* DENALI_PHY_570_DATA */
+			0x00000000,	/* DENALI_PHY_571_DATA */
+			0x00000000,	/* DENALI_PHY_572_DATA */
+			0x00000000,	/* DENALI_PHY_573_DATA */
+			0x00000000,	/* DENALI_PHY_574_DATA */
+			0x00000000,	/* DENALI_PHY_575_DATA */
+			0x00000000,	/* DENALI_PHY_576_DATA */
+			0x00000000,	/* DENALI_PHY_577_DATA */
+			0x00000000,	/* DENALI_PHY_578_DATA */
+			0x00000000,	/* DENALI_PHY_579_DATA */
+			0x00000000,	/* DENALI_PHY_580_DATA */
+			0x00000000,	/* DENALI_PHY_581_DATA */
+			0x00000000,	/* DENALI_PHY_582_DATA */
+			0x00000000,	/* DENALI_PHY_583_DATA */
+			0x00000000,	/* DENALI_PHY_584_DATA */
+			0x00000000,	/* DENALI_PHY_585_DATA */
+			0x00000000,	/* DENALI_PHY_586_DATA */
+			0x00000000,	/* DENALI_PHY_587_DATA */
+			0x00000000,	/* DENALI_PHY_588_DATA */
+			0x00000000,	/* DENALI_PHY_589_DATA */
+			0x00000000,	/* DENALI_PHY_590_DATA */
+			0x00000000,	/* DENALI_PHY_591_DATA */
+			0x00000000,	/* DENALI_PHY_592_DATA */
+			0x00000000,	/* DENALI_PHY_593_DATA */
+			0x00000000,	/* DENALI_PHY_594_DATA */
+			0x00000000,	/* DENALI_PHY_595_DATA */
+			0x00000000,	/* DENALI_PHY_596_DATA */
+			0x00000000,	/* DENALI_PHY_597_DATA */
+			0x00000000,	/* DENALI_PHY_598_DATA */
+			0x00000000,	/* DENALI_PHY_599_DATA */
+			0x00000000,	/* DENALI_PHY_600_DATA */
+			0x00000000,	/* DENALI_PHY_601_DATA */
+			0x00000000,	/* DENALI_PHY_602_DATA */
+			0x00000000,	/* DENALI_PHY_603_DATA */
+			0x00000000,	/* DENALI_PHY_604_DATA */
+			0x00000000,	/* DENALI_PHY_605_DATA */
+			0x00000000,	/* DENALI_PHY_606_DATA */
+			0x00000000,	/* DENALI_PHY_607_DATA */
+			0x00000000,	/* DENALI_PHY_608_DATA */
+			0x00000000,	/* DENALI_PHY_609_DATA */
+			0x00000000,	/* DENALI_PHY_610_DATA */
+			0x00000000,	/* DENALI_PHY_611_DATA */
+			0x00000000,	/* DENALI_PHY_612_DATA */
+			0x00000000,	/* DENALI_PHY_613_DATA */
+			0x00000000,	/* DENALI_PHY_614_DATA */
+			0x00000000,	/* DENALI_PHY_615_DATA */
+			0x00000000,	/* DENALI_PHY_616_DATA */
+			0x00000000,	/* DENALI_PHY_617_DATA */
+			0x00000000,	/* DENALI_PHY_618_DATA */
+			0x00000000,	/* DENALI_PHY_619_DATA */
+			0x00000000,	/* DENALI_PHY_620_DATA */
+			0x00000000,	/* DENALI_PHY_621_DATA */
+			0x00000000,	/* DENALI_PHY_622_DATA */
+			0x00000000,	/* DENALI_PHY_623_DATA */
+			0x00000000,	/* DENALI_PHY_624_DATA */
+			0x00000000,	/* DENALI_PHY_625_DATA */
+			0x00000000,	/* DENALI_PHY_626_DATA */
+			0x00000000,	/* DENALI_PHY_627_DATA */
+			0x00000000,	/* DENALI_PHY_628_DATA */
+			0x00000000,	/* DENALI_PHY_629_DATA */
+			0x00000000,	/* DENALI_PHY_630_DATA */
+			0x00000000,	/* DENALI_PHY_631_DATA */
+			0x00000000,	/* DENALI_PHY_632_DATA */
+			0x00000000,	/* DENALI_PHY_633_DATA */
+			0x00000000,	/* DENALI_PHY_634_DATA */
+			0x00000000,	/* DENALI_PHY_635_DATA */
+			0x00000000,	/* DENALI_PHY_636_DATA */
+			0x00000000,	/* DENALI_PHY_637_DATA */
+			0x00000000,	/* DENALI_PHY_638_DATA */
+			0x00000000,	/* DENALI_PHY_639_DATA */
+			0x00000000,	/* DENALI_PHY_640_DATA */
+			0x00000000,	/* DENALI_PHY_641_DATA */
+			0x00000000,	/* DENALI_PHY_642_DATA */
+			0x00000000,	/* DENALI_PHY_643_DATA */
+			0x00000000,	/* DENALI_PHY_644_DATA */
+			0x00000000,	/* DENALI_PHY_645_DATA */
+			0x00000000,	/* DENALI_PHY_646_DATA */
+			0x00000002,	/* DENALI_PHY_647_DATA */
+			0x00000000,	/* DENALI_PHY_648_DATA */
+			0x00000000,	/* DENALI_PHY_649_DATA */
+			0x00000000,	/* DENALI_PHY_650_DATA */
+			0x00400320,	/* DENALI_PHY_651_DATA */
+			0x00000040,	/* DENALI_PHY_652_DATA */
+			0x00000000,	/* DENALI_PHY_653_DATA */
+			0x00000000,	/* DENALI_PHY_654_DATA */
+			0x00000000,	/* DENALI_PHY_655_DATA */
+			0x01000000,	/* DENALI_PHY_656_DATA */
+			0x00020003,	/* DENALI_PHY_657_DATA */
+			0x00000000,	/* DENALI_PHY_658_DATA */
+			0x00000000,	/* DENALI_PHY_659_DATA */
+			0x00000000,	/* DENALI_PHY_660_DATA */
+			0x0000002a,	/* DENALI_PHY_661_DATA */
+			0x00000015,	/* DENALI_PHY_662_DATA */
+			0x00000015,	/* DENALI_PHY_663_DATA */
+			0x0000002a,	/* DENALI_PHY_664_DATA */
+			0x00000033,	/* DENALI_PHY_665_DATA */
+			0x0000000c,	/* DENALI_PHY_666_DATA */
+			0x0000000c,	/* DENALI_PHY_667_DATA */
+			0x00000033,	/* DENALI_PHY_668_DATA */
+			0x00000000,	/* DENALI_PHY_669_DATA */
+			0x00000000,	/* DENALI_PHY_670_DATA */
+			0x00000000,	/* DENALI_PHY_671_DATA */
+			0x00030055,	/* DENALI_PHY_672_DATA */
+			0x03000300,	/* DENALI_PHY_673_DATA */
+			0x03000300,	/* DENALI_PHY_674_DATA */
+			0x00000300,	/* DENALI_PHY_675_DATA */
+			0x42080010,	/* DENALI_PHY_676_DATA */
+			0x00000003,	/* DENALI_PHY_677_DATA */
+			0x00000000,	/* DENALI_PHY_678_DATA */
+			0x00000000,	/* DENALI_PHY_679_DATA */
+			0x00000000,	/* DENALI_PHY_680_DATA */
+			0x00000000,	/* DENALI_PHY_681_DATA */
+			0x00000000,	/* DENALI_PHY_682_DATA */
+			0x00000000,	/* DENALI_PHY_683_DATA */
+			0x00000000,	/* DENALI_PHY_684_DATA */
+			0x00000000,	/* DENALI_PHY_685_DATA */
+			0x00000000,	/* DENALI_PHY_686_DATA */
+			0x00000000,	/* DENALI_PHY_687_DATA */
+			0x00000000,	/* DENALI_PHY_688_DATA */
+			0x00000000,	/* DENALI_PHY_689_DATA */
+			0x00000000,	/* DENALI_PHY_690_DATA */
+			0x00000000,	/* DENALI_PHY_691_DATA */
+			0x00000000,	/* DENALI_PHY_692_DATA */
+			0x00000000,	/* DENALI_PHY_693_DATA */
+			0x00000000,	/* DENALI_PHY_694_DATA */
+			0x00000000,	/* DENALI_PHY_695_DATA */
+			0x00000000,	/* DENALI_PHY_696_DATA */
+			0x00000000,	/* DENALI_PHY_697_DATA */
+			0x00000000,	/* DENALI_PHY_698_DATA */
+			0x00000000,	/* DENALI_PHY_699_DATA */
+			0x00000000,	/* DENALI_PHY_700_DATA */
+			0x00000000,	/* DENALI_PHY_701_DATA */
+			0x00000000,	/* DENALI_PHY_702_DATA */
+			0x00000000,	/* DENALI_PHY_703_DATA */
+			0x00000000,	/* DENALI_PHY_704_DATA */
+			0x00000000,	/* DENALI_PHY_705_DATA */
+			0x00000000,	/* DENALI_PHY_706_DATA */
+			0x00000000,	/* DENALI_PHY_707_DATA */
+			0x00000000,	/* DENALI_PHY_708_DATA */
+			0x00000000,	/* DENALI_PHY_709_DATA */
+			0x00000000,	/* DENALI_PHY_710_DATA */
+			0x00000000,	/* DENALI_PHY_711_DATA */
+			0x00000000,	/* DENALI_PHY_712_DATA */
+			0x00000000,	/* DENALI_PHY_713_DATA */
+			0x00000000,	/* DENALI_PHY_714_DATA */
+			0x00000000,	/* DENALI_PHY_715_DATA */
+			0x00000000,	/* DENALI_PHY_716_DATA */
+			0x00000000,	/* DENALI_PHY_717_DATA */
+			0x00000000,	/* DENALI_PHY_718_DATA */
+			0x00000000,	/* DENALI_PHY_719_DATA */
+			0x00000000,	/* DENALI_PHY_720_DATA */
+			0x00000000,	/* DENALI_PHY_721_DATA */
+			0x00000000,	/* DENALI_PHY_722_DATA */
+			0x00000000,	/* DENALI_PHY_723_DATA */
+			0x00000000,	/* DENALI_PHY_724_DATA */
+			0x00000000,	/* DENALI_PHY_725_DATA */
+			0x00000000,	/* DENALI_PHY_726_DATA */
+			0x00000000,	/* DENALI_PHY_727_DATA */
+			0x00000000,	/* DENALI_PHY_728_DATA */
+			0x00000000,	/* DENALI_PHY_729_DATA */
+			0x00000000,	/* DENALI_PHY_730_DATA */
+			0x00000000,	/* DENALI_PHY_731_DATA */
+			0x00000000,	/* DENALI_PHY_732_DATA */
+			0x00000000,	/* DENALI_PHY_733_DATA */
+			0x00000000,	/* DENALI_PHY_734_DATA */
+			0x00000000,	/* DENALI_PHY_735_DATA */
+			0x00000000,	/* DENALI_PHY_736_DATA */
+			0x00000000,	/* DENALI_PHY_737_DATA */
+			0x00000000,	/* DENALI_PHY_738_DATA */
+			0x00000000,	/* DENALI_PHY_739_DATA */
+			0x00000000,	/* DENALI_PHY_740_DATA */
+			0x00000000,	/* DENALI_PHY_741_DATA */
+			0x00000000,	/* DENALI_PHY_742_DATA */
+			0x00000000,	/* DENALI_PHY_743_DATA */
+			0x00000000,	/* DENALI_PHY_744_DATA */
+			0x00000000,	/* DENALI_PHY_745_DATA */
+			0x00000000,	/* DENALI_PHY_746_DATA */
+			0x00000000,	/* DENALI_PHY_747_DATA */
+			0x00000000,	/* DENALI_PHY_748_DATA */
+			0x00000000,	/* DENALI_PHY_749_DATA */
+			0x00000000,	/* DENALI_PHY_750_DATA */
+			0x00000000,	/* DENALI_PHY_751_DATA */
+			0x00000000,	/* DENALI_PHY_752_DATA */
+			0x00000000,	/* DENALI_PHY_753_DATA */
+			0x00000000,	/* DENALI_PHY_754_DATA */
+			0x00000000,	/* DENALI_PHY_755_DATA */
+			0x00000000,	/* DENALI_PHY_756_DATA */
+			0x00000000,	/* DENALI_PHY_757_DATA */
+			0x00000000,	/* DENALI_PHY_758_DATA */
+			0x00000000,	/* DENALI_PHY_759_DATA */
+			0x00000000,	/* DENALI_PHY_760_DATA */
+			0x00000000,	/* DENALI_PHY_761_DATA */
+			0x00000000,	/* DENALI_PHY_762_DATA */
+			0x00000000,	/* DENALI_PHY_763_DATA */
+			0x00000000,	/* DENALI_PHY_764_DATA */
+			0x00000000,	/* DENALI_PHY_765_DATA */
+			0x00000000,	/* DENALI_PHY_766_DATA */
+			0x00000000,	/* DENALI_PHY_767_DATA */
+			0x00000000,	/* DENALI_PHY_768_DATA */
+			0x00000000,	/* DENALI_PHY_769_DATA */
+			0x00000000,	/* DENALI_PHY_770_DATA */
+			0x00000000,	/* DENALI_PHY_771_DATA */
+			0x00000000,	/* DENALI_PHY_772_DATA */
+			0x00000000,	/* DENALI_PHY_773_DATA */
+			0x00000000,	/* DENALI_PHY_774_DATA */
+			0x00000002,	/* DENALI_PHY_775_DATA */
+			0x00000000,	/* DENALI_PHY_776_DATA */
+			0x00000000,	/* DENALI_PHY_777_DATA */
+			0x00000000,	/* DENALI_PHY_778_DATA */
+			0x00400320,	/* DENALI_PHY_779_DATA */
+			0x00000040,	/* DENALI_PHY_780_DATA */
+			0x00000000,	/* DENALI_PHY_781_DATA */
+			0x00000000,	/* DENALI_PHY_782_DATA */
+			0x00000000,	/* DENALI_PHY_783_DATA */
+			0x01000000,	/* DENALI_PHY_784_DATA */
+			0x00020003,	/* DENALI_PHY_785_DATA */
+			0x00000000,	/* DENALI_PHY_786_DATA */
+			0x00000000,	/* DENALI_PHY_787_DATA */
+			0x00000000,	/* DENALI_PHY_788_DATA */
+			0x0000002a,	/* DENALI_PHY_789_DATA */
+			0x00000015,	/* DENALI_PHY_790_DATA */
+			0x00000015,	/* DENALI_PHY_791_DATA */
+			0x0000002a,	/* DENALI_PHY_792_DATA */
+			0x00000033,	/* DENALI_PHY_793_DATA */
+			0x0000000c,	/* DENALI_PHY_794_DATA */
+			0x0000000c,	/* DENALI_PHY_795_DATA */
+			0x00000033,	/* DENALI_PHY_796_DATA */
+			0x1ee6b16a,	/* DENALI_PHY_797_DATA */
+			0x10000000,	/* DENALI_PHY_798_DATA */
+			0x00000000,	/* DENALI_PHY_799_DATA */
+			0x00030055,	/* DENALI_PHY_800_DATA */
+			0x03000300,	/* DENALI_PHY_801_DATA */
+			0x03000300,	/* DENALI_PHY_802_DATA */
+			0x00000300,	/* DENALI_PHY_803_DATA */
+			0x42080010,	/* DENALI_PHY_804_DATA */
+			0x00000003,	/* DENALI_PHY_805_DATA */
+			0x00000000,	/* DENALI_PHY_806_DATA */
+			0x00000000,	/* DENALI_PHY_807_DATA */
+			0x00000000,	/* DENALI_PHY_808_DATA */
+			0x00000000,	/* DENALI_PHY_809_DATA */
+			0x00000000,	/* DENALI_PHY_810_DATA */
+			0x00000000,	/* DENALI_PHY_811_DATA */
+			0x00000000,	/* DENALI_PHY_812_DATA */
+			0x00000000,	/* DENALI_PHY_813_DATA */
+			0x00000000,	/* DENALI_PHY_814_DATA */
+			0x00000000,	/* DENALI_PHY_815_DATA */
+			0x00000000,	/* DENALI_PHY_816_DATA */
+			0x00000000,	/* DENALI_PHY_817_DATA */
+			0x00000000,	/* DENALI_PHY_818_DATA */
+			0x00000000,	/* DENALI_PHY_819_DATA */
+			0x00000000,	/* DENALI_PHY_820_DATA */
+			0x00000000,	/* DENALI_PHY_821_DATA */
+			0x00000000,	/* DENALI_PHY_822_DATA */
+			0x00000000,	/* DENALI_PHY_823_DATA */
+			0x00000000,	/* DENALI_PHY_824_DATA */
+			0x00000000,	/* DENALI_PHY_825_DATA */
+			0x00000000,	/* DENALI_PHY_826_DATA */
+			0x00000000,	/* DENALI_PHY_827_DATA */
+			0x00000000,	/* DENALI_PHY_828_DATA */
+			0x00000000,	/* DENALI_PHY_829_DATA */
+			0x00000000,	/* DENALI_PHY_830_DATA */
+			0x00000000,	/* DENALI_PHY_831_DATA */
+			0x00000000,	/* DENALI_PHY_832_DATA */
+			0x00000000,	/* DENALI_PHY_833_DATA */
+			0x00000000,	/* DENALI_PHY_834_DATA */
+			0x00000000,	/* DENALI_PHY_835_DATA */
+			0x00000000,	/* DENALI_PHY_836_DATA */
+			0x00000000,	/* DENALI_PHY_837_DATA */
+			0x00000000,	/* DENALI_PHY_838_DATA */
+			0x00000000,	/* DENALI_PHY_839_DATA */
+			0x00000000,	/* DENALI_PHY_840_DATA */
+			0x00000000,	/* DENALI_PHY_841_DATA */
+			0x00000000,	/* DENALI_PHY_842_DATA */
+			0x00000000,	/* DENALI_PHY_843_DATA */
+			0x00000000,	/* DENALI_PHY_844_DATA */
+			0x00000000,	/* DENALI_PHY_845_DATA */
+			0x00000000,	/* DENALI_PHY_846_DATA */
+			0x00000000,	/* DENALI_PHY_847_DATA */
+			0x00000000,	/* DENALI_PHY_848_DATA */
+			0x00000000,	/* DENALI_PHY_849_DATA */
+			0x00000000,	/* DENALI_PHY_850_DATA */
+			0x00000000,	/* DENALI_PHY_851_DATA */
+			0x00000000,	/* DENALI_PHY_852_DATA */
+			0x00000000,	/* DENALI_PHY_853_DATA */
+			0x00000000,	/* DENALI_PHY_854_DATA */
+			0x00000000,	/* DENALI_PHY_855_DATA */
+			0x00000000,	/* DENALI_PHY_856_DATA */
+			0x00000000,	/* DENALI_PHY_857_DATA */
+			0x00000000,	/* DENALI_PHY_858_DATA */
+			0x00000000,	/* DENALI_PHY_859_DATA */
+			0x00000000,	/* DENALI_PHY_860_DATA */
+			0x00000000,	/* DENALI_PHY_861_DATA */
+			0x00000000,	/* DENALI_PHY_862_DATA */
+			0x00000000,	/* DENALI_PHY_863_DATA */
+			0x00000000,	/* DENALI_PHY_864_DATA */
+			0x00000000,	/* DENALI_PHY_865_DATA */
+			0x00000000,	/* DENALI_PHY_866_DATA */
+			0x00000000,	/* DENALI_PHY_867_DATA */
+			0x00000000,	/* DENALI_PHY_868_DATA */
+			0x00000000,	/* DENALI_PHY_869_DATA */
+			0x00000000,	/* DENALI_PHY_870_DATA */
+			0x00000000,	/* DENALI_PHY_871_DATA */
+			0x00000000,	/* DENALI_PHY_872_DATA */
+			0x00000000,	/* DENALI_PHY_873_DATA */
+			0x00000000,	/* DENALI_PHY_874_DATA */
+			0x00000000,	/* DENALI_PHY_875_DATA */
+			0x00000000,	/* DENALI_PHY_876_DATA */
+			0x00000000,	/* DENALI_PHY_877_DATA */
+			0x00000000,	/* DENALI_PHY_878_DATA */
+			0x00000000,	/* DENALI_PHY_879_DATA */
+			0x00000000,	/* DENALI_PHY_880_DATA */
+			0x00000000,	/* DENALI_PHY_881_DATA */
+			0x00000000,	/* DENALI_PHY_882_DATA */
+			0x00000000,	/* DENALI_PHY_883_DATA */
+			0x00000000,	/* DENALI_PHY_884_DATA */
+			0x00000000,	/* DENALI_PHY_885_DATA */
+			0x00000000,	/* DENALI_PHY_886_DATA */
+			0x00000000,	/* DENALI_PHY_887_DATA */
+			0x00000000,	/* DENALI_PHY_888_DATA */
+			0x00000000,	/* DENALI_PHY_889_DATA */
+			0x00000000,	/* DENALI_PHY_890_DATA */
+			0x00000000,	/* DENALI_PHY_891_DATA */
+			0x00000000,	/* DENALI_PHY_892_DATA */
+			0x00000000,	/* DENALI_PHY_893_DATA */
+			0x00000000,	/* DENALI_PHY_894_DATA */
+			0x00000000,	/* DENALI_PHY_895_DATA */
+			0x00000000,	/* DENALI_PHY_896_DATA */
+			0x00000000,	/* DENALI_PHY_897_DATA */
+			0x00000005,	/* DENALI_PHY_898_DATA */
+			0x04000f01,	/* DENALI_PHY_899_DATA */
+			0x00020040,	/* DENALI_PHY_900_DATA */
+			0x00020055,	/* DENALI_PHY_901_DATA */
+			0x00000000,	/* DENALI_PHY_902_DATA */
+			0x00000000,	/* DENALI_PHY_903_DATA */
+			0x00000000,	/* DENALI_PHY_904_DATA */
+			0x00000050,	/* DENALI_PHY_905_DATA */
+			0x00000000,	/* DENALI_PHY_906_DATA */
+			0x01010100,	/* DENALI_PHY_907_DATA */
+			0x00000600,	/* DENALI_PHY_908_DATA */
+			0x00000000,	/* DENALI_PHY_909_DATA */
+			0x00006400,	/* DENALI_PHY_910_DATA */
+			0x03221302,	/* DENALI_PHY_911_DATA */
+			0x00000000,	/* DENALI_PHY_912_DATA */
+			0x000d1f01,	/* DENALI_PHY_913_DATA */
+			0x0d1f0d1f,	/* DENALI_PHY_914_DATA */
+			0x0d1f0d1f,	/* DENALI_PHY_915_DATA */
+			0x00030003,	/* DENALI_PHY_916_DATA */
+			0x03000300,	/* DENALI_PHY_917_DATA */
+			0x00000300,	/* DENALI_PHY_918_DATA */
+			0x03221302,	/* DENALI_PHY_919_DATA */
+			0x00000000,	/* DENALI_PHY_920_DATA */
+			0x00000000,	/* DENALI_PHY_921_DATA */
+			0x01020000,	/* DENALI_PHY_922_DATA */
+			0x00000001,	/* DENALI_PHY_923_DATA */
+			0x00000411,	/* DENALI_PHY_924_DATA */
+			0x00000411,	/* DENALI_PHY_925_DATA */
+			0x00000040,	/* DENALI_PHY_926_DATA */
+			0x00000040,	/* DENALI_PHY_927_DATA */
+			0x00000411,	/* DENALI_PHY_928_DATA */
+			0x00000411,	/* DENALI_PHY_929_DATA */
+			0x00004410,	/* DENALI_PHY_930_DATA */
+			0x00004410,	/* DENALI_PHY_931_DATA */
+			0x00004410,	/* DENALI_PHY_932_DATA */
+			0x00004410,	/* DENALI_PHY_933_DATA */
+			0x00004410,	/* DENALI_PHY_934_DATA */
+			0x00000411,	/* DENALI_PHY_935_DATA */
+			0x00004410,	/* DENALI_PHY_936_DATA */
+			0x00000411,	/* DENALI_PHY_937_DATA */
+			0x00004410,	/* DENALI_PHY_938_DATA */
+			0x00000411,	/* DENALI_PHY_939_DATA */
+			0x00004410,	/* DENALI_PHY_940_DATA */
+			0x00000000,	/* DENALI_PHY_941_DATA */
+			0x00000000,	/* DENALI_PHY_942_DATA */
+			0x00000000,	/* DENALI_PHY_943_DATA */
+			0x64000000,	/* DENALI_PHY_944_DATA */
+			0x00000000,	/* DENALI_PHY_945_DATA */
+			0x00000000,	/* DENALI_PHY_946_DATA */
+			0x00000408,	/* DENALI_PHY_947_DATA */
+			0x00000000,	/* DENALI_PHY_948_DATA */
+			0x00000000,	/* DENALI_PHY_949_DATA */
+			0x00000000,	/* DENALI_PHY_950_DATA */
+			0x00000000,	/* DENALI_PHY_951_DATA */
+			0x00000000,	/* DENALI_PHY_952_DATA */
+			0x00000000,	/* DENALI_PHY_953_DATA */
+			0xe4000000,	/* DENALI_PHY_954_DATA */
+			0x00000000,	/* DENALI_PHY_955_DATA */
+			0x00000000,	/* DENALI_PHY_956_DATA */
+			0x01010000,	/* DENALI_PHY_957_DATA */
+			0x00000000	/* DENALI_PHY_958_DATA */
+		}
+	},
+},
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-50-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#141 lore raw

Re: [PATCH v3 49/57] ram: rk3399: Add LPPDDR4-400 timings inc

Quoted 10 lines · Jagan Teki

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

So, add LPDDR4-400 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#142 lore raw

PATCH v3 50/57 ram: rk3399: Add LPPDDR4-800 timings inc

In reply to a message not in the archive

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 .../ram/rockchip/sdram-rk3399-lpddr4-800.inc  | 1570 +++++++++++++++++
 1 file changed, 1570 insertions(+)
 create mode 100644 drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc
drivers/ram/rockchip/sdram-rk3399-lpddr4-800.inc new file +1570 -0
new file mode 100644
index 0000000000..d8ae3359a3
@@ -0,0 +1,1570 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
+ * (C) Copyright 2019 Amarula Solutions
+ */
+
+{
+	{
+		{
+			{
+				.rank = 0x2,
+				.col = 0xA,
+				.bk = 0x3,
+				.bw = 0x2,
+				.dbw = 0x1,
+				.row_3_4 = 0x0,
+				.cs0_row = 0xF,
+				.cs1_row = 0xF,
+				.ddrconfig = 1,
+			},
+			{
+				.ddrtiminga0 = 0x80241d22,
+				.ddrtimingb0 = 0x15050f08,
+				.ddrtimingc0 = {
+					0x00000602,
+				},
+				.devtodev0 = 0x00002122,
+				.ddrmode = {
+					0x0000004c,
+				},
+				.agingx0 = 0x00000000,
+			}
+		},
+		{
+			{
+				.rank = 0x2,
+				.col = 0xA,
+				.bk = 0x3,
+				.bw = 0x2,
+				.dbw = 0x1,
+				.row_3_4 = 0x0,
+				.cs0_row = 0xF,
+				.cs1_row = 0xF,
+				.ddrconfig = 1,
+			},
+			{
+				.ddrtiminga0 = 0x80241d22,
+				.ddrtimingb0 = 0x15050f08,
+				.ddrtimingc0 = {
+					0x00000602,
+				},
+				.devtodev0 = 0x00002122,
+				.ddrmode = {
+					0x0000004c,
+				},
+				.agingx0 = 0x00000000,
+			}
+		}
+	},
+	{
+		.ddr_freq = 800 * MHz,
+		.dramtype = LPDDR4,
+		.num_channels = 2,
+		.stride = 13,
+		.odt = 1,
+	},
+	{
+		{
+			0x00000b00,	/* DENALI_CTL_00_DATA */
+			0x00000000,	/* DENALI_CTL_01_DATA */
+			0x00000000,	/* DENALI_CTL_02_DATA */
+			0x00000000,	/* DENALI_CTL_03_DATA */
+			0x00000000,	/* DENALI_CTL_04_DATA */
+			0x00013880,	/* DENALI_CTL_05_DATA */
+			0x000c3500,	/* DENALI_CTL_06_DATA */
+			0x00000005,	/* DENALI_CTL_07_DATA */
+			0x00000320,	/* DENALI_CTL_08_DATA */
+			0x00027100,	/* DENALI_CTL_09_DATA */
+			0x00186a00,	/* DENALI_CTL_10_DATA */
+			0x00000005,	/* DENALI_CTL_11_DATA */
+			0x00000640,	/* DENALI_CTL_12_DATA */
+			0x00002710,	/* DENALI_CTL_13_DATA */
+			0x000186a0,	/* DENALI_CTL_14_DATA */
+			0x00000005,	/* DENALI_CTL_15_DATA */
+			0x01000064,	/* DENALI_CTL_16_DATA */
+			0x00000000,	/* DENALI_CTL_17_DATA */
+			0x02020101,	/* DENALI_CTL_18_DATA */
+			0x00000102,	/* DENALI_CTL_19_DATA */
+			0x00000050,	/* DENALI_CTL_20_DATA */
+			0x000000c8,	/* DENALI_CTL_21_DATA */
+			0x00000000,	/* DENALI_CTL_22_DATA */
+			0x06140000,	/* DENALI_CTL_23_DATA */
+			0x00081c00,	/* DENALI_CTL_24_DATA */
+			0x0400040c,	/* DENALI_CTL_25_DATA */
+			0x19042008,	/* DENALI_CTL_26_DATA */
+			0x10080a11,	/* DENALI_CTL_27_DATA */
+			0x22310800,	/* DENALI_CTL_28_DATA */
+			0x00200f0a,	/* DENALI_CTL_29_DATA */
+			0x0a030704,	/* DENALI_CTL_30_DATA */
+			0x08000204,	/* DENALI_CTL_31_DATA */
+			0x00000a0a,	/* DENALI_CTL_32_DATA */
+			0x04006db0,	/* DENALI_CTL_33_DATA */
+			0x0a0a0804,	/* DENALI_CTL_34_DATA */
+			0x0600db60,	/* DENALI_CTL_35_DATA */
+			0x0a0a0806,	/* DENALI_CTL_36_DATA */
+			0x04000db6,	/* DENALI_CTL_37_DATA */
+			0x02030404,	/* DENALI_CTL_38_DATA */
+			0x0f0a0800,	/* DENALI_CTL_39_DATA */
+			0x08040411,	/* DENALI_CTL_40_DATA */
+			0x1400640a,	/* DENALI_CTL_41_DATA */
+			0x02010a0a,	/* DENALI_CTL_42_DATA */
+			0x00010001,	/* DENALI_CTL_43_DATA */
+			0x04082012,	/* DENALI_CTL_44_DATA */
+			0x00041109,	/* DENALI_CTL_45_DATA */
+			0x00000000,	/* DENALI_CTL_46_DATA */
+			0x03010000,	/* DENALI_CTL_47_DATA */
+			0x06100034,	/* DENALI_CTL_48_DATA */
+			0x0c280068,	/* DENALI_CTL_49_DATA */
+			0x00bb0007,	/* DENALI_CTL_50_DATA */
+			0x00000000,	/* DENALI_CTL_51_DATA */
+			0x00060003,	/* DENALI_CTL_52_DATA */
+			0x000a0003,	/* DENALI_CTL_53_DATA */
+			0x000a0014,	/* DENALI_CTL_54_DATA */
+			0x01000000,	/* DENALI_CTL_55_DATA */
+			0x030a0000,	/* DENALI_CTL_56_DATA */
+			0x0c000002,	/* DENALI_CTL_57_DATA */
+			0x00000103,	/* DENALI_CTL_58_DATA */
+			0x0003030a,	/* DENALI_CTL_59_DATA */
+			0x00060037,	/* DENALI_CTL_60_DATA */
+			0x0003006e,	/* DENALI_CTL_61_DATA */
+			0x05050007,	/* DENALI_CTL_62_DATA */
+			0x03020605,	/* DENALI_CTL_63_DATA */
+			0x06050301,	/* DENALI_CTL_64_DATA */
+			0x06020c05,	/* DENALI_CTL_65_DATA */
+			0x05050302,	/* DENALI_CTL_66_DATA */
+			0x03020305,	/* DENALI_CTL_67_DATA */
+			0x00000301,	/* DENALI_CTL_68_DATA */
+			0x00000301,	/* DENALI_CTL_69_DATA */
+			0x00000001,	/* DENALI_CTL_70_DATA */
+			0x00000000,	/* DENALI_CTL_71_DATA */
+			0x00000000,	/* DENALI_CTL_72_DATA */
+			0x01000000,	/* DENALI_CTL_73_DATA */
+			0x80104002,	/* DENALI_CTL_74_DATA */
+			0x00040003,	/* DENALI_CTL_75_DATA */
+			0x00040005,	/* DENALI_CTL_76_DATA */
+			0x00030000,	/* DENALI_CTL_77_DATA */
+			0x00050004,	/* DENALI_CTL_78_DATA */
+			0x00000004,	/* DENALI_CTL_79_DATA */
+			0x00040003,	/* DENALI_CTL_80_DATA */
+			0x00040005,	/* DENALI_CTL_81_DATA */
+			0x18400000,	/* DENALI_CTL_82_DATA */
+			0x00000c20,	/* DENALI_CTL_83_DATA */
+			0x185030a0,	/* DENALI_CTL_84_DATA */
+			0x02ec0000,	/* DENALI_CTL_85_DATA */
+			0x00000176,	/* DENALI_CTL_86_DATA */
+			0x00000000,	/* DENALI_CTL_87_DATA */
+			0x00000000,	/* DENALI_CTL_88_DATA */
+			0x00000000,	/* DENALI_CTL_89_DATA */
+			0x00000000,	/* DENALI_CTL_90_DATA */
+			0x00000000,	/* DENALI_CTL_91_DATA */
+			0x06030300,	/* DENALI_CTL_92_DATA */
+			0x00030303,	/* DENALI_CTL_93_DATA */
+			0x02030200,	/* DENALI_CTL_94_DATA */
+			0x00040703,	/* DENALI_CTL_95_DATA */
+			0x03020302,	/* DENALI_CTL_96_DATA */
+			0x02000407,	/* DENALI_CTL_97_DATA */
+			0x07030203,	/* DENALI_CTL_98_DATA */
+			0x00030f04,	/* DENALI_CTL_99_DATA */
+			0x00070004,	/* DENALI_CTL_100_DATA */
+			0x00000000,	/* DENALI_CTL_101_DATA */
+			0x00000000,	/* DENALI_CTL_102_DATA */
+			0x00000000,	/* DENALI_CTL_103_DATA */
+			0x00000000,	/* DENALI_CTL_104_DATA */
+			0x00000000,	/* DENALI_CTL_105_DATA */
+			0x00000000,	/* DENALI_CTL_106_DATA */
+			0x00000000,	/* DENALI_CTL_107_DATA */
+			0x00010000,	/* DENALI_CTL_108_DATA */
+			0x20040020,	/* DENALI_CTL_109_DATA */
+			0x00200400,	/* DENALI_CTL_110_DATA */
+			0x01000400,	/* DENALI_CTL_111_DATA */
+			0x00000b80,	/* DENALI_CTL_112_DATA */
+			0x00000000,	/* DENALI_CTL_113_DATA */
+			0x00000001,	/* DENALI_CTL_114_DATA */
+			0x00000002,	/* DENALI_CTL_115_DATA */
+			0x0000000e,	/* DENALI_CTL_116_DATA */
+			0x00000000,	/* DENALI_CTL_117_DATA */
+			0x00000000,	/* DENALI_CTL_118_DATA */
+			0x00000000,	/* DENALI_CTL_119_DATA */
+			0x00000000,	/* DENALI_CTL_120_DATA */
+			0x00000000,	/* DENALI_CTL_121_DATA */
+			0x00500000,	/* DENALI_CTL_122_DATA */
+			0x00640028,	/* DENALI_CTL_123_DATA */
+			0x00640404,	/* DENALI_CTL_124_DATA */
+			0x005000a0,	/* DENALI_CTL_125_DATA */
+			0x060600c8,	/* DENALI_CTL_126_DATA */
+			0x000a00c8,	/* DENALI_CTL_127_DATA */
+			0x000d0005,	/* DENALI_CTL_128_DATA */
+			0x000d0404,	/* DENALI_CTL_129_DATA */
+			0x00000000,	/* DENALI_CTL_130_DATA */
+			0x00000000,	/* DENALI_CTL_131_DATA */
+			0x00000000,	/* DENALI_CTL_132_DATA */
+			0x001400a3,	/* DENALI_CTL_133_DATA */
+			0x00e30009,	/* DENALI_CTL_134_DATA */
+			0x00120024,	/* DENALI_CTL_135_DATA */
+			0x00040063,	/* DENALI_CTL_136_DATA */
+			0x00000000,	/* DENALI_CTL_137_DATA */
+			0x00310031,	/* DENALI_CTL_138_DATA */
+			0x00000031,	/* DENALI_CTL_139_DATA */
+			0x004d0000,	/* DENALI_CTL_140_DATA */
+			0x004d004d,	/* DENALI_CTL_141_DATA */
+			0x004d0000,	/* DENALI_CTL_142_DATA */
+			0x004d004d,	/* DENALI_CTL_143_DATA */
+			0x00010101,	/* DENALI_CTL_144_DATA */
+			0x00000000,	/* DENALI_CTL_145_DATA */
+			0x00000000,	/* DENALI_CTL_146_DATA */
+			0x001400a3,	/* DENALI_CTL_147_DATA */
+			0x00e30009,	/* DENALI_CTL_148_DATA */
+			0x00120024,	/* DENALI_CTL_149_DATA */
+			0x00040063,	/* DENALI_CTL_150_DATA */
+			0x00000000,	/* DENALI_CTL_151_DATA */
+			0x00310031,	/* DENALI_CTL_152_DATA */
+			0x00000031,	/* DENALI_CTL_153_DATA */
+			0x004d0000,	/* DENALI_CTL_154_DATA */
+			0x004d004d,	/* DENALI_CTL_155_DATA */
+			0x004d0000,	/* DENALI_CTL_156_DATA */
+			0x004d004d,	/* DENALI_CTL_157_DATA */
+			0x00010101,	/* DENALI_CTL_158_DATA */
+			0x00000000,	/* DENALI_CTL_159_DATA */
+			0x00000000,	/* DENALI_CTL_160_DATA */
+			0x00000000,	/* DENALI_CTL_161_DATA */
+			0x00000001,	/* DENALI_CTL_162_DATA */
+			0x00000000,	/* DENALI_CTL_163_DATA */
+			0x18151100,	/* DENALI_CTL_164_DATA */
+			0x0000000c,	/* DENALI_CTL_165_DATA */
+			0x00000000,	/* DENALI_CTL_166_DATA */
+			0x00000000,	/* DENALI_CTL_167_DATA */
+			0x00000000,	/* DENALI_CTL_168_DATA */
+			0x00000000,	/* DENALI_CTL_169_DATA */
+			0x00000000,	/* DENALI_CTL_170_DATA */
+			0x00000000,	/* DENALI_CTL_171_DATA */
+			0x00000000,	/* DENALI_CTL_172_DATA */
+			0x00000000,	/* DENALI_CTL_173_DATA */
+			0x00000000,	/* DENALI_CTL_174_DATA */
+			0x00000000,	/* DENALI_CTL_175_DATA */
+			0x00000000,	/* DENALI_CTL_176_DATA */
+			0x00000000,	/* DENALI_CTL_177_DATA */
+			0x00000000,	/* DENALI_CTL_178_DATA */
+			0x00020003,	/* DENALI_CTL_179_DATA */
+			0x00400100,	/* DENALI_CTL_180_DATA */
+			0x000c0190,	/* DENALI_CTL_181_DATA */
+			0x01000200,	/* DENALI_CTL_182_DATA */
+			0x03200040,	/* DENALI_CTL_183_DATA */
+			0x00020018,	/* DENALI_CTL_184_DATA */
+			0x00400100,	/* DENALI_CTL_185_DATA */
+			0x00080032,	/* DENALI_CTL_186_DATA */
+			0x00140000,	/* DENALI_CTL_187_DATA */
+			0x00030028,	/* DENALI_CTL_188_DATA */
+			0x01010100,	/* DENALI_CTL_189_DATA */
+			0x02000202,	/* DENALI_CTL_190_DATA */
+			0x0b000002,	/* DENALI_CTL_191_DATA */
+			0x01000f0f,	/* DENALI_CTL_192_DATA */
+			0x00000000,	/* DENALI_CTL_193_DATA */
+			0x00000000,	/* DENALI_CTL_194_DATA */
+			0x00010003,	/* DENALI_CTL_195_DATA */
+			0x00000c03,	/* DENALI_CTL_196_DATA */
+			0x00040101,	/* DENALI_CTL_197_DATA */
+			0x04010100,	/* DENALI_CTL_198_DATA */
+			0x01000000,	/* DENALI_CTL_199_DATA */
+			0x02010000,	/* DENALI_CTL_200_DATA */
+			0x00000001,	/* DENALI_CTL_201_DATA */
+			0x00000000,	/* DENALI_CTL_202_DATA */
+			0x00000000,	/* DENALI_CTL_203_DATA */
+			0x00000000,	/* DENALI_CTL_204_DATA */
+			0x00000000,	/* DENALI_CTL_205_DATA */
+			0x00000000,	/* DENALI_CTL_206_DATA */
+			0x00000000,	/* DENALI_CTL_207_DATA */
+			0x00000000,	/* DENALI_CTL_208_DATA */
+			0x00000000,	/* DENALI_CTL_209_DATA */
+			0x00000000,	/* DENALI_CTL_210_DATA */
+			0x00010000,	/* DENALI_CTL_211_DATA */
+			0x00000001,	/* DENALI_CTL_212_DATA */
+			0x01010001,	/* DENALI_CTL_213_DATA */
+			0x05040001,	/* DENALI_CTL_214_DATA */
+			0x040a0703,	/* DENALI_CTL_215_DATA */
+			0x02080808,	/* DENALI_CTL_216_DATA */
+			0x020e000a,	/* DENALI_CTL_217_DATA */
+			0x020f010b,	/* DENALI_CTL_218_DATA */
+			0x000d0008,	/* DENALI_CTL_219_DATA */
+			0x00080b0a,	/* DENALI_CTL_220_DATA */
+			0x03000200,	/* DENALI_CTL_221_DATA */
+			0x00000100,	/* DENALI_CTL_222_DATA */
+			0x00000000,	/* DENALI_CTL_223_DATA */
+			0x00000000,	/* DENALI_CTL_224_DATA */
+			0x0d000001,	/* DENALI_CTL_225_DATA */
+			0x00000028,	/* DENALI_CTL_226_DATA */
+			0x00010000,	/* DENALI_CTL_227_DATA */
+			0x00000003,	/* DENALI_CTL_228_DATA */
+			0x00000000,	/* DENALI_CTL_229_DATA */
+			0x00000000,	/* DENALI_CTL_230_DATA */
+			0x00000000,	/* DENALI_CTL_231_DATA */
+			0x00000000,	/* DENALI_CTL_232_DATA */
+			0x00000000,	/* DENALI_CTL_233_DATA */
+			0x00000000,	/* DENALI_CTL_234_DATA */
+			0x00000000,	/* DENALI_CTL_235_DATA */
+			0x00000000,	/* DENALI_CTL_236_DATA */
+			0x00010100,	/* DENALI_CTL_237_DATA */
+			0x01000000,	/* DENALI_CTL_238_DATA */
+			0x00000001,	/* DENALI_CTL_239_DATA */
+			0x00000303,	/* DENALI_CTL_240_DATA */
+			0x00000000,	/* DENALI_CTL_241_DATA */
+			0x00000000,	/* DENALI_CTL_242_DATA */
+			0x00000000,	/* DENALI_CTL_243_DATA */
+			0x00000000,	/* DENALI_CTL_244_DATA */
+			0x00000000,	/* DENALI_CTL_245_DATA */
+			0x00000000,	/* DENALI_CTL_246_DATA */
+			0x00000000,	/* DENALI_CTL_247_DATA */
+			0x00000000,	/* DENALI_CTL_248_DATA */
+			0x00000000,	/* DENALI_CTL_249_DATA */
+			0x00000000,	/* DENALI_CTL_250_DATA */
+			0x00000000,	/* DENALI_CTL_251_DATA */
+			0x00000000,	/* DENALI_CTL_252_DATA */
+			0x00000000,	/* DENALI_CTL_253_DATA */
+			0x00000000,	/* DENALI_CTL_254_DATA */
+			0x00000000,	/* DENALI_CTL_255_DATA */
+			0x000556aa,	/* DENALI_CTL_256_DATA */
+			0x000aaaaa,	/* DENALI_CTL_257_DATA */
+			0x000aa955,	/* DENALI_CTL_258_DATA */
+			0x00055555,	/* DENALI_CTL_259_DATA */
+			0x000b3133,	/* DENALI_CTL_260_DATA */
+			0x0004cd33,	/* DENALI_CTL_261_DATA */
+			0x0004cecc,	/* DENALI_CTL_262_DATA */
+			0x000b32cc,	/* DENALI_CTL_263_DATA */
+			0x00010300,	/* DENALI_CTL_264_DATA */
+			0x03000100,	/* DENALI_CTL_265_DATA */
+			0x00000000,	/* DENALI_CTL_266_DATA */
+			0x00000000,	/* DENALI_CTL_267_DATA */
+			0x00000000,	/* DENALI_CTL_268_DATA */
+			0x00000000,	/* DENALI_CTL_269_DATA */
+			0x00000000,	/* DENALI_CTL_270_DATA */
+			0x00000000,	/* DENALI_CTL_271_DATA */
+			0x00000000,	/* DENALI_CTL_272_DATA */
+			0x00000000,	/* DENALI_CTL_273_DATA */
+			0x00ffff00,	/* DENALI_CTL_274_DATA */
+			0x1a160000,	/* DENALI_CTL_275_DATA */
+			0x08000012,	/* DENALI_CTL_276_DATA */
+			0x00000c20,	/* DENALI_CTL_277_DATA */
+			0x00000200,	/* DENALI_CTL_278_DATA */
+			0x00000200,	/* DENALI_CTL_279_DATA */
+			0x00000200,	/* DENALI_CTL_280_DATA */
+			0x00000200,	/* DENALI_CTL_281_DATA */
+			0x00000c20,	/* DENALI_CTL_282_DATA */
+			0x00007940,	/* DENALI_CTL_283_DATA */
+			0x18500409,	/* DENALI_CTL_284_DATA */
+			0x00000200,	/* DENALI_CTL_285_DATA */
+			0x00000200,	/* DENALI_CTL_286_DATA */
+			0x00000200,	/* DENALI_CTL_287_DATA */
+			0x00000200,	/* DENALI_CTL_288_DATA */
+			0x00001850,	/* DENALI_CTL_289_DATA */
+			0x0000f320,	/* DENALI_CTL_290_DATA */
+			0x0176060c,	/* DENALI_CTL_291_DATA */
+			0x00000200,	/* DENALI_CTL_292_DATA */
+			0x00000200,	/* DENALI_CTL_293_DATA */
+			0x00000200,	/* DENALI_CTL_294_DATA */
+			0x00000200,	/* DENALI_CTL_295_DATA */
+			0x00000176,	/* DENALI_CTL_296_DATA */
+			0x00000e9c,	/* DENALI_CTL_297_DATA */
+			0x02020205,	/* DENALI_CTL_298_DATA */
+			0x03030202,	/* DENALI_CTL_299_DATA */
+			0x00000018,	/* DENALI_CTL_300_DATA */
+			0x00000000,	/* DENALI_CTL_301_DATA */
+			0x00000000,	/* DENALI_CTL_302_DATA */
+			0x00001403,	/* DENALI_CTL_303_DATA */
+			0x00000000,	/* DENALI_CTL_304_DATA */
+			0x00000000,	/* DENALI_CTL_305_DATA */
+			0x00000000,	/* DENALI_CTL_306_DATA */
+			0x00030000,	/* DENALI_CTL_307_DATA */
+			0x000a001c,	/* DENALI_CTL_308_DATA */
+			0x000e0020,	/* DENALI_CTL_309_DATA */
+			0x00060018,	/* DENALI_CTL_310_DATA */
+			0x00000000,	/* DENALI_CTL_311_DATA */
+			0x00000000,	/* DENALI_CTL_312_DATA */
+			0x02000000,	/* DENALI_CTL_313_DATA */
+			0x00090305,	/* DENALI_CTL_314_DATA */
+			0x00050101,	/* DENALI_CTL_315_DATA */
+			0x00000000,	/* DENALI_CTL_316_DATA */
+			0x00000000,	/* DENALI_CTL_317_DATA */
+			0x00000000,	/* DENALI_CTL_318_DATA */
+			0x00000000,	/* DENALI_CTL_319_DATA */
+			0x00000000,	/* DENALI_CTL_320_DATA */
+			0x00000000,	/* DENALI_CTL_321_DATA */
+			0x00000000,	/* DENALI_CTL_322_DATA */
+			0x00000000,	/* DENALI_CTL_323_DATA */
+			0x01000001,	/* DENALI_CTL_324_DATA */
+			0x01010101,	/* DENALI_CTL_325_DATA */
+			0x01000101,	/* DENALI_CTL_326_DATA */
+			0x01000100,	/* DENALI_CTL_327_DATA */
+			0x00010001,	/* DENALI_CTL_328_DATA */
+			0x00010002,	/* DENALI_CTL_329_DATA */
+			0x00020100,	/* DENALI_CTL_330_DATA */
+			0x00000002	/* DENALI_CTL_331_DATA */
+		}
+	},
+	{
+		{
+			0x00000b00,	/* DENALI_PI_00_DATA */
+			0x00000000,	/* DENALI_PI_01_DATA */
+			0x000002ec,	/* DENALI_PI_02_DATA */
+			0x00000176,	/* DENALI_PI_03_DATA */
+			0x000030a0,	/* DENALI_PI_04_DATA */
+			0x00001850,	/* DENALI_PI_05_DATA */
+			0x00001840,	/* DENALI_PI_06_DATA */
+			0x01760c20,	/* DENALI_PI_07_DATA */
+			0x00000200,	/* DENALI_PI_08_DATA */
+			0x00000200,	/* DENALI_PI_09_DATA */
+			0x00000200,	/* DENALI_PI_10_DATA */
+			0x00000200,	/* DENALI_PI_11_DATA */
+			0x00001850,	/* DENALI_PI_12_DATA */
+			0x00000200,	/* DENALI_PI_13_DATA */
+			0x00000200,	/* DENALI_PI_14_DATA */
+			0x00000200,	/* DENALI_PI_15_DATA */
+			0x00000200,	/* DENALI_PI_16_DATA */
+			0x00000c20,	/* DENALI_PI_17_DATA */
+			0x00000200,	/* DENALI_PI_18_DATA */
+			0x00000200,	/* DENALI_PI_19_DATA */
+			0x00000200,	/* DENALI_PI_20_DATA */
+			0x00000200,	/* DENALI_PI_21_DATA */
+			0x00010000,	/* DENALI_PI_22_DATA */
+			0x00000007,	/* DENALI_PI_23_DATA */
+			0x01000001,	/* DENALI_PI_24_DATA */
+			0x00000000,	/* DENALI_PI_25_DATA */
+			0x3fffffff,	/* DENALI_PI_26_DATA */
+			0x00000000,	/* DENALI_PI_27_DATA */
+			0x00000000,	/* DENALI_PI_28_DATA */
+			0x00000000,	/* DENALI_PI_29_DATA */
+			0x00000000,	/* DENALI_PI_30_DATA */
+			0x00000000,	/* DENALI_PI_31_DATA */
+			0x00000000,	/* DENALI_PI_32_DATA */
+			0x00000000,	/* DENALI_PI_33_DATA */
+			0x00000000,	/* DENALI_PI_34_DATA */
+			0x00000000,	/* DENALI_PI_35_DATA */
+			0x00000000,	/* DENALI_PI_36_DATA */
+			0x00000000,	/* DENALI_PI_37_DATA */
+			0x00000000,	/* DENALI_PI_38_DATA */
+			0x00000000,	/* DENALI_PI_39_DATA */
+			0x00000000,	/* DENALI_PI_40_DATA */
+			0x0f000101,	/* DENALI_PI_41_DATA */
+			0x082b3223,	/* DENALI_PI_42_DATA */
+			0x080c0004,	/* DENALI_PI_43_DATA */
+			0x00061c00,	/* DENALI_PI_44_DATA */
+			0x00000214,	/* DENALI_PI_45_DATA */
+			0x00bb0007,	/* DENALI_PI_46_DATA */
+			0x0c280068,	/* DENALI_PI_47_DATA */
+			0x06100034,	/* DENALI_PI_48_DATA */
+			0x00000500,	/* DENALI_PI_49_DATA */
+			0x00000000,	/* DENALI_PI_50_DATA */
+			0x00000000,	/* DENALI_PI_51_DATA */
+			0x00000000,	/* DENALI_PI_52_DATA */
+			0x00000000,	/* DENALI_PI_53_DATA */
+			0x00000000,	/* DENALI_PI_54_DATA */
+			0x00000000,	/* DENALI_PI_55_DATA */
+			0x00000000,	/* DENALI_PI_56_DATA */
+			0x00000000,	/* DENALI_PI_57_DATA */
+			0x04040100,	/* DENALI_PI_58_DATA */
+			0x0a000004,	/* DENALI_PI_59_DATA */
+			0x00000128,	/* DENALI_PI_60_DATA */
+			0x00000000,	/* DENALI_PI_61_DATA */
+			0x0003000f,	/* DENALI_PI_62_DATA */
+			0x00000018,	/* DENALI_PI_63_DATA */
+			0x00000000,	/* DENALI_PI_64_DATA */
+			0x00000000,	/* DENALI_PI_65_DATA */
+			0x00060002,	/* DENALI_PI_66_DATA */
+			0x00010001,	/* DENALI_PI_67_DATA */
+			0x00000101,	/* DENALI_PI_68_DATA */
+			0x00020001,	/* DENALI_PI_69_DATA */
+			0x00080004,	/* DENALI_PI_70_DATA */
+			0x00000000,	/* DENALI_PI_71_DATA */
+			0x05030000,	/* DENALI_PI_72_DATA */
+			0x070a0404,	/* DENALI_PI_73_DATA */
+			0x00000000,	/* DENALI_PI_74_DATA */
+			0x00000000,	/* DENALI_PI_75_DATA */
+			0x00000000,	/* DENALI_PI_76_DATA */
+			0x000f0f00,	/* DENALI_PI_77_DATA */
+			0x0000001e,	/* DENALI_PI_78_DATA */
+			0x00000000,	/* DENALI_PI_79_DATA */
+			0x01010300,	/* DENALI_PI_80_DATA */
+			0x00000000,	/* DENALI_PI_81_DATA */
+			0x00000000,	/* DENALI_PI_82_DATA */
+			0x01000000,	/* DENALI_PI_83_DATA */
+			0x00000101,	/* DENALI_PI_84_DATA */
+			0x55555a5a,	/* DENALI_PI_85_DATA */
+			0x55555a5a,	/* DENALI_PI_86_DATA */
+			0x55555a5a,	/* DENALI_PI_87_DATA */
+			0x55555a5a,	/* DENALI_PI_88_DATA */
+			0x0c050001,	/* DENALI_PI_89_DATA */
+			0x06020009,	/* DENALI_PI_90_DATA */
+			0x00010004,	/* DENALI_PI_91_DATA */
+			0x00000203,	/* DENALI_PI_92_DATA */
+			0x00030000,	/* DENALI_PI_93_DATA */
+			0x170f0000,	/* DENALI_PI_94_DATA */
+			0x00060018,	/* DENALI_PI_95_DATA */
+			0x000e0020,	/* DENALI_PI_96_DATA */
+			0x000a001c,	/* DENALI_PI_97_DATA */
+			0x00000000,	/* DENALI_PI_98_DATA */
+			0x00000000,	/* DENALI_PI_99_DATA */
+			0x00000100,	/* DENALI_PI_100_DATA */
+			0x140a0000,	/* DENALI_PI_101_DATA */
+			0x000d010a,	/* DENALI_PI_102_DATA */
+			0x0100c802,	/* DENALI_PI_103_DATA */
+			0x010a0064,	/* DENALI_PI_104_DATA */
+			0x000e0100,	/* DENALI_PI_105_DATA */
+			0x0100000e,	/* DENALI_PI_106_DATA */
+			0x00c900c9,	/* DENALI_PI_107_DATA */
+			0x00650100,	/* DENALI_PI_108_DATA */
+			0x1e1a0065,	/* DENALI_PI_109_DATA */
+			0x10010204,	/* DENALI_PI_110_DATA */
+			0x06070605,	/* DENALI_PI_111_DATA */
+			0x20000202,	/* DENALI_PI_112_DATA */
+			0x00201000,	/* DENALI_PI_113_DATA */
+			0x00201000,	/* DENALI_PI_114_DATA */
+			0x04041000,	/* DENALI_PI_115_DATA */
+			0x10020100,	/* DENALI_PI_116_DATA */
+			0x0003010c,	/* DENALI_PI_117_DATA */
+			0x004b004a,	/* DENALI_PI_118_DATA */
+			0x1a0f0000,	/* DENALI_PI_119_DATA */
+			0x0102041e,	/* DENALI_PI_120_DATA */
+			0x34000000,	/* DENALI_PI_121_DATA */
+			0x00000000,	/* DENALI_PI_122_DATA */
+			0x00000000,	/* DENALI_PI_123_DATA */
+			0x00010000,	/* DENALI_PI_124_DATA */
+			0x00000400,	/* DENALI_PI_125_DATA */
+			0x00310000,	/* DENALI_PI_126_DATA */
+			0x004d4d00,	/* DENALI_PI_127_DATA */
+			0x00120024,	/* DENALI_PI_128_DATA */
+			0x4d000031,	/* DENALI_PI_129_DATA */
+			0x0000144d,	/* DENALI_PI_130_DATA */
+			0x00310009,	/* DENALI_PI_131_DATA */
+			0x004d4d00,	/* DENALI_PI_132_DATA */
+			0x00000004,	/* DENALI_PI_133_DATA */
+			0x4d000031,	/* DENALI_PI_134_DATA */
+			0x0000244d,	/* DENALI_PI_135_DATA */
+			0x00310012,	/* DENALI_PI_136_DATA */
+			0x004d4d00,	/* DENALI_PI_137_DATA */
+			0x00090014,	/* DENALI_PI_138_DATA */
+			0x4d000031,	/* DENALI_PI_139_DATA */
+			0x0004004d,	/* DENALI_PI_140_DATA */
+			0x00310000,	/* DENALI_PI_141_DATA */
+			0x004d4d00,	/* DENALI_PI_142_DATA */
+			0x00120024,	/* DENALI_PI_143_DATA */
+			0x4d000031,	/* DENALI_PI_144_DATA */
+			0x0000144d,	/* DENALI_PI_145_DATA */
+			0x00310009,	/* DENALI_PI_146_DATA */
+			0x004d4d00,	/* DENALI_PI_147_DATA */
+			0x00000004,	/* DENALI_PI_148_DATA */
+			0x4d000031,	/* DENALI_PI_149_DATA */
+			0x0000244d,	/* DENALI_PI_150_DATA */
+			0x00310012,	/* DENALI_PI_151_DATA */
+			0x004d4d00,	/* DENALI_PI_152_DATA */
+			0x00090014,	/* DENALI_PI_153_DATA */
+			0x4d000031,	/* DENALI_PI_154_DATA */
+			0x0200004d,	/* DENALI_PI_155_DATA */
+			0x00c8000d,	/* DENALI_PI_156_DATA */
+			0x08080064,	/* DENALI_PI_157_DATA */
+			0x040a0404,	/* DENALI_PI_158_DATA */
+			0x03000d92,	/* DENALI_PI_159_DATA */
+			0x010a2001,	/* DENALI_PI_160_DATA */
+			0x0f11080a,	/* DENALI_PI_161_DATA */
+			0x0000110a,	/* DENALI_PI_162_DATA */
+			0x2200d92e,	/* DENALI_PI_163_DATA */
+			0x080c2003,	/* DENALI_PI_164_DATA */
+			0x0809080a,	/* DENALI_PI_165_DATA */
+			0x00000a0a,	/* DENALI_PI_166_DATA */
+			0x11006c97,	/* DENALI_PI_167_DATA */
+			0x040a2002,	/* DENALI_PI_168_DATA */
+			0x0200020a,	/* DENALI_PI_169_DATA */
+			0x02000200,	/* DENALI_PI_170_DATA */
+			0x02000200,	/* DENALI_PI_171_DATA */
+			0x02000200,	/* DENALI_PI_172_DATA */
+			0x02000200,	/* DENALI_PI_173_DATA */
+			0x00000000,	/* DENALI_PI_174_DATA */
+			0x00000000,	/* DENALI_PI_175_DATA */
+			0x00000000,	/* DENALI_PI_176_DATA */
+			0x00000000,	/* DENALI_PI_177_DATA */
+			0x00000000,	/* DENALI_PI_178_DATA */
+			0x00000000,	/* DENALI_PI_179_DATA */
+			0x00000000,	/* DENALI_PI_180_DATA */
+			0x00000000,	/* DENALI_PI_181_DATA */
+			0x00000000,	/* DENALI_PI_182_DATA */
+			0x00000000,	/* DENALI_PI_183_DATA */
+			0x00000000,	/* DENALI_PI_184_DATA */
+			0x00000000,	/* DENALI_PI_185_DATA */
+			0x01000400,	/* DENALI_PI_186_DATA */
+			0x00017600,	/* DENALI_PI_187_DATA */
+			0x00000e9c,	/* DENALI_PI_188_DATA */
+			0x00001850,	/* DENALI_PI_189_DATA */
+			0x0000f320,	/* DENALI_PI_190_DATA */
+			0x00000c20,	/* DENALI_PI_191_DATA */
+			0x00007940,	/* DENALI_PI_192_DATA */
+			0x08000000,	/* DENALI_PI_193_DATA */
+			0x00000100,	/* DENALI_PI_194_DATA */
+			0x00000000,	/* DENALI_PI_195_DATA */
+			0x00000000,	/* DENALI_PI_196_DATA */
+			0x00000000,	/* DENALI_PI_197_DATA */
+			0x00000000,	/* DENALI_PI_198_DATA */
+			0x00000002	/* DENALI_PI_199_DATA */
+		}
+	},
+	{
+		{
+			0x76543210,	/* DENALI_PHY_00_DATA */
+			0x0004f008,	/* DENALI_PHY_01_DATA */
+			0x00020119,	/* DENALI_PHY_02_DATA */
+			0x00000000,	/* DENALI_PHY_03_DATA */
+			0x00000000,	/* DENALI_PHY_04_DATA */
+			0x00010000,	/* DENALI_PHY_05_DATA */
+			0x01665555,	/* DENALI_PHY_06_DATA */
+			0x03665555,	/* DENALI_PHY_07_DATA */
+			0x00010f00,	/* DENALI_PHY_08_DATA */
+			0x05010200,	/* DENALI_PHY_09_DATA */
+			0x00000002,	/* DENALI_PHY_10_DATA */
+			0x00170180,	/* DENALI_PHY_11_DATA */
+			0x00cc0201,	/* DENALI_PHY_12_DATA */
+			0x00030066,	/* DENALI_PHY_13_DATA */
+			0x00000000,	/* DENALI_PHY_14_DATA */
+			0x00000000,	/* DENALI_PHY_15_DATA */
+			0x00000000,	/* DENALI_PHY_16_DATA */
+			0x00000000,	/* DENALI_PHY_17_DATA */
+			0x00000000,	/* DENALI_PHY_18_DATA */
+			0x00000000,	/* DENALI_PHY_19_DATA */
+			0x00000000,	/* DENALI_PHY_20_DATA */
+			0x00000000,	/* DENALI_PHY_21_DATA */
+			0x04080000,	/* DENALI_PHY_22_DATA */
+			0x04080400,	/* DENALI_PHY_23_DATA */
+			0x30000000,	/* DENALI_PHY_24_DATA */
+			0x0c00c007,	/* DENALI_PHY_25_DATA */
+			0x00000100,	/* DENALI_PHY_26_DATA */
+			0x00000000,	/* DENALI_PHY_27_DATA */
+			0xfd02fe01,	/* DENALI_PHY_28_DATA */
+			0xf708fb04,	/* DENALI_PHY_29_DATA */
+			0xdf20ef10,	/* DENALI_PHY_30_DATA */
+			0x7f80bf40,	/* DENALI_PHY_31_DATA */
+			0x0001aaaa,	/* DENALI_PHY_32_DATA */
+			0x00000000,	/* DENALI_PHY_33_DATA */
+			0x00000000,	/* DENALI_PHY_34_DATA */
+			0x00000000,	/* DENALI_PHY_35_DATA */
+			0x00000000,	/* DENALI_PHY_36_DATA */
+			0x00000000,	/* DENALI_PHY_37_DATA */
+			0x00000000,	/* DENALI_PHY_38_DATA */
+			0x00000000,	/* DENALI_PHY_39_DATA */
+			0x00000000,	/* DENALI_PHY_40_DATA */
+			0x00000000,	/* DENALI_PHY_41_DATA */
+			0x00000000,	/* DENALI_PHY_42_DATA */
+			0x00000000,	/* DENALI_PHY_43_DATA */
+			0x00000000,	/* DENALI_PHY_44_DATA */
+			0x00000000,	/* DENALI_PHY_45_DATA */
+			0x00000000,	/* DENALI_PHY_46_DATA */
+			0x00000000,	/* DENALI_PHY_47_DATA */
+			0x00000000,	/* DENALI_PHY_48_DATA */
+			0x00000000,	/* DENALI_PHY_49_DATA */
+			0x00000000,	/* DENALI_PHY_50_DATA */
+			0x00000000,	/* DENALI_PHY_51_DATA */
+			0x00200000,	/* DENALI_PHY_52_DATA */
+			0x00000000,	/* DENALI_PHY_53_DATA */
+			0x00000000,	/* DENALI_PHY_54_DATA */
+			0x00000000,	/* DENALI_PHY_55_DATA */
+			0x00000000,	/* DENALI_PHY_56_DATA */
+			0x00000000,	/* DENALI_PHY_57_DATA */
+			0x00000000,	/* DENALI_PHY_58_DATA */
+			0x02800280,	/* DENALI_PHY_59_DATA */
+			0x02800280,	/* DENALI_PHY_60_DATA */
+			0x02800280,	/* DENALI_PHY_61_DATA */
+			0x02800280,	/* DENALI_PHY_62_DATA */
+			0x00000280,	/* DENALI_PHY_63_DATA */
+			0x00000000,	/* DENALI_PHY_64_DATA */
+			0x00000000,	/* DENALI_PHY_65_DATA */
+			0x00000000,	/* DENALI_PHY_66_DATA */
+			0x00000000,	/* DENALI_PHY_67_DATA */
+			0x00800000,	/* DENALI_PHY_68_DATA */
+			0x00800080,	/* DENALI_PHY_69_DATA */
+			0x00800080,	/* DENALI_PHY_70_DATA */
+			0x00800080,	/* DENALI_PHY_71_DATA */
+			0x00800080,	/* DENALI_PHY_72_DATA */
+			0x00800080,	/* DENALI_PHY_73_DATA */
+			0x00800080,	/* DENALI_PHY_74_DATA */
+			0x00800080,	/* DENALI_PHY_75_DATA */
+			0x00800080,	/* DENALI_PHY_76_DATA */
+			0x01190080,	/* DENALI_PHY_77_DATA */
+			0x00000002,	/* DENALI_PHY_78_DATA */
+			0x00000000,	/* DENALI_PHY_79_DATA */
+			0x00000000,	/* DENALI_PHY_80_DATA */
+			0x00000200,	/* DENALI_PHY_81_DATA */
+			0x00000000,	/* DENALI_PHY_82_DATA */
+			0x51315152,	/* DENALI_PHY_83_DATA */
+			0xc0013150,	/* DENALI_PHY_84_DATA */
+			0x020000c0,	/* DENALI_PHY_85_DATA */
+			0x00100001,	/* DENALI_PHY_86_DATA */
+			0x07054204,	/* DENALI_PHY_87_DATA */
+			0x000f0c18,	/* DENALI_PHY_88_DATA */
+			0x01000140,	/* DENALI_PHY_89_DATA */
+			0x00000c10,	/* DENALI_PHY_90_DATA */
+			0x00000000,	/* DENALI_PHY_91_DATA */
+			0x00000000,	/* DENALI_PHY_92_DATA */
+			0x00000000,	/* DENALI_PHY_93_DATA */
+			0x00000000,	/* DENALI_PHY_94_DATA */
+			0x00000000,	/* DENALI_PHY_95_DATA */
+			0x00000000,	/* DENALI_PHY_96_DATA */
+			0x00000000,	/* DENALI_PHY_97_DATA */
+			0x00000000,	/* DENALI_PHY_98_DATA */
+			0x00000000,	/* DENALI_PHY_99_DATA */
+			0x00000000,	/* DENALI_PHY_100_DATA */
+			0x00000000,	/* DENALI_PHY_101_DATA */
+			0x00000000,	/* DENALI_PHY_102_DATA */
+			0x00000000,	/* DENALI_PHY_103_DATA */
+			0x00000000,	/* DENALI_PHY_104_DATA */
+			0x00000000,	/* DENALI_PHY_105_DATA */
+			0x00000000,	/* DENALI_PHY_106_DATA */
+			0x00000000,	/* DENALI_PHY_107_DATA */
+			0x00000000,	/* DENALI_PHY_108_DATA */
+			0x00000000,	/* DENALI_PHY_109_DATA */
+			0x00000000,	/* DENALI_PHY_110_DATA */
+			0x00000000,	/* DENALI_PHY_111_DATA */
+			0x00000000,	/* DENALI_PHY_112_DATA */
+			0x00000000,	/* DENALI_PHY_113_DATA */
+			0x00000000,	/* DENALI_PHY_114_DATA */
+			0x00000000,	/* DENALI_PHY_115_DATA */
+			0x00000000,	/* DENALI_PHY_116_DATA */
+			0x00000000,	/* DENALI_PHY_117_DATA */
+			0x00000000,	/* DENALI_PHY_118_DATA */
+			0x00000000,	/* DENALI_PHY_119_DATA */
+			0x00000000,	/* DENALI_PHY_120_DATA */
+			0x00000000,	/* DENALI_PHY_121_DATA */
+			0x00000000,	/* DENALI_PHY_122_DATA */
+			0x00000000,	/* DENALI_PHY_123_DATA */
+			0x00000000,	/* DENALI_PHY_124_DATA */
+			0x00000000,	/* DENALI_PHY_125_DATA */
+			0x00000000,	/* DENALI_PHY_126_DATA */
+			0x00000000,	/* DENALI_PHY_127_DATA */
+			0x76543210,	/* DENALI_PHY_128_DATA */
+			0x0004f008,	/* DENALI_PHY_129_DATA */
+			0x00020119,	/* DENALI_PHY_130_DATA */
+			0x00000000,	/* DENALI_PHY_131_DATA */
+			0x00000000,	/* DENALI_PHY_132_DATA */
+			0x00010000,	/* DENALI_PHY_133_DATA */
+			0x01665555,	/* DENALI_PHY_134_DATA */
+			0x03665555,	/* DENALI_PHY_135_DATA */
+			0x00010f00,	/* DENALI_PHY_136_DATA */
+			0x05010200,	/* DENALI_PHY_137_DATA */
+			0x00000002,	/* DENALI_PHY_138_DATA */
+			0x00170180,	/* DENALI_PHY_139_DATA */
+			0x00cc0201,	/* DENALI_PHY_140_DATA */
+			0x00030066,	/* DENALI_PHY_141_DATA */
+			0x00000000,	/* DENALI_PHY_142_DATA */
+			0x00000000,	/* DENALI_PHY_143_DATA */
+			0x00000000,	/* DENALI_PHY_144_DATA */
+			0x00000000,	/* DENALI_PHY_145_DATA */
+			0x00000000,	/* DENALI_PHY_146_DATA */
+			0x00000000,	/* DENALI_PHY_147_DATA */
+			0x00000000,	/* DENALI_PHY_148_DATA */
+			0x00000000,	/* DENALI_PHY_149_DATA */
+			0x04080000,	/* DENALI_PHY_150_DATA */
+			0x04080400,	/* DENALI_PHY_151_DATA */
+			0x30000000,	/* DENALI_PHY_152_DATA */
+			0x0c00c007,	/* DENALI_PHY_153_DATA */
+			0x00000100,	/* DENALI_PHY_154_DATA */
+			0x00000000,	/* DENALI_PHY_155_DATA */
+			0xfd02fe01,	/* DENALI_PHY_156_DATA */
+			0xf708fb04,	/* DENALI_PHY_157_DATA */
+			0xdf20ef10,	/* DENALI_PHY_158_DATA */
+			0x7f80bf40,	/* DENALI_PHY_159_DATA */
+			0x0000aaaa,	/* DENALI_PHY_160_DATA */
+			0x00000000,	/* DENALI_PHY_161_DATA */
+			0x00000000,	/* DENALI_PHY_162_DATA */
+			0x00000000,	/* DENALI_PHY_163_DATA */
+			0x00000000,	/* DENALI_PHY_164_DATA */
+			0x00000000,	/* DENALI_PHY_165_DATA */
+			0x00000000,	/* DENALI_PHY_166_DATA */
+			0x00000000,	/* DENALI_PHY_167_DATA */
+			0x00000000,	/* DENALI_PHY_168_DATA */
+			0x00000000,	/* DENALI_PHY_169_DATA */
+			0x00000000,	/* DENALI_PHY_170_DATA */
+			0x00000000,	/* DENALI_PHY_171_DATA */
+			0x00000000,	/* DENALI_PHY_172_DATA */
+			0x00000000,	/* DENALI_PHY_173_DATA */
+			0x00000000,	/* DENALI_PHY_174_DATA */
+			0x00000000,	/* DENALI_PHY_175_DATA */
+			0x00000000,	/* DENALI_PHY_176_DATA */
+			0x00000000,	/* DENALI_PHY_177_DATA */
+			0x00000000,	/* DENALI_PHY_178_DATA */
+			0x00000000,	/* DENALI_PHY_179_DATA */
+			0x00200000,	/* DENALI_PHY_180_DATA */
+			0x00000000,	/* DENALI_PHY_181_DATA */
+			0x00000000,	/* DENALI_PHY_182_DATA */
+			0x00000000,	/* DENALI_PHY_183_DATA */
+			0x00000000,	/* DENALI_PHY_184_DATA */
+			0x00000000,	/* DENALI_PHY_185_DATA */
+			0x00000000,	/* DENALI_PHY_186_DATA */
+			0x02800280,	/* DENALI_PHY_187_DATA */
+			0x02800280,	/* DENALI_PHY_188_DATA */
+			0x02800280,	/* DENALI_PHY_189_DATA */
+			0x02800280,	/* DENALI_PHY_190_DATA */
+			0x00000280,	/* DENALI_PHY_191_DATA */
+			0x00000000,	/* DENALI_PHY_192_DATA */
+			0x00000000,	/* DENALI_PHY_193_DATA */
+			0x00000000,	/* DENALI_PHY_194_DATA */
+			0x00000000,	/* DENALI_PHY_195_DATA */
+			0x00800000,	/* DENALI_PHY_196_DATA */
+			0x00800080,	/* DENALI_PHY_197_DATA */
+			0x00800080,	/* DENALI_PHY_198_DATA */
+			0x00800080,	/* DENALI_PHY_199_DATA */
+			0x00800080,	/* DENALI_PHY_200_DATA */
+			0x00800080,	/* DENALI_PHY_201_DATA */
+			0x00800080,	/* DENALI_PHY_202_DATA */
+			0x00800080,	/* DENALI_PHY_203_DATA */
+			0x00800080,	/* DENALI_PHY_204_DATA */
+			0x01190080,	/* DENALI_PHY_205_DATA */
+			0x00000002,	/* DENALI_PHY_206_DATA */
+			0x00000000,	/* DENALI_PHY_207_DATA */
+			0x00000000,	/* DENALI_PHY_208_DATA */
+			0x00000200,	/* DENALI_PHY_209_DATA */
+			0x00000000,	/* DENALI_PHY_210_DATA */
+			0x51315152,	/* DENALI_PHY_211_DATA */
+			0xc0013150,	/* DENALI_PHY_212_DATA */
+			0x020000c0,	/* DENALI_PHY_213_DATA */
+			0x00100001,	/* DENALI_PHY_214_DATA */
+			0x07054204,	/* DENALI_PHY_215_DATA */
+			0x000f0c18,	/* DENALI_PHY_216_DATA */
+			0x01000140,	/* DENALI_PHY_217_DATA */
+			0x00000c10,	/* DENALI_PHY_218_DATA */
+			0x00000000,	/* DENALI_PHY_219_DATA */
+			0x00000000,	/* DENALI_PHY_220_DATA */
+			0x00000000,	/* DENALI_PHY_221_DATA */
+			0x00000000,	/* DENALI_PHY_222_DATA */
+			0x00000000,	/* DENALI_PHY_223_DATA */
+			0x00000000,	/* DENALI_PHY_224_DATA */
+			0x00000000,	/* DENALI_PHY_225_DATA */
+			0x00000000,	/* DENALI_PHY_226_DATA */
+			0x00000000,	/* DENALI_PHY_227_DATA */
+			0x00000000,	/* DENALI_PHY_228_DATA */
+			0x00000000,	/* DENALI_PHY_229_DATA */
+			0x00000000,	/* DENALI_PHY_230_DATA */
+			0x00000000,	/* DENALI_PHY_231_DATA */
+			0x00000000,	/* DENALI_PHY_232_DATA */
+			0x00000000,	/* DENALI_PHY_233_DATA */
+			0x00000000,	/* DENALI_PHY_234_DATA */
+			0x00000000,	/* DENALI_PHY_235_DATA */
+			0x00000000,	/* DENALI_PHY_236_DATA */
+			0x00000000,	/* DENALI_PHY_237_DATA */
+			0x00000000,	/* DENALI_PHY_238_DATA */
+			0x00000000,	/* DENALI_PHY_239_DATA */
+			0x00000000,	/* DENALI_PHY_240_DATA */
+			0x00000000,	/* DENALI_PHY_241_DATA */
+			0x00000000,	/* DENALI_PHY_242_DATA */
+			0x00000000,	/* DENALI_PHY_243_DATA */
+			0x00000000,	/* DENALI_PHY_244_DATA */
+			0x00000000,	/* DENALI_PHY_245_DATA */
+			0x00000000,	/* DENALI_PHY_246_DATA */
+			0x00000000,	/* DENALI_PHY_247_DATA */
+			0x00000000,	/* DENALI_PHY_248_DATA */
+			0x00000000,	/* DENALI_PHY_249_DATA */
+			0x00000000,	/* DENALI_PHY_250_DATA */
+			0x00000000,	/* DENALI_PHY_251_DATA */
+			0x00000000,	/* DENALI_PHY_252_DATA */
+			0x00000000,	/* DENALI_PHY_253_DATA */
+			0x00000000,	/* DENALI_PHY_254_DATA */
+			0x00000000,	/* DENALI_PHY_255_DATA */
+			0x76543210,	/* DENALI_PHY_256_DATA */
+			0x0004f008,	/* DENALI_PHY_257_DATA */
+			0x00020119,	/* DENALI_PHY_258_DATA */
+			0x00000000,	/* DENALI_PHY_259_DATA */
+			0x00000000,	/* DENALI_PHY_260_DATA */
+			0x00010000,	/* DENALI_PHY_261_DATA */
+			0x01665555,	/* DENALI_PHY_262_DATA */
+			0x03665555,	/* DENALI_PHY_263_DATA */
+			0x00010f00,	/* DENALI_PHY_264_DATA */
+			0x05010200,	/* DENALI_PHY_265_DATA */
+			0x00000002,	/* DENALI_PHY_266_DATA */
+			0x00170180,	/* DENALI_PHY_267_DATA */
+			0x00cc0201,	/* DENALI_PHY_268_DATA */
+			0x00030066,	/* DENALI_PHY_269_DATA */
+			0x00000000,	/* DENALI_PHY_270_DATA */
+			0x00000000,	/* DENALI_PHY_271_DATA */
+			0x00000000,	/* DENALI_PHY_272_DATA */
+			0x00000000,	/* DENALI_PHY_273_DATA */
+			0x00000000,	/* DENALI_PHY_274_DATA */
+			0x00000000,	/* DENALI_PHY_275_DATA */
+			0x00000000,	/* DENALI_PHY_276_DATA */
+			0x00000000,	/* DENALI_PHY_277_DATA */
+			0x04080000,	/* DENALI_PHY_278_DATA */
+			0x04080400,	/* DENALI_PHY_279_DATA */
+			0x30000000,	/* DENALI_PHY_280_DATA */
+			0x0c00c007,	/* DENALI_PHY_281_DATA */
+			0x00000100,	/* DENALI_PHY_282_DATA */
+			0x00000000,	/* DENALI_PHY_283_DATA */
+			0xfd02fe01,	/* DENALI_PHY_284_DATA */
+			0xf708fb04,	/* DENALI_PHY_285_DATA */
+			0xdf20ef10,	/* DENALI_PHY_286_DATA */
+			0x7f80bf40,	/* DENALI_PHY_287_DATA */
+			0x0001aaaa,	/* DENALI_PHY_288_DATA */
+			0x00000000,	/* DENALI_PHY_289_DATA */
+			0x00000000,	/* DENALI_PHY_290_DATA */
+			0x00000000,	/* DENALI_PHY_291_DATA */
+			0x00000000,	/* DENALI_PHY_292_DATA */
+			0x00000000,	/* DENALI_PHY_293_DATA */
+			0x00000000,	/* DENALI_PHY_294_DATA */
+			0x00000000,	/* DENALI_PHY_295_DATA */
+			0x00000000,	/* DENALI_PHY_296_DATA */
+			0x00000000,	/* DENALI_PHY_297_DATA */
+			0x00000000,	/* DENALI_PHY_298_DATA */
+			0x00000000,	/* DENALI_PHY_299_DATA */
+			0x00000000,	/* DENALI_PHY_300_DATA */
+			0x00000000,	/* DENALI_PHY_301_DATA */
+			0x00000000,	/* DENALI_PHY_302_DATA */
+			0x00000000,	/* DENALI_PHY_303_DATA */
+			0x00000000,	/* DENALI_PHY_304_DATA */
+			0x00000000,	/* DENALI_PHY_305_DATA */
+			0x00000000,	/* DENALI_PHY_306_DATA */
+			0x00000000,	/* DENALI_PHY_307_DATA */
+			0x00200000,	/* DENALI_PHY_308_DATA */
+			0x00000000,	/* DENALI_PHY_309_DATA */
+			0x00000000,	/* DENALI_PHY_310_DATA */
+			0x00000000,	/* DENALI_PHY_311_DATA */
+			0x00000000,	/* DENALI_PHY_312_DATA */
+			0x00000000,	/* DENALI_PHY_313_DATA */
+			0x00000000,	/* DENALI_PHY_314_DATA */
+			0x02800280,	/* DENALI_PHY_315_DATA */
+			0x02800280,	/* DENALI_PHY_316_DATA */
+			0x02800280,	/* DENALI_PHY_317_DATA */
+			0x02800280,	/* DENALI_PHY_318_DATA */
+			0x00000280,	/* DENALI_PHY_319_DATA */
+			0x00000000,	/* DENALI_PHY_320_DATA */
+			0x00000000,	/* DENALI_PHY_321_DATA */
+			0x00000000,	/* DENALI_PHY_322_DATA */
+			0x00000000,	/* DENALI_PHY_323_DATA */
+			0x00800000,	/* DENALI_PHY_324_DATA */
+			0x00800080,	/* DENALI_PHY_325_DATA */
+			0x00800080,	/* DENALI_PHY_326_DATA */
+			0x00800080,	/* DENALI_PHY_327_DATA */
+			0x00800080,	/* DENALI_PHY_328_DATA */
+			0x00800080,	/* DENALI_PHY_329_DATA */
+			0x00800080,	/* DENALI_PHY_330_DATA */
+			0x00800080,	/* DENALI_PHY_331_DATA */
+			0x00800080,	/* DENALI_PHY_332_DATA */
+			0x01190080,	/* DENALI_PHY_333_DATA */
+			0x00000002,	/* DENALI_PHY_334_DATA */
+			0x00000000,	/* DENALI_PHY_335_DATA */
+			0x00000000,	/* DENALI_PHY_336_DATA */
+			0x00000200,	/* DENALI_PHY_337_DATA */
+			0x00000000,	/* DENALI_PHY_338_DATA */
+			0x51315152,	/* DENALI_PHY_339_DATA */
+			0xc0013150,	/* DENALI_PHY_340_DATA */
+			0x020000c0,	/* DENALI_PHY_341_DATA */
+			0x00100001,	/* DENALI_PHY_342_DATA */
+			0x07054204,	/* DENALI_PHY_343_DATA */
+			0x000f0c18,	/* DENALI_PHY_344_DATA */
+			0x01000140,	/* DENALI_PHY_345_DATA */
+			0x00000c10,	/* DENALI_PHY_346_DATA */
+			0x00000000,	/* DENALI_PHY_347_DATA */
+			0x00000000,	/* DENALI_PHY_348_DATA */
+			0x00000000,	/* DENALI_PHY_349_DATA */
+			0x00000000,	/* DENALI_PHY_350_DATA */
+			0x00000000,	/* DENALI_PHY_351_DATA */
+			0x00000000,	/* DENALI_PHY_352_DATA */
+			0x00000000,	/* DENALI_PHY_353_DATA */
+			0x00000000,	/* DENALI_PHY_354_DATA */
+			0x00000000,	/* DENALI_PHY_355_DATA */
+			0x00000000,	/* DENALI_PHY_356_DATA */
+			0x00000000,	/* DENALI_PHY_357_DATA */
+			0x00000000,	/* DENALI_PHY_358_DATA */
+			0x00000000,	/* DENALI_PHY_359_DATA */
+			0x00000000,	/* DENALI_PHY_360_DATA */
+			0x00000000,	/* DENALI_PHY_361_DATA */
+			0x00000000,	/* DENALI_PHY_362_DATA */
+			0x00000000,	/* DENALI_PHY_363_DATA */
+			0x00000000,	/* DENALI_PHY_364_DATA */
+			0x00000000,	/* DENALI_PHY_365_DATA */
+			0x00000000,	/* DENALI_PHY_366_DATA */
+			0x00000000,	/* DENALI_PHY_367_DATA */
+			0x00000000,	/* DENALI_PHY_368_DATA */
+			0x00000000,	/* DENALI_PHY_369_DATA */
+			0x00000000,	/* DENALI_PHY_370_DATA */
+			0x00000000,	/* DENALI_PHY_371_DATA */
+			0x00000000,	/* DENALI_PHY_372_DATA */
+			0x00000000,	/* DENALI_PHY_373_DATA */
+			0x00000000,	/* DENALI_PHY_374_DATA */
+			0x00000000,	/* DENALI_PHY_375_DATA */
+			0x00000000,	/* DENALI_PHY_376_DATA */
+			0x00000000,	/* DENALI_PHY_377_DATA */
+			0x00000000,	/* DENALI_PHY_378_DATA */
+			0x00000000,	/* DENALI_PHY_379_DATA */
+			0x00000000,	/* DENALI_PHY_380_DATA */
+			0x00000000,	/* DENALI_PHY_381_DATA */
+			0x00000000,	/* DENALI_PHY_382_DATA */
+			0x00000000,	/* DENALI_PHY_383_DATA */
+			0x76543210,	/* DENALI_PHY_384_DATA */
+			0x0004f008,	/* DENALI_PHY_385_DATA */
+			0x00020119,	/* DENALI_PHY_386_DATA */
+			0x00000000,	/* DENALI_PHY_387_DATA */
+			0x00000000,	/* DENALI_PHY_388_DATA */
+			0x00010000,	/* DENALI_PHY_389_DATA */
+			0x01665555,	/* DENALI_PHY_390_DATA */
+			0x03665555,	/* DENALI_PHY_391_DATA */
+			0x00010f00,	/* DENALI_PHY_392_DATA */
+			0x05010200,	/* DENALI_PHY_393_DATA */
+			0x00000002,	/* DENALI_PHY_394_DATA */
+			0x00170180,	/* DENALI_PHY_395_DATA */
+			0x00cc0201,	/* DENALI_PHY_396_DATA */
+			0x00030066,	/* DENALI_PHY_397_DATA */
+			0x00000000,	/* DENALI_PHY_398_DATA */
+			0x00000000,	/* DENALI_PHY_399_DATA */
+			0x00000000,	/* DENALI_PHY_400_DATA */
+			0x00000000,	/* DENALI_PHY_401_DATA */
+			0x00000000,	/* DENALI_PHY_402_DATA */
+			0x00000000,	/* DENALI_PHY_403_DATA */
+			0x00000000,	/* DENALI_PHY_404_DATA */
+			0x00000000,	/* DENALI_PHY_405_DATA */
+			0x04080000,	/* DENALI_PHY_406_DATA */
+			0x04080400,	/* DENALI_PHY_407_DATA */
+			0x30000000,	/* DENALI_PHY_408_DATA */
+			0x0c00c007,	/* DENALI_PHY_409_DATA */
+			0x00000100,	/* DENALI_PHY_410_DATA */
+			0x00000000,	/* DENALI_PHY_411_DATA */
+			0xfd02fe01,	/* DENALI_PHY_412_DATA */
+			0xf708fb04,	/* DENALI_PHY_413_DATA */
+			0xdf20ef10,	/* DENALI_PHY_414_DATA */
+			0x7f80bf40,	/* DENALI_PHY_415_DATA */
+			0x0000aaaa,	/* DENALI_PHY_416_DATA */
+			0x00000000,	/* DENALI_PHY_417_DATA */
+			0x00000000,	/* DENALI_PHY_418_DATA */
+			0x00000000,	/* DENALI_PHY_419_DATA */
+			0x00000000,	/* DENALI_PHY_420_DATA */
+			0x00000000,	/* DENALI_PHY_421_DATA */
+			0x00000000,	/* DENALI_PHY_422_DATA */
+			0x00000000,	/* DENALI_PHY_423_DATA */
+			0x00000000,	/* DENALI_PHY_424_DATA */
+			0x00000000,	/* DENALI_PHY_425_DATA */
+			0x00000000,	/* DENALI_PHY_426_DATA */
+			0x00000000,	/* DENALI_PHY_427_DATA */
+			0x00000000,	/* DENALI_PHY_428_DATA */
+			0x00000000,	/* DENALI_PHY_429_DATA */
+			0x00000000,	/* DENALI_PHY_430_DATA */
+			0x00000000,	/* DENALI_PHY_431_DATA */
+			0x00000000,	/* DENALI_PHY_432_DATA */
+			0x00000000,	/* DENALI_PHY_433_DATA */
+			0x00000000,	/* DENALI_PHY_434_DATA */
+			0x00000000,	/* DENALI_PHY_435_DATA */
+			0x00200000,	/* DENALI_PHY_436_DATA */
+			0x00000000,	/* DENALI_PHY_437_DATA */
+			0x00000000,	/* DENALI_PHY_438_DATA */
+			0x00000000,	/* DENALI_PHY_439_DATA */
+			0x00000000,	/* DENALI_PHY_440_DATA */
+			0x00000000,	/* DENALI_PHY_441_DATA */
+			0x00000000,	/* DENALI_PHY_442_DATA */
+			0x02800280,	/* DENALI_PHY_443_DATA */
+			0x02800280,	/* DENALI_PHY_444_DATA */
+			0x02800280,	/* DENALI_PHY_445_DATA */
+			0x02800280,	/* DENALI_PHY_446_DATA */
+			0x00000280,	/* DENALI_PHY_447_DATA */
+			0x00000000,	/* DENALI_PHY_448_DATA */
+			0x00000000,	/* DENALI_PHY_449_DATA */
+			0x00000000,	/* DENALI_PHY_450_DATA */
+			0x00000000,	/* DENALI_PHY_451_DATA */
+			0x00800000,	/* DENALI_PHY_452_DATA */
+			0x00800080,	/* DENALI_PHY_453_DATA */
+			0x00800080,	/* DENALI_PHY_454_DATA */
+			0x00800080,	/* DENALI_PHY_455_DATA */
+			0x00800080,	/* DENALI_PHY_456_DATA */
+			0x00800080,	/* DENALI_PHY_457_DATA */
+			0x00800080,	/* DENALI_PHY_458_DATA */
+			0x00800080,	/* DENALI_PHY_459_DATA */
+			0x00800080,	/* DENALI_PHY_460_DATA */
+			0x01190080,	/* DENALI_PHY_461_DATA */
+			0x00000002,	/* DENALI_PHY_462_DATA */
+			0x00000000,	/* DENALI_PHY_463_DATA */
+			0x00000000,	/* DENALI_PHY_464_DATA */
+			0x00000200,	/* DENALI_PHY_465_DATA */
+			0x00000000,	/* DENALI_PHY_466_DATA */
+			0x51315152,	/* DENALI_PHY_467_DATA */
+			0xc0013150,	/* DENALI_PHY_468_DATA */
+			0x020000c0,	/* DENALI_PHY_469_DATA */
+			0x00100001,	/* DENALI_PHY_470_DATA */
+			0x07054204,	/* DENALI_PHY_471_DATA */
+			0x000f0c18,	/* DENALI_PHY_472_DATA */
+			0x01000140,	/* DENALI_PHY_473_DATA */
+			0x00000c10,	/* DENALI_PHY_474_DATA */
+			0x00000000,	/* DENALI_PHY_475_DATA */
+			0x00000000,	/* DENALI_PHY_476_DATA */
+			0x00000000,	/* DENALI_PHY_477_DATA */
+			0x00000000,	/* DENALI_PHY_478_DATA */
+			0x00000000,	/* DENALI_PHY_479_DATA */
+			0x00000000,	/* DENALI_PHY_480_DATA */
+			0x00000000,	/* DENALI_PHY_481_DATA */
+			0x00000000,	/* DENALI_PHY_482_DATA */
+			0x00000000,	/* DENALI_PHY_483_DATA */
+			0x00000000,	/* DENALI_PHY_484_DATA */
+			0x00000000,	/* DENALI_PHY_485_DATA */
+			0x00000000,	/* DENALI_PHY_486_DATA */
+			0x00000000,	/* DENALI_PHY_487_DATA */
+			0x00000000,	/* DENALI_PHY_488_DATA */
+			0x00000000,	/* DENALI_PHY_489_DATA */
+			0x00000000,	/* DENALI_PHY_490_DATA */
+			0x00000000,	/* DENALI_PHY_491_DATA */
+			0x00000000,	/* DENALI_PHY_492_DATA */
+			0x00000000,	/* DENALI_PHY_493_DATA */
+			0x00000000,	/* DENALI_PHY_494_DATA */
+			0x00000000,	/* DENALI_PHY_495_DATA */
+			0x00000000,	/* DENALI_PHY_496_DATA */
+			0x00000000,	/* DENALI_PHY_497_DATA */
+			0x00000000,	/* DENALI_PHY_498_DATA */
+			0x00000000,	/* DENALI_PHY_499_DATA */
+			0x00000000,	/* DENALI_PHY_500_DATA */
+			0x00000000,	/* DENALI_PHY_501_DATA */
+			0x00000000,	/* DENALI_PHY_502_DATA */
+			0x00000000,	/* DENALI_PHY_503_DATA */
+			0x00000000,	/* DENALI_PHY_504_DATA */
+			0x00000000,	/* DENALI_PHY_505_DATA */
+			0x00000000,	/* DENALI_PHY_506_DATA */
+			0x00000000,	/* DENALI_PHY_507_DATA */
+			0x00000000,	/* DENALI_PHY_508_DATA */
+			0x00000000,	/* DENALI_PHY_509_DATA */
+			0x00000000,	/* DENALI_PHY_510_DATA */
+			0x00000000,	/* DENALI_PHY_511_DATA */
+			0x00000000,	/* DENALI_PHY_512_DATA */
+			0x00000000,	/* DENALI_PHY_513_DATA */
+			0x00000000,	/* DENALI_PHY_514_DATA */
+			0x00000000,	/* DENALI_PHY_515_DATA */
+			0x00000000,	/* DENALI_PHY_516_DATA */
+			0x00000000,	/* DENALI_PHY_517_DATA */
+			0x00000000,	/* DENALI_PHY_518_DATA */
+			0x00000002,	/* DENALI_PHY_519_DATA */
+			0x00000000,	/* DENALI_PHY_520_DATA */
+			0x00000000,	/* DENALI_PHY_521_DATA */
+			0x00000000,	/* DENALI_PHY_522_DATA */
+			0x00400320,	/* DENALI_PHY_523_DATA */
+			0x00000040,	/* DENALI_PHY_524_DATA */
+			0x00dcba98,	/* DENALI_PHY_525_DATA */
+			0x00000000,	/* DENALI_PHY_526_DATA */
+			0x00dcba98,	/* DENALI_PHY_527_DATA */
+			0x01000000,	/* DENALI_PHY_528_DATA */
+			0x00020003,	/* DENALI_PHY_529_DATA */
+			0x00000000,	/* DENALI_PHY_530_DATA */
+			0x00000000,	/* DENALI_PHY_531_DATA */
+			0x00000000,	/* DENALI_PHY_532_DATA */
+			0x0000002a,	/* DENALI_PHY_533_DATA */
+			0x00000015,	/* DENALI_PHY_534_DATA */
+			0x00000015,	/* DENALI_PHY_535_DATA */
+			0x0000002a,	/* DENALI_PHY_536_DATA */
+			0x00000033,	/* DENALI_PHY_537_DATA */
+			0x0000000c,	/* DENALI_PHY_538_DATA */
+			0x0000000c,	/* DENALI_PHY_539_DATA */
+			0x00000033,	/* DENALI_PHY_540_DATA */
+			0x0a418820,	/* DENALI_PHY_541_DATA */
+			0x003f0000,	/* DENALI_PHY_542_DATA */
+			0x0000003f,	/* DENALI_PHY_543_DATA */
+			0x00030055,	/* DENALI_PHY_544_DATA */
+			0x03000300,	/* DENALI_PHY_545_DATA */
+			0x03000300,	/* DENALI_PHY_546_DATA */
+			0x00000300,	/* DENALI_PHY_547_DATA */
+			0x42080010,	/* DENALI_PHY_548_DATA */
+			0x00000003,	/* DENALI_PHY_549_DATA */
+			0x00000000,	/* DENALI_PHY_550_DATA */
+			0x00000000,	/* DENALI_PHY_551_DATA */
+			0x00000000,	/* DENALI_PHY_552_DATA */
+			0x00000000,	/* DENALI_PHY_553_DATA */
+			0x00000000,	/* DENALI_PHY_554_DATA */
+			0x00000000,	/* DENALI_PHY_555_DATA */
+			0x00000000,	/* DENALI_PHY_556_DATA */
+			0x00000000,	/* DENALI_PHY_557_DATA */
+			0x00000000,	/* DENALI_PHY_558_DATA */
+			0x00000000,	/* DENALI_PHY_559_DATA */
+			0x00000000,	/* DENALI_PHY_560_DATA */
+			0x00000000,	/* DENALI_PHY_561_DATA */
+			0x00000000,	/* DENALI_PHY_562_DATA */
+			0x00000000,	/* DENALI_PHY_563_DATA */
+			0x00000000,	/* DENALI_PHY_564_DATA */
+			0x00000000,	/* DENALI_PHY_565_DATA */
+			0x00000000,	/* DENALI_PHY_566_DATA */
+			0x00000000,	/* DENALI_PHY_567_DATA */
+			0x00000000,	/* DENALI_PHY_568_DATA */
+			0x00000000,	/* DENALI_PHY_569_DATA */
+			0x00000000,	/* DENALI_PHY_570_DATA */
+			0x00000000,	/* DENALI_PHY_571_DATA */
+			0x00000000,	/* DENALI_PHY_572_DATA */
+			0x00000000,	/* DENALI_PHY_573_DATA */
+			0x00000000,	/* DENALI_PHY_574_DATA */
+			0x00000000,	/* DENALI_PHY_575_DATA */
+			0x00000000,	/* DENALI_PHY_576_DATA */
+			0x00000000,	/* DENALI_PHY_577_DATA */
+			0x00000000,	/* DENALI_PHY_578_DATA */
+			0x00000000,	/* DENALI_PHY_579_DATA */
+			0x00000000,	/* DENALI_PHY_580_DATA */
+			0x00000000,	/* DENALI_PHY_581_DATA */
+			0x00000000,	/* DENALI_PHY_582_DATA */
+			0x00000000,	/* DENALI_PHY_583_DATA */
+			0x00000000,	/* DENALI_PHY_584_DATA */
+			0x00000000,	/* DENALI_PHY_585_DATA */
+			0x00000000,	/* DENALI_PHY_586_DATA */
+			0x00000000,	/* DENALI_PHY_587_DATA */
+			0x00000000,	/* DENALI_PHY_588_DATA */
+			0x00000000,	/* DENALI_PHY_589_DATA */
+			0x00000000,	/* DENALI_PHY_590_DATA */
+			0x00000000,	/* DENALI_PHY_591_DATA */
+			0x00000000,	/* DENALI_PHY_592_DATA */
+			0x00000000,	/* DENALI_PHY_593_DATA */
+			0x00000000,	/* DENALI_PHY_594_DATA */
+			0x00000000,	/* DENALI_PHY_595_DATA */
+			0x00000000,	/* DENALI_PHY_596_DATA */
+			0x00000000,	/* DENALI_PHY_597_DATA */
+			0x00000000,	/* DENALI_PHY_598_DATA */
+			0x00000000,	/* DENALI_PHY_599_DATA */
+			0x00000000,	/* DENALI_PHY_600_DATA */
+			0x00000000,	/* DENALI_PHY_601_DATA */
+			0x00000000,	/* DENALI_PHY_602_DATA */
+			0x00000000,	/* DENALI_PHY_603_DATA */
+			0x00000000,	/* DENALI_PHY_604_DATA */
+			0x00000000,	/* DENALI_PHY_605_DATA */
+			0x00000000,	/* DENALI_PHY_606_DATA */
+			0x00000000,	/* DENALI_PHY_607_DATA */
+			0x00000000,	/* DENALI_PHY_608_DATA */
+			0x00000000,	/* DENALI_PHY_609_DATA */
+			0x00000000,	/* DENALI_PHY_610_DATA */
+			0x00000000,	/* DENALI_PHY_611_DATA */
+			0x00000000,	/* DENALI_PHY_612_DATA */
+			0x00000000,	/* DENALI_PHY_613_DATA */
+			0x00000000,	/* DENALI_PHY_614_DATA */
+			0x00000000,	/* DENALI_PHY_615_DATA */
+			0x00000000,	/* DENALI_PHY_616_DATA */
+			0x00000000,	/* DENALI_PHY_617_DATA */
+			0x00000000,	/* DENALI_PHY_618_DATA */
+			0x00000000,	/* DENALI_PHY_619_DATA */
+			0x00000000,	/* DENALI_PHY_620_DATA */
+			0x00000000,	/* DENALI_PHY_621_DATA */
+			0x00000000,	/* DENALI_PHY_622_DATA */
+			0x00000000,	/* DENALI_PHY_623_DATA */
+			0x00000000,	/* DENALI_PHY_624_DATA */
+			0x00000000,	/* DENALI_PHY_625_DATA */
+			0x00000000,	/* DENALI_PHY_626_DATA */
+			0x00000000,	/* DENALI_PHY_627_DATA */
+			0x00000000,	/* DENALI_PHY_628_DATA */
+			0x00000000,	/* DENALI_PHY_629_DATA */
+			0x00000000,	/* DENALI_PHY_630_DATA */
+			0x00000000,	/* DENALI_PHY_631_DATA */
+			0x00000000,	/* DENALI_PHY_632_DATA */
+			0x00000000,	/* DENALI_PHY_633_DATA */
+			0x00000000,	/* DENALI_PHY_634_DATA */
+			0x00000000,	/* DENALI_PHY_635_DATA */
+			0x00000000,	/* DENALI_PHY_636_DATA */
+			0x00000000,	/* DENALI_PHY_637_DATA */
+			0x00000000,	/* DENALI_PHY_638_DATA */
+			0x00000000,	/* DENALI_PHY_639_DATA */
+			0x00000000,	/* DENALI_PHY_640_DATA */
+			0x00000000,	/* DENALI_PHY_641_DATA */
+			0x00000000,	/* DENALI_PHY_642_DATA */
+			0x00000000,	/* DENALI_PHY_643_DATA */
+			0x00000000,	/* DENALI_PHY_644_DATA */
+			0x00000000,	/* DENALI_PHY_645_DATA */
+			0x00000000,	/* DENALI_PHY_646_DATA */
+			0x00000002,	/* DENALI_PHY_647_DATA */
+			0x00000000,	/* DENALI_PHY_648_DATA */
+			0x00000000,	/* DENALI_PHY_649_DATA */
+			0x00000000,	/* DENALI_PHY_650_DATA */
+			0x00400320,	/* DENALI_PHY_651_DATA */
+			0x00000040,	/* DENALI_PHY_652_DATA */
+			0x00000000,	/* DENALI_PHY_653_DATA */
+			0x00000000,	/* DENALI_PHY_654_DATA */
+			0x00000000,	/* DENALI_PHY_655_DATA */
+			0x01000000,	/* DENALI_PHY_656_DATA */
+			0x00020003,	/* DENALI_PHY_657_DATA */
+			0x00000000,	/* DENALI_PHY_658_DATA */
+			0x00000000,	/* DENALI_PHY_659_DATA */
+			0x00000000,	/* DENALI_PHY_660_DATA */
+			0x0000002a,	/* DENALI_PHY_661_DATA */
+			0x00000015,	/* DENALI_PHY_662_DATA */
+			0x00000015,	/* DENALI_PHY_663_DATA */
+			0x0000002a,	/* DENALI_PHY_664_DATA */
+			0x00000033,	/* DENALI_PHY_665_DATA */
+			0x0000000c,	/* DENALI_PHY_666_DATA */
+			0x0000000c,	/* DENALI_PHY_667_DATA */
+			0x00000033,	/* DENALI_PHY_668_DATA */
+			0x00000000,	/* DENALI_PHY_669_DATA */
+			0x00000000,	/* DENALI_PHY_670_DATA */
+			0x00000000,	/* DENALI_PHY_671_DATA */
+			0x00030055,	/* DENALI_PHY_672_DATA */
+			0x03000300,	/* DENALI_PHY_673_DATA */
+			0x03000300,	/* DENALI_PHY_674_DATA */
+			0x00000300,	/* DENALI_PHY_675_DATA */
+			0x42080010,	/* DENALI_PHY_676_DATA */
+			0x00000003,	/* DENALI_PHY_677_DATA */
+			0x00000000,	/* DENALI_PHY_678_DATA */
+			0x00000000,	/* DENALI_PHY_679_DATA */
+			0x00000000,	/* DENALI_PHY_680_DATA */
+			0x00000000,	/* DENALI_PHY_681_DATA */
+			0x00000000,	/* DENALI_PHY_682_DATA */
+			0x00000000,	/* DENALI_PHY_683_DATA */
+			0x00000000,	/* DENALI_PHY_684_DATA */
+			0x00000000,	/* DENALI_PHY_685_DATA */
+			0x00000000,	/* DENALI_PHY_686_DATA */
+			0x00000000,	/* DENALI_PHY_687_DATA */
+			0x00000000,	/* DENALI_PHY_688_DATA */
+			0x00000000,	/* DENALI_PHY_689_DATA */
+			0x00000000,	/* DENALI_PHY_690_DATA */
+			0x00000000,	/* DENALI_PHY_691_DATA */
+			0x00000000,	/* DENALI_PHY_692_DATA */
+			0x00000000,	/* DENALI_PHY_693_DATA */
+			0x00000000,	/* DENALI_PHY_694_DATA */
+			0x00000000,	/* DENALI_PHY_695_DATA */
+			0x00000000,	/* DENALI_PHY_696_DATA */
+			0x00000000,	/* DENALI_PHY_697_DATA */
+			0x00000000,	/* DENALI_PHY_698_DATA */
+			0x00000000,	/* DENALI_PHY_699_DATA */
+			0x00000000,	/* DENALI_PHY_700_DATA */
+			0x00000000,	/* DENALI_PHY_701_DATA */
+			0x00000000,	/* DENALI_PHY_702_DATA */
+			0x00000000,	/* DENALI_PHY_703_DATA */
+			0x00000000,	/* DENALI_PHY_704_DATA */
+			0x00000000,	/* DENALI_PHY_705_DATA */
+			0x00000000,	/* DENALI_PHY_706_DATA */
+			0x00000000,	/* DENALI_PHY_707_DATA */
+			0x00000000,	/* DENALI_PHY_708_DATA */
+			0x00000000,	/* DENALI_PHY_709_DATA */
+			0x00000000,	/* DENALI_PHY_710_DATA */
+			0x00000000,	/* DENALI_PHY_711_DATA */
+			0x00000000,	/* DENALI_PHY_712_DATA */
+			0x00000000,	/* DENALI_PHY_713_DATA */
+			0x00000000,	/* DENALI_PHY_714_DATA */
+			0x00000000,	/* DENALI_PHY_715_DATA */
+			0x00000000,	/* DENALI_PHY_716_DATA */
+			0x00000000,	/* DENALI_PHY_717_DATA */
+			0x00000000,	/* DENALI_PHY_718_DATA */
+			0x00000000,	/* DENALI_PHY_719_DATA */
+			0x00000000,	/* DENALI_PHY_720_DATA */
+			0x00000000,	/* DENALI_PHY_721_DATA */
+			0x00000000,	/* DENALI_PHY_722_DATA */
+			0x00000000,	/* DENALI_PHY_723_DATA */
+			0x00000000,	/* DENALI_PHY_724_DATA */
+			0x00000000,	/* DENALI_PHY_725_DATA */
+			0x00000000,	/* DENALI_PHY_726_DATA */
+			0x00000000,	/* DENALI_PHY_727_DATA */
+			0x00000000,	/* DENALI_PHY_728_DATA */
+			0x00000000,	/* DENALI_PHY_729_DATA */
+			0x00000000,	/* DENALI_PHY_730_DATA */
+			0x00000000,	/* DENALI_PHY_731_DATA */
+			0x00000000,	/* DENALI_PHY_732_DATA */
+			0x00000000,	/* DENALI_PHY_733_DATA */
+			0x00000000,	/* DENALI_PHY_734_DATA */
+			0x00000000,	/* DENALI_PHY_735_DATA */
+			0x00000000,	/* DENALI_PHY_736_DATA */
+			0x00000000,	/* DENALI_PHY_737_DATA */
+			0x00000000,	/* DENALI_PHY_738_DATA */
+			0x00000000,	/* DENALI_PHY_739_DATA */
+			0x00000000,	/* DENALI_PHY_740_DATA */
+			0x00000000,	/* DENALI_PHY_741_DATA */
+			0x00000000,	/* DENALI_PHY_742_DATA */
+			0x00000000,	/* DENALI_PHY_743_DATA */
+			0x00000000,	/* DENALI_PHY_744_DATA */
+			0x00000000,	/* DENALI_PHY_745_DATA */
+			0x00000000,	/* DENALI_PHY_746_DATA */
+			0x00000000,	/* DENALI_PHY_747_DATA */
+			0x00000000,	/* DENALI_PHY_748_DATA */
+			0x00000000,	/* DENALI_PHY_749_DATA */
+			0x00000000,	/* DENALI_PHY_750_DATA */
+			0x00000000,	/* DENALI_PHY_751_DATA */
+			0x00000000,	/* DENALI_PHY_752_DATA */
+			0x00000000,	/* DENALI_PHY_753_DATA */
+			0x00000000,	/* DENALI_PHY_754_DATA */
+			0x00000000,	/* DENALI_PHY_755_DATA */
+			0x00000000,	/* DENALI_PHY_756_DATA */
+			0x00000000,	/* DENALI_PHY_757_DATA */
+			0x00000000,	/* DENALI_PHY_758_DATA */
+			0x00000000,	/* DENALI_PHY_759_DATA */
+			0x00000000,	/* DENALI_PHY_760_DATA */
+			0x00000000,	/* DENALI_PHY_761_DATA */
+			0x00000000,	/* DENALI_PHY_762_DATA */
+			0x00000000,	/* DENALI_PHY_763_DATA */
+			0x00000000,	/* DENALI_PHY_764_DATA */
+			0x00000000,	/* DENALI_PHY_765_DATA */
+			0x00000000,	/* DENALI_PHY_766_DATA */
+			0x00000000,	/* DENALI_PHY_767_DATA */
+			0x00000000,	/* DENALI_PHY_768_DATA */
+			0x00000000,	/* DENALI_PHY_769_DATA */
+			0x00000000,	/* DENALI_PHY_770_DATA */
+			0x00000000,	/* DENALI_PHY_771_DATA */
+			0x00000000,	/* DENALI_PHY_772_DATA */
+			0x00000000,	/* DENALI_PHY_773_DATA */
+			0x00000000,	/* DENALI_PHY_774_DATA */
+			0x00000002,	/* DENALI_PHY_775_DATA */
+			0x00000000,	/* DENALI_PHY_776_DATA */
+			0x00000000,	/* DENALI_PHY_777_DATA */
+			0x00000000,	/* DENALI_PHY_778_DATA */
+			0x00400320,	/* DENALI_PHY_779_DATA */
+			0x00000040,	/* DENALI_PHY_780_DATA */
+			0x00000000,	/* DENALI_PHY_781_DATA */
+			0x00000000,	/* DENALI_PHY_782_DATA */
+			0x00000000,	/* DENALI_PHY_783_DATA */
+			0x01000000,	/* DENALI_PHY_784_DATA */
+			0x00020003,	/* DENALI_PHY_785_DATA */
+			0x00000000,	/* DENALI_PHY_786_DATA */
+			0x00000000,	/* DENALI_PHY_787_DATA */
+			0x00000000,	/* DENALI_PHY_788_DATA */
+			0x0000002a,	/* DENALI_PHY_789_DATA */
+			0x00000015,	/* DENALI_PHY_790_DATA */
+			0x00000015,	/* DENALI_PHY_791_DATA */
+			0x0000002a,	/* DENALI_PHY_792_DATA */
+			0x00000033,	/* DENALI_PHY_793_DATA */
+			0x0000000c,	/* DENALI_PHY_794_DATA */
+			0x0000000c,	/* DENALI_PHY_795_DATA */
+			0x00000033,	/* DENALI_PHY_796_DATA */
+			0x1ee6b16a,	/* DENALI_PHY_797_DATA */
+			0x10000000,	/* DENALI_PHY_798_DATA */
+			0x00000000,	/* DENALI_PHY_799_DATA */
+			0x00030055,	/* DENALI_PHY_800_DATA */
+			0x03000300,	/* DENALI_PHY_801_DATA */
+			0x03000300,	/* DENALI_PHY_802_DATA */
+			0x00000300,	/* DENALI_PHY_803_DATA */
+			0x42080010,	/* DENALI_PHY_804_DATA */
+			0x00000003,	/* DENALI_PHY_805_DATA */
+			0x00000000,	/* DENALI_PHY_806_DATA */
+			0x00000000,	/* DENALI_PHY_807_DATA */
+			0x00000000,	/* DENALI_PHY_808_DATA */
+			0x00000000,	/* DENALI_PHY_809_DATA */
+			0x00000000,	/* DENALI_PHY_810_DATA */
+			0x00000000,	/* DENALI_PHY_811_DATA */
+			0x00000000,	/* DENALI_PHY_812_DATA */
+			0x00000000,	/* DENALI_PHY_813_DATA */
+			0x00000000,	/* DENALI_PHY_814_DATA */
+			0x00000000,	/* DENALI_PHY_815_DATA */
+			0x00000000,	/* DENALI_PHY_816_DATA */
+			0x00000000,	/* DENALI_PHY_817_DATA */
+			0x00000000,	/* DENALI_PHY_818_DATA */
+			0x00000000,	/* DENALI_PHY_819_DATA */
+			0x00000000,	/* DENALI_PHY_820_DATA */
+			0x00000000,	/* DENALI_PHY_821_DATA */
+			0x00000000,	/* DENALI_PHY_822_DATA */
+			0x00000000,	/* DENALI_PHY_823_DATA */
+			0x00000000,	/* DENALI_PHY_824_DATA */
+			0x00000000,	/* DENALI_PHY_825_DATA */
+			0x00000000,	/* DENALI_PHY_826_DATA */
+			0x00000000,	/* DENALI_PHY_827_DATA */
+			0x00000000,	/* DENALI_PHY_828_DATA */
+			0x00000000,	/* DENALI_PHY_829_DATA */
+			0x00000000,	/* DENALI_PHY_830_DATA */
+			0x00000000,	/* DENALI_PHY_831_DATA */
+			0x00000000,	/* DENALI_PHY_832_DATA */
+			0x00000000,	/* DENALI_PHY_833_DATA */
+			0x00000000,	/* DENALI_PHY_834_DATA */
+			0x00000000,	/* DENALI_PHY_835_DATA */
+			0x00000000,	/* DENALI_PHY_836_DATA */
+			0x00000000,	/* DENALI_PHY_837_DATA */
+			0x00000000,	/* DENALI_PHY_838_DATA */
+			0x00000000,	/* DENALI_PHY_839_DATA */
+			0x00000000,	/* DENALI_PHY_840_DATA */
+			0x00000000,	/* DENALI_PHY_841_DATA */
+			0x00000000,	/* DENALI_PHY_842_DATA */
+			0x00000000,	/* DENALI_PHY_843_DATA */
+			0x00000000,	/* DENALI_PHY_844_DATA */
+			0x00000000,	/* DENALI_PHY_845_DATA */
+			0x00000000,	/* DENALI_PHY_846_DATA */
+			0x00000000,	/* DENALI_PHY_847_DATA */
+			0x00000000,	/* DENALI_PHY_848_DATA */
+			0x00000000,	/* DENALI_PHY_849_DATA */
+			0x00000000,	/* DENALI_PHY_850_DATA */
+			0x00000000,	/* DENALI_PHY_851_DATA */
+			0x00000000,	/* DENALI_PHY_852_DATA */
+			0x00000000,	/* DENALI_PHY_853_DATA */
+			0x00000000,	/* DENALI_PHY_854_DATA */
+			0x00000000,	/* DENALI_PHY_855_DATA */
+			0x00000000,	/* DENALI_PHY_856_DATA */
+			0x00000000,	/* DENALI_PHY_857_DATA */
+			0x00000000,	/* DENALI_PHY_858_DATA */
+			0x00000000,	/* DENALI_PHY_859_DATA */
+			0x00000000,	/* DENALI_PHY_860_DATA */
+			0x00000000,	/* DENALI_PHY_861_DATA */
+			0x00000000,	/* DENALI_PHY_862_DATA */
+			0x00000000,	/* DENALI_PHY_863_DATA */
+			0x00000000,	/* DENALI_PHY_864_DATA */
+			0x00000000,	/* DENALI_PHY_865_DATA */
+			0x00000000,	/* DENALI_PHY_866_DATA */
+			0x00000000,	/* DENALI_PHY_867_DATA */
+			0x00000000,	/* DENALI_PHY_868_DATA */
+			0x00000000,	/* DENALI_PHY_869_DATA */
+			0x00000000,	/* DENALI_PHY_870_DATA */
+			0x00000000,	/* DENALI_PHY_871_DATA */
+			0x00000000,	/* DENALI_PHY_872_DATA */
+			0x00000000,	/* DENALI_PHY_873_DATA */
+			0x00000000,	/* DENALI_PHY_874_DATA */
+			0x00000000,	/* DENALI_PHY_875_DATA */
+			0x00000000,	/* DENALI_PHY_876_DATA */
+			0x00000000,	/* DENALI_PHY_877_DATA */
+			0x00000000,	/* DENALI_PHY_878_DATA */
+			0x00000000,	/* DENALI_PHY_879_DATA */
+			0x00000000,	/* DENALI_PHY_880_DATA */
+			0x00000000,	/* DENALI_PHY_881_DATA */
+			0x00000000,	/* DENALI_PHY_882_DATA */
+			0x00000000,	/* DENALI_PHY_883_DATA */
+			0x00000000,	/* DENALI_PHY_884_DATA */
+			0x00000000,	/* DENALI_PHY_885_DATA */
+			0x00000000,	/* DENALI_PHY_886_DATA */
+			0x00000000,	/* DENALI_PHY_887_DATA */
+			0x00000000,	/* DENALI_PHY_888_DATA */
+			0x00000000,	/* DENALI_PHY_889_DATA */
+			0x00000000,	/* DENALI_PHY_890_DATA */
+			0x00000000,	/* DENALI_PHY_891_DATA */
+			0x00000000,	/* DENALI_PHY_892_DATA */
+			0x00000000,	/* DENALI_PHY_893_DATA */
+			0x00000000,	/* DENALI_PHY_894_DATA */
+			0x00000000,	/* DENALI_PHY_895_DATA */
+			0x00000000,	/* DENALI_PHY_896_DATA */
+			0x00000000,	/* DENALI_PHY_897_DATA */
+			0x00000005,	/* DENALI_PHY_898_DATA */
+			0x04000f01,	/* DENALI_PHY_899_DATA */
+			0x00020040,	/* DENALI_PHY_900_DATA */
+			0x00020055,	/* DENALI_PHY_901_DATA */
+			0x00000000,	/* DENALI_PHY_902_DATA */
+			0x00000000,	/* DENALI_PHY_903_DATA */
+			0x00000000,	/* DENALI_PHY_904_DATA */
+			0x00000050,	/* DENALI_PHY_905_DATA */
+			0x00000000,	/* DENALI_PHY_906_DATA */
+			0x01010100,	/* DENALI_PHY_907_DATA */
+			0x00000600,	/* DENALI_PHY_908_DATA */
+			0x00000000,	/* DENALI_PHY_909_DATA */
+			0x00006400,	/* DENALI_PHY_910_DATA */
+			0x01221102,	/* DENALI_PHY_911_DATA */
+			0x00000000,	/* DENALI_PHY_912_DATA */
+			0x000d1f00,	/* DENALI_PHY_913_DATA */
+			0x0d1f0d1f,	/* DENALI_PHY_914_DATA */
+			0x0d1f0d1f,	/* DENALI_PHY_915_DATA */
+			0x00030003,	/* DENALI_PHY_916_DATA */
+			0x03000300,	/* DENALI_PHY_917_DATA */
+			0x00000300,	/* DENALI_PHY_918_DATA */
+			0x01221102,	/* DENALI_PHY_919_DATA */
+			0x00000000,	/* DENALI_PHY_920_DATA */
+			0x00000000,	/* DENALI_PHY_921_DATA */
+			0x03020000,	/* DENALI_PHY_922_DATA */
+			0x00000001,	/* DENALI_PHY_923_DATA */
+			0x00000411,	/* DENALI_PHY_924_DATA */
+			0x00000411,	/* DENALI_PHY_925_DATA */
+			0x00000040,	/* DENALI_PHY_926_DATA */
+			0x00000040,	/* DENALI_PHY_927_DATA */
+			0x00000411,	/* DENALI_PHY_928_DATA */
+			0x00000411,	/* DENALI_PHY_929_DATA */
+			0x00004410,	/* DENALI_PHY_930_DATA */
+			0x00004410,	/* DENALI_PHY_931_DATA */
+			0x00004410,	/* DENALI_PHY_932_DATA */
+			0x00004410,	/* DENALI_PHY_933_DATA */
+			0x00004410,	/* DENALI_PHY_934_DATA */
+			0x00000411,	/* DENALI_PHY_935_DATA */
+			0x00004410,	/* DENALI_PHY_936_DATA */
+			0x00000411,	/* DENALI_PHY_937_DATA */
+			0x00004410,	/* DENALI_PHY_938_DATA */
+			0x00000411,	/* DENALI_PHY_939_DATA */
+			0x00004410,	/* DENALI_PHY_940_DATA */
+			0x00000000,	/* DENALI_PHY_941_DATA */
+			0x00000000,	/* DENALI_PHY_942_DATA */
+			0x00000000,	/* DENALI_PHY_943_DATA */
+			0x64000000,	/* DENALI_PHY_944_DATA */
+			0x00000000,	/* DENALI_PHY_945_DATA */
+			0x00000000,	/* DENALI_PHY_946_DATA */
+			0x00000508,	/* DENALI_PHY_947_DATA */
+			0x00000000,	/* DENALI_PHY_948_DATA */
+			0x00000000,	/* DENALI_PHY_949_DATA */
+			0x00000000,	/* DENALI_PHY_950_DATA */
+			0x00000000,	/* DENALI_PHY_951_DATA */
+			0x00000000,	/* DENALI_PHY_952_DATA */
+			0x00000000,	/* DENALI_PHY_953_DATA */
+			0xe4000000,	/* DENALI_PHY_954_DATA */
+			0x00000000,	/* DENALI_PHY_955_DATA */
+			0x00000000,	/* DENALI_PHY_956_DATA */
+			0x01010000,	/* DENALI_PHY_957_DATA */
+			0x00000000	/* DENALI_PHY_958_DATA */
+		}
+	},
+},
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-51-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#144 lore raw

Re: [PATCH v3 50/57] ram: rk3399: Add LPPDDR4-800 timings inc

Quoted 10 lines · Jagan Teki

LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#145 lore raw

PATCH v3 51/57 ram: rk3399: Add set_rate sdram rk3399 ops

In reply to a message not in the archive

DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4.

For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 drivers/ram/rockchip/sdram_rk3399.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +8 -3
index 623685e3c5..c3d7665ea2 100644
@@ -74,6 +74,8 @@ struct dram_info {
 struct sdram_rk3399_ops {
 	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
 			     struct rk3399_sdram_params *sdram);
+	int (*set_rate)(struct dram_info *dram,
+			const struct rk3399_sdram_params *params);
 };
 
 #if defined(CONFIG_TPL_BUILD) || \

@@ -948,6 +950,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	return 0;
 }
 
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
 static void select_per_cs_training_index(const struct chan_info *chan,
 					 u32 rank)
 {

@@ -1368,6 +1371,7 @@ static int data_training(struct dram_info *dram, u32 channel,
 
 	return 0;
 }
+#endif
 
 static void set_ddrconfig(const struct chan_info *chan,
 			  const struct rk3399_sdram_params *params,

@@ -1487,7 +1491,6 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 
 	return data_training(dram, channel, params, training_flag);
 }
-#endif
 
 static int switch_to_phy_index1(struct dram_info *dram,
 				const struct rk3399_sdram_params *params)

@@ -1534,7 +1537,8 @@ static int switch_to_phy_index1(struct dram_info *dram,
 	return 0;
 }
 
-#if defined(CONFIG_RAM_RK3399_LPDDR4)
+#else
+
 static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
 {
 	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);

@@ -1938,7 +1942,7 @@ static int sdram_init(struct dram_info *dram,
 
 	params->base.stride = calculate_stride(params);
 	dram_all_config(dram, params);
-	switch_to_phy_index1(dram, params);
+	dram->ops->set_rate(dram, params);
 
 	debug("Finish SDRAM initialization...\n");
 	return 0;

@@ -1986,6 +1990,7 @@ static int conv_of_platdata(struct udevice *dev)
 static const struct sdram_rk3399_ops rk3399_ops = {
 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
 	.data_training = default_data_training,
+	.set_rate = switch_to_phy_index1,
 #else
 	.data_training = lpddr4_mr_detect,
 #endif
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-52-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#147 lore raw

Re: [PATCH v3 51/57] ram: rk3399: Add set_rate sdram rk3399 ops

Quoted 9 lines · Jagan Teki

DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4.

For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 61 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 11 ++++++++---
  1 file changed, 8 insertions(+), 3 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +7 -3
index 623685e3c5..c3d7665ea2 100644
@@ -74,6 +74,8 @@ struct dram_info {
  struct sdram_rk3399_ops {
  	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
  			     struct rk3399_sdram_params *sdram);
+	int (*set_rate)(struct dram_info *dram,
+			const struct rk3399_sdram_params *params);
  };
 
  #if defined(CONFIG_TPL_BUILD) || \

@@ -948,6 +950,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	return 0;
  }
 
+#if !defined(CONFIG_RAM_RK3399_LPDDR4)
  static void select_per_cs_training_index(const struct chan_info *chan,
  					 u32 rank)
  {

@@ -1368,6 +1371,7 @@ static int data_training(struct dram_info *dram, u32 channel,
 
  	return 0;
  }
+#endif
 
  static void set_ddrconfig(const struct chan_info *chan,
  			  const struct rk3399_sdram_params *params,

@@ -1487,7 +1491,6 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 
  	return data_training(dram, channel, params, training_flag);
  }
-#endif
 
  static int switch_to_phy_index1(struct dram_info *dram,
  				const struct rk3399_sdram_params *params)

@@ -1534,7 +1537,8 @@ static int switch_to_phy_index1(struct dram_info *dram,
  	return 0;
  }
 
-#if defined(CONFIG_RAM_RK3399_LPDDR4)
+#else
+
  static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
  {
  	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);

@@ -1938,7 +1942,7 @@ static int sdram_init(struct dram_info *dram,
 
  	params->base.stride = calculate_stride(params);
  	dram_all_config(dram, params);
-	switch_to_phy_index1(dram, params);
+	dram->ops->set_rate(dram, params);
 
  	debug("Finish SDRAM initialization...\n");
  	return 0;

drivers/ram/rockchip/sdram_rk3399.c static int conv_of_platdata(struct udevice *dev) · line 1996

Quoted 7 lines
drivers/ram/rockchip/sdram_rk3399.c +1 -0
@@ -1986,6 +1990,7 @@ static int conv_of_platdata(struct udevice *dev)
  static const struct sdram_rk3399_ops rk3399_ops = {
  #if !defined(CONFIG_RAM_RK3399_LPDDR4)
  	.data_training = default_data_training,
+	.set_rate = switch_to_phy_index1,
  #else
  	.data_training = lpddr4_mr_detect,
  #endif

_______________________________________________
Linux-rockchip mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/linux-rockchip

#148 lore raw

PATCH v3 52/57 ram: rk3399: Add lpddr4 set rate support

In reply to a message not in the archive

Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.

Here is sameple log about LPDDR4-100 init sequence in Rockpro64:

Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0

This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
Signed-off-by YouMin Chen <[email protected]>
---
 drivers/ram/rockchip/sdram_rk3399.c | 677 +++++++++++++++++++++++++++-
 1 file changed, 665 insertions(+), 12 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +665 -12
index c3d7665ea2..3f29b5e0e8 100644
@@ -16,6 +16,7 @@
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/cru_rk3399.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/pmu_rk3399.h>
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/sdram_common.h>
 #include <asm/arch-rockchip/sdram_rk3399.h>

@@ -62,6 +63,7 @@ struct dram_info {
 	struct clk ddr_clk;
 	struct rk3399_cru *cru;
 	struct rk3399_grf_regs *grf;
+	struct rk3399_pmu_regs *pmu;
 	struct rk3399_pmucru *pmucru;
 	struct rk3399_pmusgrf_regs *pmusgrf;
 	struct rk3399_ddr_cic_regs *cic;

@@ -75,7 +77,7 @@ struct sdram_rk3399_ops {
 	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
 			     struct rk3399_sdram_params *sdram);
 	int (*set_rate)(struct dram_info *dram,
-			const struct rk3399_sdram_params *params);
+			struct rk3399_sdram_params *params);
 };
 
 #if defined(CONFIG_TPL_BUILD) || \

@@ -221,6 +223,18 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
 	return io;
 }
 
+static void *get_denali_phy(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
+}
+
+static void *get_denali_ctl(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
+}
+
 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
 {
 	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

@@ -574,10 +588,11 @@ static int phy_io_config(const struct chan_info *chan,
 }
 
 static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *params, u32 mr5)
+		       struct rk3399_sdram_params *params,
+		       bool ctl_phy_reg, u32 mr5)
 {
-	u32 *denali_phy = chan->publ->denali_phy;
-	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
 	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
 	u32 tsel_idle_select_p, tsel_rd_select_p;
 	u32 tsel_idle_select_n, tsel_rd_select_n;

@@ -735,7 +750,8 @@ static void set_ds_odt(const struct chan_info *chan,
 	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 
 	/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
-	clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+	if (!ctl_phy_reg)
+		clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 
 	/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
 	clrsetbits_le32(&denali_phy[935], 0xff, reg_value);

@@ -919,7 +935,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
 	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
 	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, params, 0);
+	set_ds_odt(chan, params, true, 0);
 
 	/*
 	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8

@@ -950,7 +966,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
 	return 0;
 }
 
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
 static void select_per_cs_training_index(const struct chan_info *chan,
 					 u32 rank)
 {

@@ -1308,7 +1323,7 @@ static int data_training(struct dram_info *dram, u32 channel,
 
 	if (training_flag == PI_FULL_TRAINING) {
 		if (params->base.dramtype == LPDDR4) {
-			training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+			training_flag = PI_WRITE_LEVELING |
 					PI_READ_GATE_TRAINING |
 					PI_READ_LEVELING | PI_WDQ_LEVELING;
 		} else if (params->base.dramtype == LPDDR3) {

@@ -1371,7 +1386,6 @@ static int data_training(struct dram_info *dram, u32 channel,
 
 	return 0;
 }
-#endif
 
 static void set_ddrconfig(const struct chan_info *chan,
 			  const struct rk3399_sdram_params *params,

@@ -1493,7 +1507,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 }
 
 static int switch_to_phy_index1(struct dram_info *dram,
-				const struct rk3399_sdram_params *params)
+				struct rk3399_sdram_params *params)
 {
 	u32 channel;
 	u32 *denali_phy;

@@ -1539,6 +1553,31 @@ static int switch_to_phy_index1(struct dram_info *dram,
 
 #else
 
+struct rk3399_sdram_params lpddr4_timings[] = {
+	#include "sdram-rk3399-lpddr4-400.inc"
+	#include "sdram-rk3399-lpddr4-800.inc"
+};
+
+static void *get_denali_pi(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pi->denali_pi : &params->pi_regs.denali_pi;
+}
+
+static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
+{
+	u32 lpddr4_phy[] = {1, 0, 0xb};
+
+	return lpddr4_phy[ctl];
+}
+
+static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
+{
+	u32 lpddr4_ctl[] = {1, 0, 2};
+
+	return lpddr4_ctl[phy];
+}
+
 static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
 {
 	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);

@@ -1756,6 +1795,618 @@ end:
 
 	return ret;
 }
+
+static void set_lpddr4_dq_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
+		break;
+	}
+}
+
+static void set_lpddr4_ca_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
+		break;
+	}
+}
+
+static void set_lpddr4_MR3(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, u32 ctl,
+			   bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = ((io->pdds << 3) | 1);
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
+		break;
+	}
+}
+
+static void set_lpddr4_MR12(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
+		break;
+	}
+}
+
+static void set_lpddr4_MR14(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
+		break;
+	}
+}
+
+static void lpddr4_copy_phy(struct dram_info *dram,
+			    struct rk3399_sdram_params *params, u32 phy,
+			    struct rk3399_sdram_params *timings,
+			    u32 channel)
+{
+	u32 *denali_ctl, *denali_phy;
+	u32 *denali_phy_params;
+	u32 speed = 0;
+	u32 ctl, mr5;
+
+	denali_ctl = dram->chan[channel].pctl->denali_ctl;
+	denali_phy = dram->chan[channel].publ->denali_phy;
+	denali_phy_params = timings->phy_regs.denali_phy;
+
+	/* switch index */
+	clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
+	writel(denali_phy_params[896], &denali_phy[896]);
+
+	/* phy_pll_ctrl_ca, phy_pll_ctrl */
+	writel(denali_phy_params[911], &denali_phy[911]);
+
+	/* phy_low_freq_sel */
+	clrsetbits_le32(&denali_phy[913], 0x1,
+			denali_phy_params[913] & 0x1);
+
+	/* phy_grp_slave_delay_x, phy_cslvl_dly_step */
+	writel(denali_phy_params[916], &denali_phy[916]);
+	writel(denali_phy_params[917], &denali_phy[917]);
+	writel(denali_phy_params[918], &denali_phy[918]);
+
+	/* phy_adrz_sw_wraddr_shift_x  */
+	writel(denali_phy_params[512], &denali_phy[512]);
+	clrsetbits_le32(&denali_phy[513], 0xffff,
+			denali_phy_params[513] & 0xffff);
+	writel(denali_phy_params[640], &denali_phy[640]);
+	clrsetbits_le32(&denali_phy[641], 0xffff,
+			denali_phy_params[641] & 0xffff);
+	writel(denali_phy_params[768], &denali_phy[768]);
+	clrsetbits_le32(&denali_phy[769], 0xffff,
+			denali_phy_params[769] & 0xffff);
+
+	writel(denali_phy_params[544], &denali_phy[544]);
+	writel(denali_phy_params[545], &denali_phy[545]);
+	writel(denali_phy_params[546], &denali_phy[546]);
+	writel(denali_phy_params[547], &denali_phy[547]);
+
+	writel(denali_phy_params[672], &denali_phy[672]);
+	writel(denali_phy_params[673], &denali_phy[673]);
+	writel(denali_phy_params[674], &denali_phy[674]);
+	writel(denali_phy_params[675], &denali_phy[675]);
+
+	writel(denali_phy_params[800], &denali_phy[800]);
+	writel(denali_phy_params[801], &denali_phy[801]);
+	writel(denali_phy_params[802], &denali_phy[802]);
+	writel(denali_phy_params[803], &denali_phy[803]);
+
+	/*
+	 * phy_adr_master_delay_start_x
+	 * phy_adr_master_delay_step_x
+	 * phy_adr_master_delay_wait_x
+	 */
+	writel(denali_phy_params[548], &denali_phy[548]);
+	writel(denali_phy_params[676], &denali_phy[676]);
+	writel(denali_phy_params[804], &denali_phy[804]);
+
+	/* phy_adr_calvl_dly_step_x */
+	writel(denali_phy_params[549], &denali_phy[549]);
+	writel(denali_phy_params[677], &denali_phy[677]);
+	writel(denali_phy_params[805], &denali_phy[805]);
+
+	/*
+	 * phy_clk_wrdm_slave_delay_x
+	 * phy_clk_wrdqz_slave_delay_x
+	 * phy_clk_wrdqs_slave_delay_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
+		    (63 - 58) * 4);
+	copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
+		    (191 - 186) * 4);
+	copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
+		    (319 - 314) * 4);
+	copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
+		    (447 - 442) * 4);
+
+	/*
+	 * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
+	 * dqs_tsel_wr_end[7:4] add half cycle
+	 * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
+	 * dq_tsel_wr_end[7:4] add half cycle
+	 */
+	writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
+	writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
+	writel(denali_phy_params[85], &denali_phy[85]);
+
+	writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
+	writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
+	writel(denali_phy_params[213], &denali_phy[213]);
+
+	writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
+	writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
+	writel(denali_phy_params[341], &denali_phy[341]);
+
+	writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
+	writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
+	writel(denali_phy_params[469], &denali_phy[469]);
+
+	/*
+	 * phy_gtlvl_resp_wait_cnt_x
+	 * phy_gtlvl_dly_step_x
+	 * phy_wrlvl_resp_wait_cnt_x
+	 * phy_gtlvl_final_step_x
+	 * phy_gtlvl_back_step_x
+	 * phy_rdlvl_dly_step_x
+	 *
+	 * phy_master_delay_step_x
+	 * phy_master_delay_wait_x
+	 * phy_wrlvl_dly_step_x
+	 * phy_rptr_update_x
+	 * phy_wdqlvl_dly_step_x
+	 */
+	writel(denali_phy_params[87], &denali_phy[87]);
+	writel(denali_phy_params[88], &denali_phy[88]);
+	writel(denali_phy_params[89], &denali_phy[89]);
+	writel(denali_phy_params[90], &denali_phy[90]);
+
+	writel(denali_phy_params[215], &denali_phy[215]);
+	writel(denali_phy_params[216], &denali_phy[216]);
+	writel(denali_phy_params[217], &denali_phy[217]);
+	writel(denali_phy_params[218], &denali_phy[218]);
+
+	writel(denali_phy_params[343], &denali_phy[343]);
+	writel(denali_phy_params[344], &denali_phy[344]);
+	writel(denali_phy_params[345], &denali_phy[345]);
+	writel(denali_phy_params[346], &denali_phy[346]);
+
+	writel(denali_phy_params[471], &denali_phy[471]);
+	writel(denali_phy_params[472], &denali_phy[472]);
+	writel(denali_phy_params[473], &denali_phy[473]);
+	writel(denali_phy_params[474], &denali_phy[474]);
+
+	/*
+	 * phy_gtlvl_lat_adj_start_x
+	 * phy_gtlvl_rddqs_slv_dly_start_x
+	 * phy_rdlvl_rddqs_dq_slv_dly_start_x
+	 * phy_wdqlvl_dqdm_slv_dly_start_x
+	 */
+	writel(denali_phy_params[80], &denali_phy[80]);
+	writel(denali_phy_params[81], &denali_phy[81]);
+
+	writel(denali_phy_params[208], &denali_phy[208]);
+	writel(denali_phy_params[209], &denali_phy[209]);
+
+	writel(denali_phy_params[336], &denali_phy[336]);
+	writel(denali_phy_params[337], &denali_phy[337]);
+
+	writel(denali_phy_params[464], &denali_phy[464]);
+	writel(denali_phy_params[465], &denali_phy[465]);
+
+	/*
+	 * phy_master_delay_start_x
+	 * phy_sw_master_mode_x
+	 * phy_rddata_en_tsel_dly_x
+	 */
+	writel(denali_phy_params[86], &denali_phy[86]);
+	writel(denali_phy_params[214], &denali_phy[214]);
+	writel(denali_phy_params[342], &denali_phy[342]);
+	writel(denali_phy_params[470], &denali_phy[470]);
+
+	/*
+	 * phy_rddqz_slave_delay_x
+	 * phy_rddqs_dqz_fall_slave_delay_x
+	 * phy_rddqs_dqz_rise_slave_delay_x
+	 * phy_rddqs_dm_fall_slave_delay_x
+	 * phy_rddqs_dm_rise_slave_delay_x
+	 * phy_rddqs_gate_slave_delay_x
+	 * phy_wrlvl_delay_early_threshold_x
+	 * phy_write_path_lat_add_x
+	 * phy_rddqs_latency_adjust_x
+	 * phy_wrlvl_delay_period_threshold_x
+	 * phy_wrlvl_early_force_zero_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
+		    (67 - 63) * 4);
+	clrsetbits_le32(&denali_phy[68], 0xfffffc00,
+			denali_phy_params[68] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
+		    (79 - 68) * 4);
+	copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
+		    (195 - 191) * 4);
+	clrsetbits_le32(&denali_phy[196], 0xfffffc00,
+			denali_phy_params[196] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
+		    (207 - 196) * 4);
+	copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
+		    (323 - 319) * 4);
+	clrsetbits_le32(&denali_phy[324], 0xfffffc00,
+			denali_phy_params[324] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
+		    (335 - 324) * 4);
+
+	copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
+		    (451 - 447) * 4);
+	clrsetbits_le32(&denali_phy[452], 0xfffffc00,
+			denali_phy_params[452] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
+		    (463 - 452) * 4);
+
+	/* phy_two_cyc_preamble_x */
+	clrsetbits_le32(&denali_phy[7], 0x3 << 24,
+			denali_phy_params[7] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[135], 0x3 << 24,
+			denali_phy_params[135] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[263], 0x3 << 24,
+			denali_phy_params[263] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[391], 0x3 << 24,
+			denali_phy_params[391] & (0x3 << 24));
+
+	/* speed */
+	if (timings->base.ddr_freq < 400 * MHz)
+		speed = 0x0;
+	else if (timings->base.ddr_freq < 800 * MHz)
+		speed = 0x1;
+	else if (timings->base.ddr_freq < 1200 * MHz)
+		speed = 0x2;
+
+	/* phy_924 phy_pad_fdbk_drive */
+	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+	/* phy_926 phy_pad_data_drive */
+	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+	/* phy_927 phy_pad_dqs_drive */
+	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+	/* phy_928 phy_pad_addr_drive */
+	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+	/* phy_929 phy_pad_clk_drive */
+	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+	/* phy_935 phy_pad_cke_drive */
+	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+	/* phy_937 phy_pad_rst_drive */
+	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+	/* phy_939 phy_pad_cs_drive */
+	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+	read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
+	set_ds_odt(&dram->chan[channel], timings, true, mr5);
+
+	ctl = lpddr4_get_ctl(timings, phy);
+	set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
+
+	/*
+	 * if phy_sw_master_mode_x not bypass mode,
+	 * clear phy_slice_pwr_rdc_disable.
+	 * note: need use timings, not ddr_publ_regs
+	 */
+	if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
+		clrbits_le32(&denali_phy[10], 1 << 16);
+		clrbits_le32(&denali_phy[138], 1 << 16);
+		clrbits_le32(&denali_phy[266], 1 << 16);
+		clrbits_le32(&denali_phy[394], 1 << 16);
+	}
+
+	/*
+	 * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
+	 * smaller than 8
+	 * NOTE: need use timings, not ddr_publ_regs
+	 */
+	if ((denali_phy_params[84] >> 16) & 1) {
+		if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
+			clrsetbits_le32(&denali_ctl[217 + ctl],
+					0x1f << 16, 8 << 16);
+	}
+}
+
+static void lpddr4_set_phy(struct dram_info *dram,
+			   struct rk3399_sdram_params *params, u32 phy,
+			   struct rk3399_sdram_params *timings)
+{
+	u32 channel;
+
+	for (channel = 0; channel < 2; channel++)
+		lpddr4_copy_phy(dram, params, phy, timings, channel);
+}
+
+static int lpddr4_set_ctl(struct dram_info *dram,
+			  struct rk3399_sdram_params *params, u32 ctl, u32 hz)
+{
+	u32 channel;
+	int ret_clk, ret[2];
+
+	/* cci idle req stall */
+	writel(0x70007, &dram->grf->soc_con0);
+
+	/* enable all clk */
+	setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* idle */
+	setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+	       != (0x3 << 18))
+		;
+
+	/* change freq */
+	writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
+		(ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
+		;
+
+	ret_clk = clk_set_rate(&dram->ddr_clk, hz);
+	if (ret_clk < 0) {
+		printf("%s clk set failed %d\n", __func__, ret_clk);
+		return ret_clk;
+	}
+
+	writel(0x20002, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
+		;
+
+	/* deidle */
+	clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+		;
+
+	/* clear enable all clk */
+	clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* lpddr4 ctl2 can not do training, all training will fail */
+	if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			ret[channel] = data_training(dram, channel, params,
+						     PI_FULL_TRAINING);
+		}
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			if (ret[channel])
+				printf("%s: channel %d training failed!\n",
+				       __func__, channel);
+			else
+				debug("%s: channel %d training pass\n",
+				      __func__, channel);
+		}
+	}
+
+	return 0;
+}
+
+static int lpddr4_set_rate(struct dram_info *dram,
+			   struct rk3399_sdram_params *params)
+{
+	u32 ctl;
+	u32 phy;
+
+	for (ctl = 0; ctl < 2; ctl++) {
+		phy = lpddr4_get_phy(params, ctl);
+
+		lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
+		lpddr4_set_ctl(dram, params, ctl,
+			       lpddr4_timings[ctl].base.ddr_freq);
+
+		debug("%s: change freq to %d mhz %d, %d\n", __func__,
+		      lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
+	}
+
+	return 0;
+}
 #endif /* CONFIG_RAM_RK3399_LPDDR4 */
 
 static unsigned char calculate_stride(struct rk3399_sdram_params *params)

@@ -1993,6 +2644,7 @@ static const struct sdram_rk3399_ops rk3399_ops = {
 	.set_rate = switch_to_phy_index1,
 #else
 	.data_training = lpddr4_mr_detect,
+	.set_rate = lpddr4_set_rate,
 #endif
 };
 

@@ -2016,6 +2668,7 @@ static int rk3399_dmc_init(struct udevice *dev)
 	priv->ops = &rk3399_ops;
 	priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
 	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
 	priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
 	priv->pmucru = rockchip_get_pmucru();

@@ -2034,8 +2687,8 @@ static int rk3399_dmc_init(struct udevice *dev)
 	      priv->chan[0].publ, priv->chan[0].msch,
 	      priv->chan[1].pctl, priv->chan[1].pi,
 	      priv->chan[1].publ, priv->chan[1].msch);
-	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
-	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
+	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
 	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-53-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#150 lore raw

Re: [PATCH v3 52/57] ram: rk3399: Add lpddr4 set rate support

Quoted 27 lines · Jagan Teki

Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.

Here is sameple log about LPDDR4-100 init sequence in Rockpro64:

Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0

Quoted 5 lines

This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 788 lines
---
  drivers/ram/rockchip/sdram_rk3399.c | 677 +++++++++++++++++++++++++++-
  1 file changed, 665 insertions(+), 12 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +663 -10
index c3d7665ea2..3f29b5e0e8 100644
@@ -16,6 +16,7 @@
  #include <asm/arch-rockchip/clock.h>
  #include <asm/arch-rockchip/cru_rk3399.h>
  #include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/pmu_rk3399.h>
  #include <asm/arch-rockchip/hardware.h>
  #include <asm/arch-rockchip/sdram_common.h>
  #include <asm/arch-rockchip/sdram_rk3399.h>

@@ -62,6 +63,7 @@ struct dram_info {
  	struct clk ddr_clk;
  	struct rk3399_cru *cru;
  	struct rk3399_grf_regs *grf;
+	struct rk3399_pmu_regs *pmu;
  	struct rk3399_pmucru *pmucru;
  	struct rk3399_pmusgrf_regs *pmusgrf;
  	struct rk3399_ddr_cic_regs *cic;

@@ -75,7 +77,7 @@ struct sdram_rk3399_ops {
  	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
  			     struct rk3399_sdram_params *sdram);
  	int (*set_rate)(struct dram_info *dram,
-			const struct rk3399_sdram_params *params);
+			struct rk3399_sdram_params *params);
  };
 
  #if defined(CONFIG_TPL_BUILD) || \

@@ -221,6 +223,18 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
  	return io;
  }
 
+static void *get_denali_phy(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
+}
+
+static void *get_denali_ctl(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
+}
+
  static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  {
  	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

@@ -574,10 +588,11 @@ static int phy_io_config(const struct chan_info *chan,
  }
 
  static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *params, u32 mr5)
+		       struct rk3399_sdram_params *params,
+		       bool ctl_phy_reg, u32 mr5)
  {
-	u32 *denali_phy = chan->publ->denali_phy;
-	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_rd_select_p;
  	u32 tsel_idle_select_n, tsel_rd_select_n;

@@ -735,7 +750,8 @@ static void set_ds_odt(const struct chan_info *chan,
  	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 
  	/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
-	clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+	if (!ctl_phy_reg)
+		clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 
  	/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
  	clrsetbits_le32(&denali_phy[935], 0xff, reg_value);

@@ -919,7 +935,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
  	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
  	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, params, 0);
+	set_ds_odt(chan, params, true, 0);
 
  	/*
  	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8

@@ -950,7 +966,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	return 0;
  }
 
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
  static void select_per_cs_training_index(const struct chan_info *chan,
  					 u32 rank)
  {

@@ -1308,7 +1323,7 @@ static int data_training(struct dram_info *dram, u32 channel,
 
  	if (training_flag == PI_FULL_TRAINING) {
  		if (params->base.dramtype == LPDDR4) {
-			training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+			training_flag = PI_WRITE_LEVELING |
  					PI_READ_GATE_TRAINING |
  					PI_READ_LEVELING | PI_WDQ_LEVELING;
  		} else if (params->base.dramtype == LPDDR3) {

@@ -1371,7 +1386,6 @@ static int data_training(struct dram_info *dram, u32 channel,
 
  	return 0;
  }
-#endif
 
  static void set_ddrconfig(const struct chan_info *chan,
  			  const struct rk3399_sdram_params *params,

@@ -1493,7 +1507,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
  }
 
  static int switch_to_phy_index1(struct dram_info *dram,
-				const struct rk3399_sdram_params *params)
+				struct rk3399_sdram_params *params)
  {
  	u32 channel;
  	u32 *denali_phy;

@@ -1539,6 +1553,31 @@ static int switch_to_phy_index1(struct dram_info *dram,
 
  #else
 
+struct rk3399_sdram_params lpddr4_timings[] = {
+	#include "sdram-rk3399-lpddr4-400.inc"
+	#include "sdram-rk3399-lpddr4-800.inc"
+};
+
+static void *get_denali_pi(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pi->denali_pi : &params->pi_regs.denali_pi;
+}
+
+static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
+{
+	u32 lpddr4_phy[] = {1, 0, 0xb};
+
+	return lpddr4_phy[ctl];
+}
+
+static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
+{
+	u32 lpddr4_ctl[] = {1, 0, 2};
+
+	return lpddr4_ctl[phy];
+}
+
  static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
  {
  	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);

@@ -1756,6 +1795,618 @@ end:
 
  	return ret;
  }
+
+static void set_lpddr4_dq_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
+		break;
+	}
+}
+
+static void set_lpddr4_ca_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
+		break;
+	}
+}
+
+static void set_lpddr4_MR3(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, u32 ctl,
+			   bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = ((io->pdds << 3) | 1);
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
+		break;
+	}
+}
+
+static void set_lpddr4_MR12(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
+		break;
+	}
+}
+
+static void set_lpddr4_MR14(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
+		break;
+	}
+}
+
+static void lpddr4_copy_phy(struct dram_info *dram,
+			    struct rk3399_sdram_params *params, u32 phy,
+			    struct rk3399_sdram_params *timings,
+			    u32 channel)
+{
+	u32 *denali_ctl, *denali_phy;
+	u32 *denali_phy_params;
+	u32 speed = 0;
+	u32 ctl, mr5;
+
+	denali_ctl = dram->chan[channel].pctl->denali_ctl;
+	denali_phy = dram->chan[channel].publ->denali_phy;
+	denali_phy_params = timings->phy_regs.denali_phy;
+
+	/* switch index */
+	clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
+	writel(denali_phy_params[896], &denali_phy[896]);
+
+	/* phy_pll_ctrl_ca, phy_pll_ctrl */
+	writel(denali_phy_params[911], &denali_phy[911]);
+
+	/* phy_low_freq_sel */
+	clrsetbits_le32(&denali_phy[913], 0x1,
+			denali_phy_params[913] & 0x1);
+
+	/* phy_grp_slave_delay_x, phy_cslvl_dly_step */
+	writel(denali_phy_params[916], &denali_phy[916]);
+	writel(denali_phy_params[917], &denali_phy[917]);
+	writel(denali_phy_params[918], &denali_phy[918]);
+
+	/* phy_adrz_sw_wraddr_shift_x  */
+	writel(denali_phy_params[512], &denali_phy[512]);
+	clrsetbits_le32(&denali_phy[513], 0xffff,
+			denali_phy_params[513] & 0xffff);
+	writel(denali_phy_params[640], &denali_phy[640]);
+	clrsetbits_le32(&denali_phy[641], 0xffff,
+			denali_phy_params[641] & 0xffff);
+	writel(denali_phy_params[768], &denali_phy[768]);
+	clrsetbits_le32(&denali_phy[769], 0xffff,
+			denali_phy_params[769] & 0xffff);
+
+	writel(denali_phy_params[544], &denali_phy[544]);
+	writel(denali_phy_params[545], &denali_phy[545]);
+	writel(denali_phy_params[546], &denali_phy[546]);
+	writel(denali_phy_params[547], &denali_phy[547]);
+
+	writel(denali_phy_params[672], &denali_phy[672]);
+	writel(denali_phy_params[673], &denali_phy[673]);
+	writel(denali_phy_params[674], &denali_phy[674]);
+	writel(denali_phy_params[675], &denali_phy[675]);
+
+	writel(denali_phy_params[800], &denali_phy[800]);
+	writel(denali_phy_params[801], &denali_phy[801]);
+	writel(denali_phy_params[802], &denali_phy[802]);
+	writel(denali_phy_params[803], &denali_phy[803]);
+
+	/*
+	 * phy_adr_master_delay_start_x
+	 * phy_adr_master_delay_step_x
+	 * phy_adr_master_delay_wait_x
+	 */
+	writel(denali_phy_params[548], &denali_phy[548]);
+	writel(denali_phy_params[676], &denali_phy[676]);
+	writel(denali_phy_params[804], &denali_phy[804]);
+
+	/* phy_adr_calvl_dly_step_x */
+	writel(denali_phy_params[549], &denali_phy[549]);
+	writel(denali_phy_params[677], &denali_phy[677]);
+	writel(denali_phy_params[805], &denali_phy[805]);
+
+	/*
+	 * phy_clk_wrdm_slave_delay_x
+	 * phy_clk_wrdqz_slave_delay_x
+	 * phy_clk_wrdqs_slave_delay_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
+		    (63 - 58) * 4);
+	copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
+		    (191 - 186) * 4);
+	copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
+		    (319 - 314) * 4);
+	copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
+		    (447 - 442) * 4);
+
+	/*
+	 * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
+	 * dqs_tsel_wr_end[7:4] add half cycle
+	 * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
+	 * dq_tsel_wr_end[7:4] add half cycle
+	 */
+	writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
+	writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
+	writel(denali_phy_params[85], &denali_phy[85]);
+
+	writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
+	writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
+	writel(denali_phy_params[213], &denali_phy[213]);
+
+	writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
+	writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
+	writel(denali_phy_params[341], &denali_phy[341]);
+
+	writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
+	writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
+	writel(denali_phy_params[469], &denali_phy[469]);
+
+	/*
+	 * phy_gtlvl_resp_wait_cnt_x
+	 * phy_gtlvl_dly_step_x
+	 * phy_wrlvl_resp_wait_cnt_x
+	 * phy_gtlvl_final_step_x
+	 * phy_gtlvl_back_step_x
+	 * phy_rdlvl_dly_step_x
+	 *
+	 * phy_master_delay_step_x
+	 * phy_master_delay_wait_x
+	 * phy_wrlvl_dly_step_x
+	 * phy_rptr_update_x
+	 * phy_wdqlvl_dly_step_x
+	 */
+	writel(denali_phy_params[87], &denali_phy[87]);
+	writel(denali_phy_params[88], &denali_phy[88]);
+	writel(denali_phy_params[89], &denali_phy[89]);
+	writel(denali_phy_params[90], &denali_phy[90]);
+
+	writel(denali_phy_params[215], &denali_phy[215]);
+	writel(denali_phy_params[216], &denali_phy[216]);
+	writel(denali_phy_params[217], &denali_phy[217]);
+	writel(denali_phy_params[218], &denali_phy[218]);
+
+	writel(denali_phy_params[343], &denali_phy[343]);
+	writel(denali_phy_params[344], &denali_phy[344]);
+	writel(denali_phy_params[345], &denali_phy[345]);
+	writel(denali_phy_params[346], &denali_phy[346]);
+
+	writel(denali_phy_params[471], &denali_phy[471]);
+	writel(denali_phy_params[472], &denali_phy[472]);
+	writel(denali_phy_params[473], &denali_phy[473]);
+	writel(denali_phy_params[474], &denali_phy[474]);
+
+	/*
+	 * phy_gtlvl_lat_adj_start_x
+	 * phy_gtlvl_rddqs_slv_dly_start_x
+	 * phy_rdlvl_rddqs_dq_slv_dly_start_x
+	 * phy_wdqlvl_dqdm_slv_dly_start_x
+	 */
+	writel(denali_phy_params[80], &denali_phy[80]);
+	writel(denali_phy_params[81], &denali_phy[81]);
+
+	writel(denali_phy_params[208], &denali_phy[208]);
+	writel(denali_phy_params[209], &denali_phy[209]);
+
+	writel(denali_phy_params[336], &denali_phy[336]);
+	writel(denali_phy_params[337], &denali_phy[337]);
+
+	writel(denali_phy_params[464], &denali_phy[464]);
+	writel(denali_phy_params[465], &denali_phy[465]);
+
+	/*
+	 * phy_master_delay_start_x
+	 * phy_sw_master_mode_x
+	 * phy_rddata_en_tsel_dly_x
+	 */
+	writel(denali_phy_params[86], &denali_phy[86]);
+	writel(denali_phy_params[214], &denali_phy[214]);
+	writel(denali_phy_params[342], &denali_phy[342]);
+	writel(denali_phy_params[470], &denali_phy[470]);
+
+	/*
+	 * phy_rddqz_slave_delay_x
+	 * phy_rddqs_dqz_fall_slave_delay_x
+	 * phy_rddqs_dqz_rise_slave_delay_x
+	 * phy_rddqs_dm_fall_slave_delay_x
+	 * phy_rddqs_dm_rise_slave_delay_x
+	 * phy_rddqs_gate_slave_delay_x
+	 * phy_wrlvl_delay_early_threshold_x
+	 * phy_write_path_lat_add_x
+	 * phy_rddqs_latency_adjust_x
+	 * phy_wrlvl_delay_period_threshold_x
+	 * phy_wrlvl_early_force_zero_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
+		    (67 - 63) * 4);
+	clrsetbits_le32(&denali_phy[68], 0xfffffc00,
+			denali_phy_params[68] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
+		    (79 - 68) * 4);
+	copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
+		    (195 - 191) * 4);
+	clrsetbits_le32(&denali_phy[196], 0xfffffc00,
+			denali_phy_params[196] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
+		    (207 - 196) * 4);
+	copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
+		    (323 - 319) * 4);
+	clrsetbits_le32(&denali_phy[324], 0xfffffc00,
+			denali_phy_params[324] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
+		    (335 - 324) * 4);
+
+	copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
+		    (451 - 447) * 4);
+	clrsetbits_le32(&denali_phy[452], 0xfffffc00,
+			denali_phy_params[452] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
+		    (463 - 452) * 4);
+
+	/* phy_two_cyc_preamble_x */
+	clrsetbits_le32(&denali_phy[7], 0x3 << 24,
+			denali_phy_params[7] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[135], 0x3 << 24,
+			denali_phy_params[135] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[263], 0x3 << 24,
+			denali_phy_params[263] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[391], 0x3 << 24,
+			denali_phy_params[391] & (0x3 << 24));
+
+	/* speed */
+	if (timings->base.ddr_freq < 400 * MHz)
+		speed = 0x0;
+	else if (timings->base.ddr_freq < 800 * MHz)
+		speed = 0x1;
+	else if (timings->base.ddr_freq < 1200 * MHz)
+		speed = 0x2;
+
+	/* phy_924 phy_pad_fdbk_drive */
+	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+	/* phy_926 phy_pad_data_drive */
+	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+	/* phy_927 phy_pad_dqs_drive */
+	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+	/* phy_928 phy_pad_addr_drive */
+	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+	/* phy_929 phy_pad_clk_drive */
+	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+	/* phy_935 phy_pad_cke_drive */
+	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+	/* phy_937 phy_pad_rst_drive */
+	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+	/* phy_939 phy_pad_cs_drive */
+	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+	read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
+	set_ds_odt(&dram->chan[channel], timings, true, mr5);
+
+	ctl = lpddr4_get_ctl(timings, phy);
+	set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
+
+	/*
+	 * if phy_sw_master_mode_x not bypass mode,
+	 * clear phy_slice_pwr_rdc_disable.
+	 * note: need use timings, not ddr_publ_regs
+	 */
+	if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
+		clrbits_le32(&denali_phy[10], 1 << 16);
+		clrbits_le32(&denali_phy[138], 1 << 16);
+		clrbits_le32(&denali_phy[266], 1 << 16);
+		clrbits_le32(&denali_phy[394], 1 << 16);
+	}
+
+	/*
+	 * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
+	 * smaller than 8
+	 * NOTE: need use timings, not ddr_publ_regs
+	 */
+	if ((denali_phy_params[84] >> 16) & 1) {
+		if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
+			clrsetbits_le32(&denali_ctl[217 + ctl],
+					0x1f << 16, 8 << 16);
+	}
+}
+
+static void lpddr4_set_phy(struct dram_info *dram,
+			   struct rk3399_sdram_params *params, u32 phy,
+			   struct rk3399_sdram_params *timings)
+{
+	u32 channel;
+
+	for (channel = 0; channel < 2; channel++)
+		lpddr4_copy_phy(dram, params, phy, timings, channel);
+}
+
+static int lpddr4_set_ctl(struct dram_info *dram,
+			  struct rk3399_sdram_params *params, u32 ctl, u32 hz)
+{
+	u32 channel;
+	int ret_clk, ret[2];
+
+	/* cci idle req stall */
+	writel(0x70007, &dram->grf->soc_con0);
+
+	/* enable all clk */
+	setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* idle */
+	setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+	       != (0x3 << 18))
+		;
+
+	/* change freq */
+	writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
+		(ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
+		;
+
+	ret_clk = clk_set_rate(&dram->ddr_clk, hz);
+	if (ret_clk < 0) {
+		printf("%s clk set failed %d\n", __func__, ret_clk);
+		return ret_clk;
+	}
+
+	writel(0x20002, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
+		;
+
+	/* deidle */
+	clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+		;
+
+	/* clear enable all clk */
+	clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* lpddr4 ctl2 can not do training, all training will fail */
+	if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			ret[channel] = data_training(dram, channel, params,
+						     PI_FULL_TRAINING);
+		}
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			if (ret[channel])
+				printf("%s: channel %d training failed!\n",
+				       __func__, channel);
+			else
+				debug("%s: channel %d training pass\n",
+				      __func__, channel);
+		}
+	}
+
+	return 0;
+}
+
+static int lpddr4_set_rate(struct dram_info *dram,
+			   struct rk3399_sdram_params *params)
+{
+	u32 ctl;
+	u32 phy;
+
+	for (ctl = 0; ctl < 2; ctl++) {
+		phy = lpddr4_get_phy(params, ctl);
+
+		lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
+		lpddr4_set_ctl(dram, params, ctl,
+			       lpddr4_timings[ctl].base.ddr_freq);
+
+		debug("%s: change freq to %d mhz %d, %d\n", __func__,
+		      lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
+	}
+
+	return 0;
+}
  #endif /* CONFIG_RAM_RK3399_LPDDR4 */
 
  static unsigned char calculate_stride(struct rk3399_sdram_params *params)

@@ -1993,6 +2644,7 @@ static const struct sdram_rk3399_ops rk3399_ops = {
  	.set_rate = switch_to_phy_index1,
  #else
  	.data_training = lpddr4_mr_detect,
+	.set_rate = lpddr4_set_rate,
  #endif
  };
 

@@ -2016,6 +2668,7 @@ static int rk3399_dmc_init(struct udevice *dev)
  	priv->ops = &rk3399_ops;
  	priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
  	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
  	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  	priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  	priv->pmucru = rockchip_get_pmucru();

drivers/ram/rockchip/sdram_rk3399.c static int rk3399_dmc_init(struct udevice *dev) · line 2694

Quoted 10 lines
drivers/ram/rockchip/sdram_rk3399.c +2 -2
@@ -2034,8 +2687,8 @@ static int rk3399_dmc_init(struct udevice *dev)
  	      priv->chan[0].publ, priv->chan[0].msch,
  	      priv->chan[1].pctl, priv->chan[1].pi,
  	      priv->chan[1].publ, priv->chan[1].msch);
-	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
-	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
+	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
 
  #if CONFIG_IS_ENABLED(OF_PLATDATA)
  	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);

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#151 lore raw

PATCH v3 52/57 ram: rk3399: Add lpddr4 set rate support

In reply to Jagan Teki

Hi Jagan,

    This patch build fail with Travis, could you help to update and
send the fix to me:

https://travis-ci.org/keveryang/u-boot/jobs/560925061

   aarch64:  +   rockpro64-rk3399
+drivers/ram/rockchip/sdram_rk3399.c: In function 'lpddr4_set_rate':
+drivers/ram/rockchip/sdram_rk3399.c:2379:7: error: 'ret[1]' may be used uninitialized in this function [-Werror=maybe-uninitialized] +    if (ret[channel])
+       ^
+drivers/ram/rockchip/sdram_rk3399.c:2330:15: note: 'ret[1]' was declared here
+  int ret_clk, ret[2];
+               ^~~ +drivers/ram/rockchip/sdram_rk3399.c:2379:7: error: 'ret[0]' may be used uninitialized in this function [-Werror=maybe-uninitialized] +drivers/ram/rockchip/sdram_rk3399.c:2330:15: note: 'ret[0]' was declared here
+cc1: all warnings being treated as errors

Thanks,

- Kever

Quoted 830 lines · Jagan Teki

Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training.

The lpddr4 set rate sequnce will follow by setting lpddr4
- dq out
- ca odt
- MR3
- MR12
- MR14
registers sets in sequential order.

Here is sameple log about LPDDR4-100 init sequence in Rockpro64:

Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride
channel 0 training pass
channel 1 training pass
change freq to 400 MHz 0, 1
channel 0 training pass
channel 1 training pass
change freq to 800 MHz 1, 0

This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files.

Signed-off-by Jagan Teki <[email protected]>
Signed-off-by YouMin Chen <[email protected]>
---
  drivers/ram/rockchip/sdram_rk3399.c | 677 +++++++++++++++++++++++++++-
  1 file changed, 665 insertions(+), 12 deletions(-)
drivers/ram/rockchip/sdram_rk3399.c +665 -12
index c3d7665ea2..3f29b5e0e8 100644
@@ -16,6 +16,7 @@
  #include <asm/arch-rockchip/clock.h>
  #include <asm/arch-rockchip/cru_rk3399.h>
  #include <asm/arch-rockchip/grf_rk3399.h>
+#include <asm/arch-rockchip/pmu_rk3399.h>
  #include <asm/arch-rockchip/hardware.h>
  #include <asm/arch-rockchip/sdram_common.h>
  #include <asm/arch-rockchip/sdram_rk3399.h>

@@ -62,6 +63,7 @@ struct dram_info {
  	struct clk ddr_clk;
  	struct rk3399_cru *cru;
  	struct rk3399_grf_regs *grf;
+	struct rk3399_pmu_regs *pmu;
  	struct rk3399_pmucru *pmucru;
  	struct rk3399_pmusgrf_regs *pmusgrf;
  	struct rk3399_ddr_cic_regs *cic;

@@ -75,7 +77,7 @@ struct sdram_rk3399_ops {
  	int (*data_training)(struct dram_info *dram, u32 channel, u8 rank,
  			     struct rk3399_sdram_params *sdram);
  	int (*set_rate)(struct dram_info *dram,
-			const struct rk3399_sdram_params *params);
+			struct rk3399_sdram_params *params);
  };
 
  #if defined(CONFIG_TPL_BUILD) || \

@@ -221,6 +223,18 @@ lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
  	return io;
  }
 
+static void *get_denali_phy(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->publ->denali_phy : &params->phy_regs.denali_phy;
+}
+
+static void *get_denali_ctl(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pctl->denali_ctl : &params->pctl_regs.denali_ctl;
+}
+
  static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
  {
  	return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;

@@ -574,10 +588,11 @@ static int phy_io_config(const struct chan_info *chan,
  }
 
  static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *params, u32 mr5)
+		       struct rk3399_sdram_params *params,
+		       bool ctl_phy_reg, u32 mr5)
  {
-	u32 *denali_phy = chan->publ->denali_phy;
-	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_rd_select_p;
  	u32 tsel_idle_select_n, tsel_rd_select_n;

@@ -735,7 +750,8 @@ static void set_ds_odt(const struct chan_info *chan,
  	clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
 
  	/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
-	clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
+	if (!ctl_phy_reg)
+		clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
 
  	/* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
  	clrsetbits_le32(&denali_phy[935], 0xff, reg_value);

@@ -919,7 +935,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
  	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
  	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, params, 0);
+	set_ds_odt(chan, params, true, 0);
 
  	/*
  	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8

@@ -950,7 +966,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
  	return 0;
  }
 
-#if !defined(CONFIG_RAM_RK3399_LPDDR4)
  static void select_per_cs_training_index(const struct chan_info *chan,
  					 u32 rank)
  {

@@ -1308,7 +1323,7 @@ static int data_training(struct dram_info *dram, u32 channel,
 
  	if (training_flag == PI_FULL_TRAINING) {
  		if (params->base.dramtype == LPDDR4) {
-			training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
+			training_flag = PI_WRITE_LEVELING |
  					PI_READ_GATE_TRAINING |
  					PI_READ_LEVELING | PI_WDQ_LEVELING;
  		} else if (params->base.dramtype == LPDDR3) {

@@ -1371,7 +1386,6 @@ static int data_training(struct dram_info *dram, u32 channel,
 
  	return 0;
  }
-#endif
 
  static void set_ddrconfig(const struct chan_info *chan,
  			  const struct rk3399_sdram_params *params,

@@ -1493,7 +1507,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
  }
 
  static int switch_to_phy_index1(struct dram_info *dram,
-				const struct rk3399_sdram_params *params)
+				struct rk3399_sdram_params *params)
  {
  	u32 channel;
  	u32 *denali_phy;

@@ -1539,6 +1553,31 @@ static int switch_to_phy_index1(struct dram_info *dram,
 
  #else
 
+struct rk3399_sdram_params lpddr4_timings[] = {
+	#include "sdram-rk3399-lpddr4-400.inc"
+	#include "sdram-rk3399-lpddr4-800.inc"
+};
+
+static void *get_denali_pi(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, bool reg)
+{
+	return reg ? &chan->pi->denali_pi : &params->pi_regs.denali_pi;
+}
+
+static u32 lpddr4_get_phy(struct rk3399_sdram_params *params, u32 ctl)
+{
+	u32 lpddr4_phy[] = {1, 0, 0xb};
+
+	return lpddr4_phy[ctl];
+}
+
+static u32 lpddr4_get_ctl(struct rk3399_sdram_params *params, u32 phy)
+{
+	u32 lpddr4_ctl[] = {1, 0, 2};
+
+	return lpddr4_ctl[phy];
+}
+
  static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
  {
  	return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);

@@ -1756,6 +1795,618 @@ end:
 
  	return ret;
  }
+
+static void set_lpddr4_dq_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
+		clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
+		clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
+		break;
+	}
+}
+
+static void set_lpddr4_ca_odt(const struct chan_info *chan,
+			      struct rk3399_sdram_params *params, u32 ctl,
+			      bool en, bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	if (!en)
+		return;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_odt;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
+		clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
+
+		clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
+
+		clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
+		clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
+
+		clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
+		clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
+		clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
+		break;
+	}
+}
+
+static void set_lpddr4_MR3(const struct chan_info *chan,
+			   struct rk3399_sdram_params *params, u32 ctl,
+			   bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = ((io->pdds << 3) | 1);
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
+		break;
+	}
+}
+
+static void set_lpddr4_MR12(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->ca_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
+		clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
+		break;
+	}
+}
+
+static void set_lpddr4_MR14(const struct chan_info *chan,
+			    struct rk3399_sdram_params *params, u32 ctl,
+			    bool ctl_phy_reg, u32 mr5)
+{
+	u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
+	u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
+	struct io_setting *io;
+	u32 reg_value;
+
+	io = lpddr4_get_io_settings(params, mr5);
+
+	reg_value = io->dq_vref;
+
+	switch (ctl) {
+	case 0:
+		clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
+		break;
+	case 1:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
+
+		clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
+		break;
+	case 2:
+	default:
+		clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
+				reg_value << 16);
+		clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
+				reg_value << 16);
+
+		clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
+		clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
+		clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
+		break;
+	}
+}
+
+static void lpddr4_copy_phy(struct dram_info *dram,
+			    struct rk3399_sdram_params *params, u32 phy,
+			    struct rk3399_sdram_params *timings,
+			    u32 channel)
+{
+	u32 *denali_ctl, *denali_phy;
+	u32 *denali_phy_params;
+	u32 speed = 0;
+	u32 ctl, mr5;
+
+	denali_ctl = dram->chan[channel].pctl->denali_ctl;
+	denali_phy = dram->chan[channel].publ->denali_phy;
+	denali_phy_params = timings->phy_regs.denali_phy;
+
+	/* switch index */
+	clrsetbits_le32(&denali_phy_params[896], 0x3 << 8, phy << 8);
+	writel(denali_phy_params[896], &denali_phy[896]);
+
+	/* phy_pll_ctrl_ca, phy_pll_ctrl */
+	writel(denali_phy_params[911], &denali_phy[911]);
+
+	/* phy_low_freq_sel */
+	clrsetbits_le32(&denali_phy[913], 0x1,
+			denali_phy_params[913] & 0x1);
+
+	/* phy_grp_slave_delay_x, phy_cslvl_dly_step */
+	writel(denali_phy_params[916], &denali_phy[916]);
+	writel(denali_phy_params[917], &denali_phy[917]);
+	writel(denali_phy_params[918], &denali_phy[918]);
+
+	/* phy_adrz_sw_wraddr_shift_x  */
+	writel(denali_phy_params[512], &denali_phy[512]);
+	clrsetbits_le32(&denali_phy[513], 0xffff,
+			denali_phy_params[513] & 0xffff);
+	writel(denali_phy_params[640], &denali_phy[640]);
+	clrsetbits_le32(&denali_phy[641], 0xffff,
+			denali_phy_params[641] & 0xffff);
+	writel(denali_phy_params[768], &denali_phy[768]);
+	clrsetbits_le32(&denali_phy[769], 0xffff,
+			denali_phy_params[769] & 0xffff);
+
+	writel(denali_phy_params[544], &denali_phy[544]);
+	writel(denali_phy_params[545], &denali_phy[545]);
+	writel(denali_phy_params[546], &denali_phy[546]);
+	writel(denali_phy_params[547], &denali_phy[547]);
+
+	writel(denali_phy_params[672], &denali_phy[672]);
+	writel(denali_phy_params[673], &denali_phy[673]);
+	writel(denali_phy_params[674], &denali_phy[674]);
+	writel(denali_phy_params[675], &denali_phy[675]);
+
+	writel(denali_phy_params[800], &denali_phy[800]);
+	writel(denali_phy_params[801], &denali_phy[801]);
+	writel(denali_phy_params[802], &denali_phy[802]);
+	writel(denali_phy_params[803], &denali_phy[803]);
+
+	/*
+	 * phy_adr_master_delay_start_x
+	 * phy_adr_master_delay_step_x
+	 * phy_adr_master_delay_wait_x
+	 */
+	writel(denali_phy_params[548], &denali_phy[548]);
+	writel(denali_phy_params[676], &denali_phy[676]);
+	writel(denali_phy_params[804], &denali_phy[804]);
+
+	/* phy_adr_calvl_dly_step_x */
+	writel(denali_phy_params[549], &denali_phy[549]);
+	writel(denali_phy_params[677], &denali_phy[677]);
+	writel(denali_phy_params[805], &denali_phy[805]);
+
+	/*
+	 * phy_clk_wrdm_slave_delay_x
+	 * phy_clk_wrdqz_slave_delay_x
+	 * phy_clk_wrdqs_slave_delay_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[59], (u32 *)&denali_phy_params[59],
+		    (63 - 58) * 4);
+	copy_to_reg((u32 *)&denali_phy[187], (u32 *)&denali_phy_params[187],
+		    (191 - 186) * 4);
+	copy_to_reg((u32 *)&denali_phy[315], (u32 *)&denali_phy_params[315],
+		    (319 - 314) * 4);
+	copy_to_reg((u32 *)&denali_phy[443], (u32 *)&denali_phy_params[443],
+		    (447 - 442) * 4);
+
+	/*
+	 * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
+	 * dqs_tsel_wr_end[7:4] add half cycle
+	 * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
+	 * dq_tsel_wr_end[7:4] add half cycle
+	 */
+	writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
+	writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
+	writel(denali_phy_params[85], &denali_phy[85]);
+
+	writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
+	writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
+	writel(denali_phy_params[213], &denali_phy[213]);
+
+	writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
+	writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
+	writel(denali_phy_params[341], &denali_phy[341]);
+
+	writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
+	writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
+	writel(denali_phy_params[469], &denali_phy[469]);
+
+	/*
+	 * phy_gtlvl_resp_wait_cnt_x
+	 * phy_gtlvl_dly_step_x
+	 * phy_wrlvl_resp_wait_cnt_x
+	 * phy_gtlvl_final_step_x
+	 * phy_gtlvl_back_step_x
+	 * phy_rdlvl_dly_step_x
+	 *
+	 * phy_master_delay_step_x
+	 * phy_master_delay_wait_x
+	 * phy_wrlvl_dly_step_x
+	 * phy_rptr_update_x
+	 * phy_wdqlvl_dly_step_x
+	 */
+	writel(denali_phy_params[87], &denali_phy[87]);
+	writel(denali_phy_params[88], &denali_phy[88]);
+	writel(denali_phy_params[89], &denali_phy[89]);
+	writel(denali_phy_params[90], &denali_phy[90]);
+
+	writel(denali_phy_params[215], &denali_phy[215]);
+	writel(denali_phy_params[216], &denali_phy[216]);
+	writel(denali_phy_params[217], &denali_phy[217]);
+	writel(denali_phy_params[218], &denali_phy[218]);
+
+	writel(denali_phy_params[343], &denali_phy[343]);
+	writel(denali_phy_params[344], &denali_phy[344]);
+	writel(denali_phy_params[345], &denali_phy[345]);
+	writel(denali_phy_params[346], &denali_phy[346]);
+
+	writel(denali_phy_params[471], &denali_phy[471]);
+	writel(denali_phy_params[472], &denali_phy[472]);
+	writel(denali_phy_params[473], &denali_phy[473]);
+	writel(denali_phy_params[474], &denali_phy[474]);
+
+	/*
+	 * phy_gtlvl_lat_adj_start_x
+	 * phy_gtlvl_rddqs_slv_dly_start_x
+	 * phy_rdlvl_rddqs_dq_slv_dly_start_x
+	 * phy_wdqlvl_dqdm_slv_dly_start_x
+	 */
+	writel(denali_phy_params[80], &denali_phy[80]);
+	writel(denali_phy_params[81], &denali_phy[81]);
+
+	writel(denali_phy_params[208], &denali_phy[208]);
+	writel(denali_phy_params[209], &denali_phy[209]);
+
+	writel(denali_phy_params[336], &denali_phy[336]);
+	writel(denali_phy_params[337], &denali_phy[337]);
+
+	writel(denali_phy_params[464], &denali_phy[464]);
+	writel(denali_phy_params[465], &denali_phy[465]);
+
+	/*
+	 * phy_master_delay_start_x
+	 * phy_sw_master_mode_x
+	 * phy_rddata_en_tsel_dly_x
+	 */
+	writel(denali_phy_params[86], &denali_phy[86]);
+	writel(denali_phy_params[214], &denali_phy[214]);
+	writel(denali_phy_params[342], &denali_phy[342]);
+	writel(denali_phy_params[470], &denali_phy[470]);
+
+	/*
+	 * phy_rddqz_slave_delay_x
+	 * phy_rddqs_dqz_fall_slave_delay_x
+	 * phy_rddqs_dqz_rise_slave_delay_x
+	 * phy_rddqs_dm_fall_slave_delay_x
+	 * phy_rddqs_dm_rise_slave_delay_x
+	 * phy_rddqs_gate_slave_delay_x
+	 * phy_wrlvl_delay_early_threshold_x
+	 * phy_write_path_lat_add_x
+	 * phy_rddqs_latency_adjust_x
+	 * phy_wrlvl_delay_period_threshold_x
+	 * phy_wrlvl_early_force_zero_x
+	 */
+	copy_to_reg((u32 *)&denali_phy[64], (u32 *)&denali_phy_params[64],
+		    (67 - 63) * 4);
+	clrsetbits_le32(&denali_phy[68], 0xfffffc00,
+			denali_phy_params[68] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[69], (u32 *)&denali_phy_params[69],
+		    (79 - 68) * 4);
+	copy_to_reg((u32 *)&denali_phy[192], (u32 *)&denali_phy_params[192],
+		    (195 - 191) * 4);
+	clrsetbits_le32(&denali_phy[196], 0xfffffc00,
+			denali_phy_params[196] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[197], (u32 *)&denali_phy_params[197],
+		    (207 - 196) * 4);
+	copy_to_reg((u32 *)&denali_phy[320], (u32 *)&denali_phy_params[320],
+		    (323 - 319) * 4);
+	clrsetbits_le32(&denali_phy[324], 0xfffffc00,
+			denali_phy_params[324] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[325], (u32 *)&denali_phy_params[325],
+		    (335 - 324) * 4);
+
+	copy_to_reg((u32 *)&denali_phy[448], (u32 *)&denali_phy_params[448],
+		    (451 - 447) * 4);
+	clrsetbits_le32(&denali_phy[452], 0xfffffc00,
+			denali_phy_params[452] & 0xfffffc00);
+	copy_to_reg((u32 *)&denali_phy[453], (u32 *)&denali_phy_params[453],
+		    (463 - 452) * 4);
+
+	/* phy_two_cyc_preamble_x */
+	clrsetbits_le32(&denali_phy[7], 0x3 << 24,
+			denali_phy_params[7] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[135], 0x3 << 24,
+			denali_phy_params[135] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[263], 0x3 << 24,
+			denali_phy_params[263] & (0x3 << 24));
+	clrsetbits_le32(&denali_phy[391], 0x3 << 24,
+			denali_phy_params[391] & (0x3 << 24));
+
+	/* speed */
+	if (timings->base.ddr_freq < 400 * MHz)
+		speed = 0x0;
+	else if (timings->base.ddr_freq < 800 * MHz)
+		speed = 0x1;
+	else if (timings->base.ddr_freq < 1200 * MHz)
+		speed = 0x2;
+
+	/* phy_924 phy_pad_fdbk_drive */
+	clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
+	/* phy_926 phy_pad_data_drive */
+	clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
+	/* phy_927 phy_pad_dqs_drive */
+	clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
+	/* phy_928 phy_pad_addr_drive */
+	clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
+	/* phy_929 phy_pad_clk_drive */
+	clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
+	/* phy_935 phy_pad_cke_drive */
+	clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
+	/* phy_937 phy_pad_rst_drive */
+	clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
+	/* phy_939 phy_pad_cs_drive */
+	clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
+
+	read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
+	set_ds_odt(&dram->chan[channel], timings, true, mr5);
+
+	ctl = lpddr4_get_ctl(timings, phy);
+	set_lpddr4_dq_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_ca_odt(&dram->chan[channel], timings, ctl, true, true, mr5);
+	set_lpddr4_MR3(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR12(&dram->chan[channel], timings, ctl, true, mr5);
+	set_lpddr4_MR14(&dram->chan[channel], timings, ctl, true, mr5);
+
+	/*
+	 * if phy_sw_master_mode_x not bypass mode,
+	 * clear phy_slice_pwr_rdc_disable.
+	 * note: need use timings, not ddr_publ_regs
+	 */
+	if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
+		clrbits_le32(&denali_phy[10], 1 << 16);
+		clrbits_le32(&denali_phy[138], 1 << 16);
+		clrbits_le32(&denali_phy[266], 1 << 16);
+		clrbits_le32(&denali_phy[394], 1 << 16);
+	}
+
+	/*
+	 * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
+	 * smaller than 8
+	 * NOTE: need use timings, not ddr_publ_regs
+	 */
+	if ((denali_phy_params[84] >> 16) & 1) {
+		if (((readl(&denali_ctl[217 + ctl]) >> 16) & 0x1f) < 8)
+			clrsetbits_le32(&denali_ctl[217 + ctl],
+					0x1f << 16, 8 << 16);
+	}
+}
+
+static void lpddr4_set_phy(struct dram_info *dram,
+			   struct rk3399_sdram_params *params, u32 phy,
+			   struct rk3399_sdram_params *timings)
+{
+	u32 channel;
+
+	for (channel = 0; channel < 2; channel++)
+		lpddr4_copy_phy(dram, params, phy, timings, channel);
+}
+
+static int lpddr4_set_ctl(struct dram_info *dram,
+			  struct rk3399_sdram_params *params, u32 ctl, u32 hz)
+{
+	u32 channel;
+	int ret_clk, ret[2];
+
+	/* cci idle req stall */
+	writel(0x70007, &dram->grf->soc_con0);
+
+	/* enable all clk */
+	setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* idle */
+	setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+	       != (0x3 << 18))
+		;
+
+	/* change freq */
+	writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
+		(ctl << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
+		;
+
+	ret_clk = clk_set_rate(&dram->ddr_clk, hz);
+	if (ret_clk < 0) {
+		printf("%s clk set failed %d\n", __func__, ret_clk);
+		return ret_clk;
+	}
+
+	writel(0x20002, &dram->cic->cic_ctrl0);
+	while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
+		;
+
+	/* deidle */
+	clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
+	while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
+		;
+
+	/* clear enable all clk */
+	clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
+
+	/* lpddr4 ctl2 can not do training, all training will fail */
+	if (!(params->base.dramtype == LPDDR4 && ctl == 2)) {
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			ret[channel] = data_training(dram, channel, params,
+						     PI_FULL_TRAINING);
+		}
+		for (channel = 0; channel < 2; channel++) {
+			if (!(params->ch[channel].cap_info.col))
+				continue;
+			if (ret[channel])
+				printf("%s: channel %d training failed!\n",
+				       __func__, channel);
+			else
+				debug("%s: channel %d training pass\n",
+				      __func__, channel);
+		}
+	}
+
+	return 0;
+}
+
+static int lpddr4_set_rate(struct dram_info *dram,
+			   struct rk3399_sdram_params *params)
+{
+	u32 ctl;
+	u32 phy;
+
+	for (ctl = 0; ctl < 2; ctl++) {
+		phy = lpddr4_get_phy(params, ctl);
+
+		lpddr4_set_phy(dram, params, phy, &lpddr4_timings[ctl]);
+		lpddr4_set_ctl(dram, params, ctl,
+			       lpddr4_timings[ctl].base.ddr_freq);
+
+		debug("%s: change freq to %d mhz %d, %d\n", __func__,
+		      lpddr4_timings[ctl].base.ddr_freq / MHz, ctl, phy);
+	}
+
+	return 0;
+}
  #endif /* CONFIG_RAM_RK3399_LPDDR4 */
 
  static unsigned char calculate_stride(struct rk3399_sdram_params *params)

@@ -1993,6 +2644,7 @@ static const struct sdram_rk3399_ops rk3399_ops = {
  	.set_rate = switch_to_phy_index1,
  #else
  	.data_training = lpddr4_mr_detect,
+	.set_rate = lpddr4_set_rate,
  #endif
  };
 

@@ -2016,6 +2668,7 @@ static int rk3399_dmc_init(struct udevice *dev)
  	priv->ops = &rk3399_ops;
  	priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
  	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
  	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  	priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
  	priv->pmucru = rockchip_get_pmucru();

@@ -2034,8 +2687,8 @@ static int rk3399_dmc_init(struct udevice *dev)
  	      priv->chan[0].publ, priv->chan[0].msch,
  	      priv->chan[1].pctl, priv->chan[1].pi,
  	      priv->chan[1].publ, priv->chan[1].msch);
-	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
-	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
+	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
 
  #if CONFIG_IS_ENABLED(OF_PLATDATA)
  	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
#152 lore raw

PATCH v3 53/57 configs: rockpro64: Enable LPDDR4 support

In reply to a message not in the archive

Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4.

So, enable it for Rockpro64 board.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 configs/rockpro64-rk3399_defconfig | 1 +
 1 file changed, 1 insertion(+)
configs/rockpro64-rk3399_defconfig +1 -0
index e8fc7ae141..39e68aad82 100644
@@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-54-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#154 lore raw

Re: [PATCH v3 53/57] configs: rockpro64: Enable LPDDR4 support

Quoted 6 lines · Jagan Teki

Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4.

So, enable it for Rockpro64 board.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  configs/rockpro64-rk3399_defconfig | 1 +
  1 file changed, 1 insertion(+)
configs/rockpro64-rk3399_defconfig +0 -0
index e8fc7ae141..39e68aad82 100644

configs/rockpro64-rk3399_defconfig CONFIG_SPL_OF_CONTROL=y · line 34

Quoted 7 lines
configs/rockpro64-rk3399_defconfig +1 -0
@@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y
  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rockpro64"
  CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
  CONFIG_ENV_IS_IN_MMC=y
+CONFIG_RAM_RK3399_LPDDR4=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
  CONFIG_MMC_DW=y

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#155 lore raw

PATCH v3 54/57 configs: rock-pi-4: Enable LPDDR4 support

In reply to a message not in the archive

Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4.

So, enable it for Rock-PI-4 board.

Signed-off-by Jagan Teki <jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
---
 configs/rock-pi-4-rk3399_defconfig | 1 +
 1 file changed, 1 insertion(+)
configs/rock-pi-4-rk3399_defconfig +1 -0
index be670df23f..c6fc9b995d 100644
@@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_RAM_RK3399_LPDDR4=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
 CONFIG_MMC_DW=y
Signature · 1 line
2.18.0.321.gffc6fa0e3

A message that is not in the archive (sent off-list or not yet received): 20190716115745.12585-55-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org

Reviewed-by
#157 lore raw

Re: [PATCH v3 54/57] configs: rock-pi-4: Enable LPDDR4 support

Quoted 6 lines · Jagan Teki

Due to foot-print issues, we have LPDDR4 code can be marked as CONFIG_RAM_RK3399_LPDDR4.

So, enable it for Rock-PI-4 board.

Signed-off-by Jagan Teki <[email protected]>
Reviewed-by Kever Yang <[email protected]>

Thanks,
 - Kever

Quoted 9 lines
---
  configs/rock-pi-4-rk3399_defconfig | 1 +
  1 file changed, 1 insertion(+)
configs/rock-pi-4-rk3399_defconfig +0 -0
index be670df23f..c6fc9b995d 100644

configs/rock-pi-4-rk3399_defconfig CONFIG_SPL_OF_CONTROL=y · line 34

Quoted 7 lines
configs/rock-pi-4-rk3399_defconfig +1 -0
@@ -28,6 +28,7 @@ CONFIG_SPL_OF_CONTROL=y
  CONFIG_DEFAULT_DEVICE_TREE="rk3399-rock-pi-4"
  CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
  CONFIG_ENV_IS_IN_MMC=y
+CONFIG_RAM_RK3399_LPDDR4=y
  CONFIG_ROCKCHIP_GPIO=y
  CONFIG_SYS_I2C_ROCKCHIP=y
  CONFIG_MMC_DW=y

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