arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG, ERG}
Will Deacon
maintainerPATCH 1/1 arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG, ERG}
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of FTR_HIGHER_SAFE when sanitising CPU ID registers on heterogeneous machines.
Introduce FTR_HIGHER_OR_ZERO_SAFE so that these fields effectively saturate at zero.
--- arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 8 ++++++-- 2 files changed, 10 insertions(+), 5 deletions(-)
arch/arm64/include/asm/cpufeature.h +4 -3
@@ -35,9 +35,10 @@*/ enum ftr_type { -FTR_EXACT ,/* Use a predefined safe value */ -FTR_LOWER_SAFE ,/* Smaller value is safe */ -FTR_HIGHER_SAFE ,/* Bigger value is safe */ +FTR_EXACT ,/* Use a predefined safe value */ +FTR_LOWER_SAFE ,/* Smaller value is safe */ +FTR_HIGHER_SAFE ,/* Bigger value is safe */ +FTR_HIGHER_OR_ZERO_SAFE ,/* Bigger value is safe, but 0 is biggest */ };#define FTR_STRICT true/* SANITY check strict matching required */
arch/arm64/kernel/cpufeature.c +6 -2
@@ -225,8 +225,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = {ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_EXACT ,31 ,1 ,1 ),/* RES1 */ ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_DIC_SHIFT ,1 ,1 ),ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_IDC_SHIFT ,1 ,1 ), -ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_SAFE ,CTR_CWG_SHIFT ,4 ,0 ), -ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_SAFE ,CTR_ERG_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_OR_ZERO_SAFE ,CTR_CWG_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_OR_ZERO_SAFE ,CTR_ERG_SHIFT ,4 ,0 ),ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_DMINLINE_SHIFT ,4 ,1 ),/* * Linux can handle differing I-cache policies. Userspace JITs will
@@ -468,6 +468,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,case FTR_LOWER_SAFE : ret = new < cur ? new : cur;break ; +case FTR_HIGHER_OR_ZERO_SAFE : +if (!cur || !new) +break ; +/* Fallthrough */ case FTR_HIGHER_SAFE : ret = new > cur ? new : cur;break ;
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2.11.0 _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
Quoted 11 lines · Will Deacon
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of
FTR_HIGHER_SAFEwhen sanitising CPU ID registers on heterogeneous machines.Introduce
FTR_HIGHER_OR_ZERO_SAFEso that these fields effectively saturate at zero.Cc Suzuki Poulose <[email protected]>Fixes 3c739b571084 ("arm64: Keep track of CPU feature registers")Signed-off-by Will Deacon <[email protected]>
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Quoted 22 lines · Will Deacon
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of
FTR_HIGHER_SAFEwhen sanitising CPU ID registers on heterogeneous machines.Introduce
FTR_HIGHER_OR_ZERO_SAFEso that these fields effectively saturate at zero.Cc Suzuki Poulose <[email protected]>Fixes 3c739b571084 ("arm64: Keep track of CPU feature registers")Signed-off-by Will Deacon <[email protected]>--- arch/arm64/include/asm/cpufeature.h | 7 ++++--- arch/arm64/kernel/cpufeature.c | 8 ++++++-- 2 files changed, 10 insertions(+), 5 deletions(-)arch/arm64/include/asm/cpufeature.h +0
-0@@ -35,9 +35,10 @@*/
arch/arm64/include/asm/cpufeature.h line 42
Quoted 10 lines
arch/arm64/include/asm/cpufeature.h +4
-3enum ftr_type { -FTR_EXACT ,/* Use a predefined safe value */ -FTR_LOWER_SAFE ,/* Smaller value is safe */ -FTR_HIGHER_SAFE ,/* Bigger value is safe */ +FTR_EXACT ,/* Use a predefined safe value */ +FTR_LOWER_SAFE ,/* Smaller value is safe */ +FTR_HIGHER_SAFE ,/* Bigger value is safe */ +FTR_HIGHER_OR_ZERO_SAFE ,/* Bigger value is safe, but 0 is biggest */ };
Does this mean we've disproved the FUTEX_MAX_LOOPS conjecture? ;)
FWIW:
Mark.
Quoted 36 lines
arch/arm64/include/asm/cpufeature.h +0
-0#define FTR_STRICT true/* SANITY check strict matching required */ arch/arm64/kernel/cpufeature.c +6
-2@@ -225,8 +225,8 @@ static const struct arm64_ftr_bits ftr_ctr[] = {ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_EXACT ,31 ,1 ,1 ),/* RES1 */ ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_DIC_SHIFT ,1 ,1 ),ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_IDC_SHIFT ,1 ,1 ), -ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_SAFE ,CTR_CWG_SHIFT ,4 ,0 ), -ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_SAFE ,CTR_ERG_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_OR_ZERO_SAFE ,CTR_CWG_SHIFT ,4 ,0 ), +ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_HIGHER_OR_ZERO_SAFE ,CTR_ERG_SHIFT ,4 ,0 ),ARM64_FTR_BITS (FTR_VISIBLE ,FTR_STRICT ,FTR_LOWER_SAFE ,CTR_DMINLINE_SHIFT ,4 ,1 ),/* * Linux can handle differing I-cache policies. Userspace JITs will @@ -468,6 +468,10 @@ static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,case FTR_LOWER_SAFE : ret = new < cur ? new : cur;break ; +case FTR_HIGHER_OR_ZERO_SAFE : +if (!cur || !new) +break ; +/* Fallthrough */ case FTR_HIGHER_SAFE : ret = new > cur ? new : cur;break ;Signature · 7 lines
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Re: [PATCH] arm64: cpufeature: Fix feature comparison for CTR_EL0.{CWG,ERG}
In reply to Will DeaconQuoted 11 lines · Will Deacon
If CTR_EL0.{CWG,ERG} are 0b0000 then they must be interpreted to have their architecturally maximum values, which defeats the use of
FTR_HIGHER_SAFEwhen sanitising CPU ID registers on heterogeneous machines.Introduce
FTR_HIGHER_OR_ZERO_SAFEso that these fields effectively saturate at zero.Cc Suzuki Poulose <[email protected]>Fixes 3c739b571084 ("arm64: Keep track of CPU feature registers")Signed-off-by Will Deacon <[email protected]>
Queued for 5.3-rc3 (with a cc stable tag). Thanks.
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